2006-11-28 00:16:29 +03:00
/*
* Lite5200 board Device Tree Source
*
2007-02-12 23:36:54 +03:00
* Copyright 2006-2007 Secret Lab Technologies Ltd.
2006-11-28 00:16:29 +03:00
* Grant Likely <grant.likely@secretlab.ca>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
2008-04-29 17:19:07 +04:00
/dts-v1/;
2006-11-28 00:16:29 +03:00
/ {
2007-02-12 23:36:54 +03:00
model = "fsl,lite5200";
2007-11-15 14:40:21 +03:00
compatible = "fsl,lite5200";
2006-11-28 00:16:29 +03:00
#address-cells = <1>;
#size-cells = <1>;
2009-02-03 22:30:26 +03:00
interrupt-parent = <&mpc5200_pic>;
2006-11-28 00:16:29 +03:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
2008-04-29 17:19:07 +04:00
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
2006-11-28 00:16:29 +03:00
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
2008-04-29 17:19:07 +04:00
reg = <0x00000000 0x04000000>; // 64MB
2006-11-28 00:16:29 +03:00
};
soc5200@f0000000 {
2008-01-25 23:33:20 +03:00
#address-cells = <1>;
#size-cells = <1>;
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-immr";
2008-04-29 17:19:07 +04:00
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
2006-11-28 00:16:29 +03:00
bus-frequency = <0>; // from bootloader
2007-02-12 23:36:54 +03:00
system-frequency = <0>; // from bootloader
2006-11-28 00:16:29 +03:00
cdm@200 {
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-cdm";
2008-04-29 17:19:07 +04:00
reg = <0x200 0x38>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
mpc5200_pic: interrupt-controller@500 {
2006-11-28 00:16:29 +03:00
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-pic";
2008-04-29 17:19:07 +04:00
reg = <0x500 0x80>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@600 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x600 0x10>;
2006-11-28 00:16:29 +03:00
interrupts = <1 9 0>;
2007-10-18 22:44:24 +04:00
fsl,has-wdt;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@610 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x610 0x10>;
interrupts = <1 10 0>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@620 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x620 0x10>;
interrupts = <1 11 0>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@630 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x630 0x10>;
interrupts = <1 12 0>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@640 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x640 0x10>;
interrupts = <1 13 0>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@650 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x650 0x10>;
interrupts = <1 14 0>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@660 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x660 0x10>;
interrupts = <1 15 0>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
timer@670 { // General Purpose Timer
2007-10-18 22:44:24 +04:00
compatible = "fsl,mpc5200-gpt";
2008-04-29 17:19:07 +04:00
reg = <0x670 0x10>;
interrupts = <1 16 0>;
2006-11-28 00:16:29 +03:00
};
rtc@800 { // Real time clock
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-rtc";
2008-04-29 17:19:07 +04:00
reg = <0x800 0x100>;
2006-11-28 00:16:29 +03:00
interrupts = <1 5 0 1 6 0>;
};
2008-01-25 08:25:31 +03:00
can@900 {
compatible = "fsl,mpc5200-mscan";
2008-04-29 17:19:07 +04:00
interrupts = <2 17 0>;
reg = <0x900 0x80>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
can@980 {
compatible = "fsl,mpc5200-mscan";
2008-04-29 17:19:07 +04:00
interrupts = <2 18 0>;
reg = <0x980 0x80>;
2006-11-28 00:16:29 +03:00
};
gpio@b00 {
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-gpio";
2008-04-29 17:19:07 +04:00
reg = <0xb00 0x40>;
2006-11-28 00:16:29 +03:00
interrupts = <1 7 0>;
2010-06-11 05:52:34 +04:00
gpio-controller;
#gpio-cells = <2>;
2006-11-28 00:16:29 +03:00
};
2008-01-25 08:25:31 +03:00
gpio@c00 {
compatible = "fsl,mpc5200-gpio-wkup";
2008-04-29 17:19:07 +04:00
reg = <0xc00 0x40>;
2006-11-28 00:16:29 +03:00
interrupts = <1 8 0 0 3 0>;
2010-06-11 05:52:34 +04:00
gpio-controller;
#gpio-cells = <2>;
2006-11-28 00:16:29 +03:00
};
spi@f00 {
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-spi";
2008-04-29 17:19:07 +04:00
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
2006-11-28 00:16:29 +03:00
};
usb@1000 {
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-ohci","ohci-be";
2008-04-29 17:19:07 +04:00
reg = <0x1000 0xff>;
2006-11-28 00:16:29 +03:00
interrupts = <2 6 0>;
};
2008-01-25 08:25:31 +03:00
dma-controller@1200 {
compatible = "fsl,mpc5200-bestcomm";
2008-04-29 17:19:07 +04:00
reg = <0x1200 0x80>;
2006-11-28 00:16:29 +03:00
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
2008-04-29 17:19:07 +04:00
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
2006-11-28 00:16:29 +03:00
};
xlb@1f00 {
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-xlb";
2008-04-29 17:19:07 +04:00
reg = <0x1f00 0x100>;
2006-11-28 00:16:29 +03:00
};
serial@2000 { // PSC1
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-psc-uart";
2007-02-12 23:36:54 +03:00
cell-index = <0>;
2008-04-29 17:19:07 +04:00
reg = <0x2000 0x100>;
2006-11-28 00:16:29 +03:00
interrupts = <2 1 0>;
};
2007-02-12 23:36:54 +03:00
// PSC2 in ac97 mode example
//ac97@2200 { // PSC2
2008-01-25 08:25:31 +03:00
// compatible = "fsl,mpc5200-psc-ac97";
2007-02-12 23:36:54 +03:00
// cell-index = <1>;
2008-04-29 17:19:07 +04:00
// reg = <0x2200 0x100>;
2007-02-12 23:36:54 +03:00
// interrupts = <2 2 0>;
//};
2006-11-28 00:16:29 +03:00
// PSC3 in CODEC mode example
2007-02-12 23:36:54 +03:00
//i2s@2400 { // PSC3
2008-01-25 08:25:31 +03:00
// compatible = "fsl,mpc5200-psc-i2s";
2007-02-12 23:36:54 +03:00
// cell-index = <2>;
2008-04-29 17:19:07 +04:00
// reg = <0x2400 0x100>;
2007-02-12 23:36:54 +03:00
// interrupts = <2 3 0>;
//};
2006-11-28 00:16:29 +03:00
2007-02-12 23:36:54 +03:00
// PSC4 in uart mode example
2006-11-28 00:16:29 +03:00
//serial@2600 { // PSC4
2008-01-25 08:25:31 +03:00
// compatible = "fsl,mpc5200-psc-uart";
2007-02-12 23:36:54 +03:00
// cell-index = <3>;
2008-04-29 17:19:07 +04:00
// reg = <0x2600 0x100>;
// interrupts = <2 11 0>;
2006-11-28 00:16:29 +03:00
//};
2007-02-12 23:36:54 +03:00
// PSC5 in uart mode example
2006-11-28 00:16:29 +03:00
//serial@2800 { // PSC5
2008-01-25 08:25:31 +03:00
// compatible = "fsl,mpc5200-psc-uart";
2007-02-12 23:36:54 +03:00
// cell-index = <4>;
2008-04-29 17:19:07 +04:00
// reg = <0x2800 0x100>;
// interrupts = <2 12 0>;
2006-11-28 00:16:29 +03:00
//};
2007-02-12 23:36:54 +03:00
// PSC6 in spi mode example
//spi@2c00 { // PSC6
2008-01-25 08:25:31 +03:00
// compatible = "fsl,mpc5200-psc-spi";
2007-02-12 23:36:54 +03:00
// cell-index = <5>;
2008-04-29 17:19:07 +04:00
// reg = <0x2c00 0x100>;
2007-02-12 23:36:54 +03:00
// interrupts = <2 4 0>;
//};
2006-11-28 00:16:29 +03:00
ethernet@3000 {
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-fec";
2008-04-29 17:19:07 +04:00
reg = <0x3000 0x400>;
2008-01-25 08:25:31 +03:00
local-mac-address = [ 00 00 00 00 00 00 ];
2006-11-28 00:16:29 +03:00
interrupts = <2 5 0>;
2008-04-03 12:58:37 +04:00
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200-mdio";
2008-04-29 17:19:07 +04:00
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
2008-04-03 12:58:37 +04:00
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
2010-06-10 01:16:20 +04:00
phy0: ethernet-phy@0 {
reg = <0>;
2008-04-03 12:58:37 +04:00
};
2006-11-28 00:16:29 +03:00
};
ata@3a00 {
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-ata";
2008-04-29 17:19:07 +04:00
reg = <0x3a00 0x100>;
2006-11-28 00:16:29 +03:00
interrupts = <2 7 0>;
};
i2c@3d00 {
2007-12-12 08:17:24 +03:00
#address-cells = <1>;
#size-cells = <0>;
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-i2c","fsl-i2c";
2008-04-29 17:19:07 +04:00
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
2006-11-28 00:16:29 +03:00
};
i2c@3d40 {
2007-12-12 08:17:24 +03:00
#address-cells = <1>;
#size-cells = <0>;
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-i2c","fsl-i2c";
2008-04-29 17:19:07 +04:00
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
2010-06-11 05:52:34 +04:00
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
2006-11-28 00:16:29 +03:00
};
2010-06-11 05:52:34 +04:00
2006-11-28 00:16:29 +03:00
sram@8000 {
2009-02-03 22:30:26 +03:00
compatible = "fsl,mpc5200-sram";
2008-04-29 17:19:07 +04:00
reg = <0x8000 0x4000>;
2006-11-28 00:16:29 +03:00
};
};
2007-09-13 03:23:46 +04:00
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
2008-01-25 08:25:31 +03:00
compatible = "fsl,mpc5200-pci";
2008-04-29 17:19:07 +04:00
reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
0xc000 0 0 2 &mpc5200_pic 0 0 3
0xc000 0 0 3 &mpc5200_pic 0 0 3
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
2007-09-13 03:23:46 +04:00
clock-frequency = <0>; // From boot loader
2008-04-29 17:19:07 +04:00
interrupts = <2 8 0 2 9 0 2 10 0>;
2007-09-13 03:23:46 +04:00
bus-range = <0 0>;
2008-04-29 17:19:07 +04:00
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
2007-09-13 03:23:46 +04:00
};
2010-06-11 05:52:34 +04:00
localbus {
compatible = "fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xff000000 0x01000000>;
flash@0,0 {
compatible = "amd,am29lv652d", "cfi-flash";
reg = <0 0 0x01000000>;
bank-width = <1>;
};
};
2006-11-28 00:16:29 +03:00
};