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/*
* arch / arm / mach - tegra / board - dt - tegra30 . c
*
* NVIDIA Tegra30 device tree board support
*
* Copyright ( C ) 2011 NVIDIA Corporation
*
* Derived from :
*
* arch / arm / mach - tegra / board - dt - tegra20 . c
*
* Copyright ( C ) 2010 Secret Lab Technologies , Ltd .
* Copyright ( C ) 2010 Google , Inc .
*
* This software is licensed under the terms of the GNU General Public
* License version 2 , as published by the Free Software Foundation , and
* may be copied , distributed , and modified under those terms .
*
* This program is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the
* GNU General Public License for more details .
*
*/
# include <linux/kernel.h>
# include <linux/of.h>
# include <linux/of_address.h>
# include <linux/of_fdt.h>
# include <linux/of_irq.h>
# include <linux/of_platform.h>
# include <asm/mach/arch.h>
# include <asm/hardware/gic.h>
# include "board.h"
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# include "clock.h"
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# include "common.h"
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# include "iomap.h"
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struct of_dev_auxdata tegra30_auxdata_lookup [ ] __initdata = {
OF_DEV_AUXDATA ( " nvidia,tegra20-sdhci " , 0x78000000 , " sdhci-tegra.0 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-sdhci " , 0x78000200 , " sdhci-tegra.1 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-sdhci " , 0x78000400 , " sdhci-tegra.2 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-sdhci " , 0x78000600 , " sdhci-tegra.3 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-i2c " , 0x7000C000 , " tegra-i2c.0 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-i2c " , 0x7000C400 , " tegra-i2c.1 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-i2c " , 0x7000C500 , " tegra-i2c.2 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-i2c " , 0x7000C700 , " tegra-i2c.3 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra20-i2c " , 0x7000D000 , " tegra-i2c.4 " , NULL ) ,
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OF_DEV_AUXDATA ( " nvidia,tegra30-ahub " , 0x70080000 , " tegra30-ahub " , NULL ) ,
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OF_DEV_AUXDATA ( " nvidia,tegra30-apbdma " , 0x6000a000 , " tegra-apbdma " , NULL ) ,
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OF_DEV_AUXDATA ( " nvidia,tegra30-pwm " , TEGRA_PWFM_BASE , " tegra-pwm " , NULL ) ,
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OF_DEV_AUXDATA ( " nvidia,tegra30-slink " , 0x7000D400 , " spi_tegra.0 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-slink " , 0x7000D600 , " spi_tegra.1 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-slink " , 0x7000D800 , " spi_tegra.2 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-slink " , 0x7000DA00 , " spi_tegra.3 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-slink " , 0x7000DC00 , " spi_tegra.4 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-slink " , 0x7000DE00 , " spi_tegra.5 " , NULL ) ,
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OF_DEV_AUXDATA ( " nvidia,tegra30-host1x " , 0x50000000 , " host1x " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-dc " , 0x54200000 , " tegradc.0 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-dc " , 0x54240000 , " tegradc.1 " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-hdmi " , 0x54280000 , " hdmi " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-dsi " , 0x54300000 , " dsi " , NULL ) ,
OF_DEV_AUXDATA ( " nvidia,tegra30-tvo " , 0x542c0000 , " tvo " , NULL ) ,
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{ }
} ;
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table [ ] = {
/* name parent rate enabled */
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{ " uarta " , " pll_p " , 408000000 , true } ,
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{ " pll_a " , " pll_p_out1 " , 564480000 , true } ,
{ " pll_a_out0 " , " pll_a " , 11289600 , true } ,
{ " extern1 " , " pll_a_out0 " , 0 , true } ,
{ " clk_out_1 " , " extern1 " , 0 , true } ,
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{ " blink " , " clk_32k " , 32768 , true } ,
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{ " i2s0 " , " pll_a_out0 " , 11289600 , false } ,
{ " i2s1 " , " pll_a_out0 " , 11289600 , false } ,
{ " i2s2 " , " pll_a_out0 " , 11289600 , false } ,
{ " i2s3 " , " pll_a_out0 " , 11289600 , false } ,
{ " i2s4 " , " pll_a_out0 " , 11289600 , false } ,
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{ " sdmmc1 " , " pll_p " , 48000000 , false } ,
{ " sdmmc3 " , " pll_p " , 48000000 , false } ,
{ " sdmmc4 " , " pll_p " , 48000000 , false } ,
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{ " sbc1 " , " pll_p " , 100000000 , false } ,
{ " sbc2 " , " pll_p " , 100000000 , false } ,
{ " sbc3 " , " pll_p " , 100000000 , false } ,
{ " sbc4 " , " pll_p " , 100000000 , false } ,
{ " sbc5 " , " pll_p " , 100000000 , false } ,
{ " sbc6 " , " pll_p " , 100000000 , false } ,
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{ " host1x " , " pll_c " , 150000000 , false } ,
{ " disp1 " , " pll_p " , 600000000 , false } ,
{ " disp2 " , " pll_p " , 600000000 , false } ,
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{ NULL , NULL , 0 , 0 } ,
} ;
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static void __init tegra30_dt_init ( void )
{
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tegra_clk_init_from_table ( tegra_dt_clk_init_table ) ;
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of_platform_populate ( NULL , of_default_bus_match_table ,
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tegra30_auxdata_lookup , NULL ) ;
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}
static const char * tegra30_dt_board_compat [ ] = {
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" nvidia,tegra30 " ,
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NULL
} ;
DT_MACHINE_START ( TEGRA30_DT , " NVIDIA Tegra30 (Flattened Device Tree) " )
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. smp = smp_ops ( tegra_smp_ops ) ,
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. map_io = tegra_map_common_io ,
. init_early = tegra30_init_early ,
. init_irq = tegra_dt_init_irq ,
. handle_irq = gic_handle_irq ,
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. timer = & tegra_sys_timer ,
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. init_machine = tegra30_dt_init ,
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. init_late = tegra_init_late ,
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. restart = tegra_assert_system_reset ,
. dt_compat = tegra30_dt_board_compat ,
MACHINE_END