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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Cache operations for the cache instruction .
*
* Copyright ( C ) 2020 - 2022 Loongson Technology Corporation Limited
*/
# ifndef __ASM_CACHEOPS_H
# define __ASM_CACHEOPS_H
/*
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:14 +08:00
* Most cache ops are split into a 3 bit field identifying the cache , and a 2
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* bit field identifying the cache operation .
*/
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:14 +08:00
# define CacheOp_Cache 0x07
# define CacheOp_Op 0x18
2022-05-31 18:04:11 +08:00
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:14 +08:00
# define Cache_LEAF0 0x00
# define Cache_LEAF1 0x01
# define Cache_LEAF2 0x02
# define Cache_LEAF3 0x03
# define Cache_LEAF4 0x04
# define Cache_LEAF5 0x05
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# define Index_Invalidate 0x08
# define Index_Writeback_Inv 0x08
# define Hit_Invalidate 0x10
# define Hit_Writeback_Inv 0x10
# define CacheOp_User_Defined 0x18
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-10-12 16:36:14 +08:00
# define Index_Writeback_Inv_LEAF0 (Cache_LEAF0 | Index_Writeback_Inv)
# define Index_Writeback_Inv_LEAF1 (Cache_LEAF1 | Index_Writeback_Inv)
# define Index_Writeback_Inv_LEAF2 (Cache_LEAF2 | Index_Writeback_Inv)
# define Index_Writeback_Inv_LEAF3 (Cache_LEAF3 | Index_Writeback_Inv)
# define Index_Writeback_Inv_LEAF4 (Cache_LEAF4 | Index_Writeback_Inv)
# define Index_Writeback_Inv_LEAF5 (Cache_LEAF5 | Index_Writeback_Inv)
# define Hit_Writeback_Inv_LEAF0 (Cache_LEAF0 | Hit_Writeback_Inv)
# define Hit_Writeback_Inv_LEAF1 (Cache_LEAF1 | Hit_Writeback_Inv)
# define Hit_Writeback_Inv_LEAF2 (Cache_LEAF2 | Hit_Writeback_Inv)
# define Hit_Writeback_Inv_LEAF3 (Cache_LEAF3 | Hit_Writeback_Inv)
# define Hit_Writeback_Inv_LEAF4 (Cache_LEAF4 | Hit_Writeback_Inv)
# define Hit_Writeback_Inv_LEAF5 (Cache_LEAF5 | Hit_Writeback_Inv)
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# endif /* __ASM_CACHEOPS_H */
