2020-04-28 05:59:12 +09:00
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Source for the TMPV7708
*
* (C) Copyright 2018 - 2020, Toshiba Corporation.
* (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
/ {
compatible = "toshiba,tmpv7708";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x00>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x01>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x02>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x03>;
};
cpu4: cpu@100 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x100>;
};
cpu5: cpu@101 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x101>;
};
cpu6: cpu@102 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x102>;
};
cpu7: cpu@103 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "spin-table";
cpu-release-addr = <0x0 0x81100000>;
reg = <0x103>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
uart_clk: uart-clk {
compatible = "fixed-clock";
clock-frequency = <150000000>;
#clock-cells = <0>;
};
2021-02-16 00:24:38 +09:00
clk125mhz: clk125mhz {
compatible = "fixed-clock";
clock-frequency = <125000000>;
#clock-cells = <0>;
clock-output-names = "clk125mhz";
};
clk300mhz: clk300mhz {
compatible = "fixed-clock";
clock-frequency = <300000000>;
#clock-cells = <0>;
clock-output-names = "clk300mhz";
};
2020-12-01 18:39:07 +09:00
wdt_clk: wdt-clk {
compatible = "fixed-clock";
clock-frequency = <150000000>;
#clock-cells = <0>;
};
2020-04-28 05:59:12 +09:00
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
gic: interrupt-controller@24001000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
reg = <0 0x24001000 0 0x1000>,
<0 0x24002000 0 0x2000>,
<0 0x24004000 0 0x2000>,
<0 0x24006000 0 0x2000>;
};
pmux: pmux@24190000 {
compatible = "toshiba,tmpv7708-pinctrl";
reg = <0 0x24190000 0 0x10000>;
};
2020-12-17 23:43:38 +09:00
gpio: gpio@28020000 {
compatible = "toshiba,gpio-tmpv7708";
reg = <0 0x28020000 0 0x1000>;
#gpio-cells = <0x2>;
gpio-ranges = <&pmux 0 0 32>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gic>;
};
2020-04-28 05:59:12 +09:00
uart0: serial@28200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28200000 0 0x1000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "disabled";
};
uart1: serial@28201000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28201000 0 0x1000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
uart2: serial@28202000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28202000 0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
uart3: serial@28203000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x28203000 0 0x1000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "disabled";
};
i2c0: i2c@28030000 {
compatible = "snps,designware-i2c";
reg = <0 0x28030000 0 0x1000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@28031000 {
compatible = "snps,designware-i2c";
reg = <0 0x28031000 0 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@28032000 {
compatible = "snps,designware-i2c";
reg = <0 0x28032000 0 0x1000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@28033000 {
compatible = "snps,designware-i2c";
reg = <0 0x28033000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@28034000 {
compatible = "snps,designware-i2c";
reg = <0 0x28034000 0 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@28035000 {
compatible = "snps,designware-i2c";
reg = <0 0x28035000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@28036000 {
compatible = "snps,designware-i2c";
reg = <0 0x28036000 0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@28037000 {
compatible = "snps,designware-i2c";
reg = <0 0x28037000 0 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@28038000 {
compatible = "snps,designware-i2c";
reg = <0 0x28038000 0 0x1000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_pins>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@28140000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28140000 0 0x1000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@28141000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28141000 0 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@28142000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28142000 0 0x1000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@28143000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28143000 0 0x1000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@28144000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28144000 0 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi4_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@28145000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28145000 0 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@28146000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0 0x28146000 0 0x1000>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi6_pins>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
2021-02-16 00:24:38 +09:00
piether: ethernet@28000000 {
compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
reg = <0 0x28000000 0 0x10000>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,txpbl = <4>;
snps,rxpbl = <4>;
snps,tso;
status = "disabled";
};
ARM: SoC devicetree updates for v5.12
After the last release contained a surprising amount of new 32-bit
machines, this time two thirds of the code changes are for 64-bit.
The usual updates to existing files include:
- Device tree compiler warning fixes for Berlin, Renesas, SoCFPGA,
nomadik, stm32, Allwinner, TI Keystone
- Support for additional devices on existing machines on Renesas, SoCFPGA,
at91, hisilicon, OMAP, Tegra, TI K3, Allwinner, Broadcom, ux500,
Mediatek, Marvell Armada, Marvell MMP, ZynqMP, AMLogic, Qualcomm,
i.MX, Layerscape, Actions, ASpeed, Toshiba
- Cleanups and minor fixes for Renesas, at91, mstar, ux500, Samsung,
stm32, Tegra, Broadcom, Mediatek, Marvell MMP, AMLogic, Qualcomm,
i.MX, Rockchip, ASpeed, Zynq
Only three new SoCs this time, but a number of boards across:
Renesas:
- Two Beacon EmbeddedWorks boards (RZ/G2H and RZ/G2N based)
Intel SoCFPGA:
- eASIC N5X board (N5X)
ST-Ericsson Ux500:
- Samsung GT-I9070 (Janice) phone (u8500)
TI OMAP:
- MYIR Tech Limited development board (AM335X)
Allwinner/sunxi:
- SL631 Action Camera (V3)
- PineTab Early Adopter tablet (A64)
Broadcom:
- BCM4906/BCM4908 networking chip
- Netgear R8000P router (BCM5906)
AMLogic:
- Hardkernel ODROID-HC4 development board (SM1)
- Beelink GS-King-X TV Box (S922X)
Qualcomm:
- Snapdragon 888 / SM8350 high-end phone SoC
- Qualcomm SDX55 5G modem as standalone SoC
- Snapdragon MTP reference board (SM8350)
- Snapdragon MTP reference board (SDX55)
- Sony Kitakami phones: Xperia Z3+/Z4/Z5 (APQ8094)
- Alcatel Idol 3 phone (MSM8916)
- ASUS Zenfone 2 Laser phone (MSM8916)
- BQ Aquaris X5 aka Longcheer L8910 phone (MSM8916)
- OnePlus6 phone (SDM845)
- OnePlus6T phone (SDM845)
- Alfa Network AP120C-AC access point (IPQ4018)
NXP i.MX6 (32-bit):
- Plymovent BAS base system controller for filter systems (imx6dl)
- Protonic MVT industrial touchscreen terminals (imx6dl)
- Protonic PRTI6G reference board (imx6ul)
- Kverneland UT1, UT1Q, UT1P, TGO agricultural terminals (imx6q/dl/qp)
NXP i.MX8 (64-bit)
- Beacon i.MX8M Nano development kit (imx8mn)
- Boundary Devices i.MX8MM Nitrogen SBC (imx8mm)
- Gateworks Venice i.MX 8M Mini Development Kits (imx8mm)
- phyBOARD-Pollux-i.MX8MP (imx8mp)
- Purism Librem5 Evergreen phone (imx8mp)
- Kontron SMARC-sAL28 system-on-module(imx8mp)
Rockchip:
- NanoPi M4B Single-board computer (RK3399)
- Radxa Rock Pi E router SBC (RK3328)
ASpeed:
- Ampere Mt. Jade, a BMC for an x86 server (AST2500)
- IBM Everest, a BMC for a Power10 server (AST2600)
- Supermicro x11spi, a BMC for an ARM server (AST2500)
Zynq:
- Ebang EBAZ4205, FPGA board (Zynq-7000)
- ZynqMP zcu104 revC reference platform (ZynqMP)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-dt-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"After the last release contained a surprising amount of new 32-bit
machines, this time two thirds of the code changes are for 64-bit.
The usual updates to existing files include:
- Device tree compiler warning fixes for Berlin, Renesas, SoCFPGA,
nomadik, stm32, Allwinner, TI Keystone
- Support for additional devices on existing machines on Renesas,
SoCFPGA, at91, hisilicon, OMAP, Tegra, TI K3, Allwinner, Broadcom,
ux500, Mediatek, Marvell Armada, Marvell MMP, ZynqMP, AMLogic,
Qualcomm, i.MX, Layerscape, Actions, ASpeed, Toshiba
- Cleanups and minor fixes for Renesas, at91, mstar, ux500, Samsung,
stm32, Tegra, Broadcom, Mediatek, Marvell MMP, AMLogic, Qualcomm,
i.MX, Rockchip, ASpeed, Zynq
Only three new SoCs this time, but a number of boards across:
Renesas:
- Two Beacon EmbeddedWorks boards (RZ/G2H and RZ/G2N based)
Intel SoCFPGA:
- eASIC N5X board (N5X)
ST-Ericsson Ux500:
- Samsung GT-I9070 (Janice) phone (u8500)
TI OMAP:
- MYIR Tech Limited development board (AM335X)
Allwinner/sunxi:
- SL631 Action Camera (V3)
- PineTab Early Adopter tablet (A64)
Broadcom:
- BCM4906 networking chip
- Netgear R8000P router (BCM4906)
AMLogic:
- Hardkernel ODROID-HC4 development board (SM1)
- Beelink GS-King-X TV Box (S922X)
Qualcomm:
- Snapdragon 888 / SM8350 high-end phone SoC
- Qualcomm SDX55 5G modem as standalone SoC
- Snapdragon MTP reference board (SM8350)
- Snapdragon MTP reference board (SDX55)
- Sony Kitakami phones: Xperia Z3+/Z4/Z5 (APQ8094)
- Alcatel Idol 3 phone (MSM8916)
- ASUS Zenfone 2 Laser phone (MSM8916)
- BQ Aquaris X5 aka Longcheer L8910 phone (MSM8916)
- OnePlus6 phone (SDM845)
- OnePlus6T phone (SDM845)
- Alfa Network AP120C-AC access point (IPQ4018)
NXP i.MX6 (32-bit):
- Plymovent BAS base system controller for filter systems (imx6dl)
- Protonic MVT industrial touchscreen terminals (imx6dl)
- Protonic PRTI6G reference board (imx6ul)
- Kverneland UT1, UT1Q, UT1P, TGO agricultural terminals (imx6q/dl/qp)
NXP i.MX8 (64-bit)
- Beacon i.MX8M Nano development kit (imx8mn)
- Boundary Devices i.MX8MM Nitrogen SBC (imx8mm)
- Gateworks Venice i.MX 8M Mini Development Kits (imx8mm)
- phyBOARD-Pollux-i.MX8MP (imx8mp)
- Purism Librem5 Evergreen phone (imx8mp)
- Kontron SMARC-sAL28 system-on-module(imx8mp)
Rockchip:
- NanoPi M4B Single-board computer (RK3399)
- Radxa Rock Pi E router SBC (RK3328)
ASpeed:
- Ampere Mt. Jade, a BMC for an x86 server (AST2500)
- IBM Everest, a BMC for a Power10 server (AST2600)
- Supermicro x11spi, a BMC for an ARM server (AST2500)
Zynq:
- Ebang EBAZ4205, FPGA board (Zynq-7000)
- ZynqMP zcu104 revC reference platform (ZynqMP)"
* tag 'arm-dt-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (584 commits)
ARM: dts: aspeed: align GPIO hog names with dtschema
ARM: dts: aspeed: fix PCA95xx GPIO expander properties on Portwell
dt-bindings: spi: zynq: Convert Zynq QSPI binding to yaml
arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driver
ARM: dts: aspeed: ast2600evb: Add enable ehci and uhci
ARM: dts: aspeed: mowgli: Add i2c rtc device
ARM: dts: aspeed: amd-ethanolx: Enable secondary LPC snooping address
dt-bindings: arm: xilinx: Add missing Zturn boards
ARM: dts: ebaz4205: add pinctrl entries for switches
ARM: dts: add Ebang EBAZ4205 device tree
dt-bindings: arm: add Ebang EBAZ4205 board
dt-bindings: add ebang vendor prefix
ARM: dts: aspeed: Add Everest BMC machine
ARM: dts: aspeed: inspur-fp5280g2: Add ipsps1 driver
ARM: dts: aspeed: inspur-fp5280g2: Add GPIO line names
ARM: dts: aspeed: Add Supermicro x11spi BMC machine
ARM: dts: aspeed: g220a: Fix some gpio
ARM: dts: aspeed: g220a: Enable ipmb
ARM: dts: aspeed: rainier: Add eMMC clock phase compensation
ARM: dts: aspeed: Add LCLK to lpc-snoop
...
2021-02-20 18:34:53 -08:00
2020-12-01 18:39:07 +09:00
wdt: wdt@28330000 {
compatible = "toshiba,visconti-wdt";
reg = <0 0x28330000 0 0x1000>;
status = "disabled";
};
2020-04-28 05:59:12 +09:00
};
};
#include "tmpv7708_pins.dtsi"
