linux/arch/arm/mm/tlb-fa.S

/*
 *  linux/arch/arm/mm/tlb-fa.S
 *
 *  Copyright (C) 2005 Faraday Corp.
 *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 *
 * Based on tlb-v4wbi.S:
 *  Copyright (C) 1997-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  ARM architecture version 4, Faraday variation.
 *  This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
 *
 *  Processors: FA520 FA526 FA626
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/asm-offsets.h>
#include <asm/tlbflush.h>
#include "proc-macros.S"


/*
 *	flush_user_tlb_range(start, end, mm)
 *
 *	Invalidate a range of TLB entries in the specified address space.
 *
 *	- start - range start address
 *	- end   - range end address
 *	- mm    - mm_struct describing address space
 */
	.align	4
ENTRY(fa_flush_user_tlb_range)
	vma_vm_mm ip, r2
	act_mm	r3				@ get current->active_mm
	eors	r3, ip, r3			@ == mm ?
	movne	pc, lr				@ no, we dont do anything
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	bic	r0, r0, #0x0ff
	bic	r0, r0, #0xf00
1:	mcr	p15, 0, r0, c8, c7, 1		@ invalidate UTLB entry
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r3, c7, c10, 4		@ data write barrier
	mov	pc, lr


ENTRY(fa_flush_kern_tlb_range)
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	bic	r0, r0, #0x0ff
	bic	r0, r0, #0xf00
1:	mcr	p15, 0, r0, c8, c7, 1		@ invalidate UTLB entry
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r3, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r3, c7, c5, 4		@ prefetch flush (isb)
	mov	pc, lr

	__INITDATA

	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
	define_tlb_functions fa, fa_tlb_flags
ARM: Add support for FA526 v2 Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 2009-03-25 13:10:01 +02:00			`/*`
			`* linux/arch/arm/mm/tlb-fa.S`
			`*`
			`* Copyright (C) 2005 Faraday Corp.`
			`* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>`
			`*`
			`* Based on tlb-v4wbi.S:`
			`* Copyright (C) 1997-2002 Russell King`
			`*`
			`* This program is free software; you can redistribute it and/or modify`
			`* it under the terms of the GNU General Public License version 2 as`
			`* published by the Free Software Foundation.`
			`*`
			`* ARM architecture version 4, Faraday variation.`
			`* This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)`
			`*`
			`* Processors: FA520 FA526 FA626`
			`*/`
			`#include <linux/linkage.h>`
			`#include <linux/init.h>`
			`#include <asm/asm-offsets.h>`
			`#include <asm/tlbflush.h>`
			`#include "proc-macros.S"`


			`/*`
			`* flush_user_tlb_range(start, end, mm)`
			`*`
			`* Invalidate a range of TLB entries in the specified address space.`
			`*`
			`* - start - range start address`
			`* - end - range end address`
			`* - mm - mm_struct describing address space`
			`*/`
			`.align 4`
			`ENTRY(fa_flush_user_tlb_range)`
			`vma_vm_mm ip, r2`
			`act_mm r3 @ get current->active_mm`
			`eors r3, ip, r3 @ == mm ?`
			`movne pc, lr @ no, we dont do anything`
			`mov r3, #0`
			`mcr p15, 0, r3, c7, c10, 4 @ drain WB`
			`bic r0, r0, #0x0ff`
			`bic r0, r0, #0xf00`
			`1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry`
			`add r0, r0, #PAGE_SZ`
			`cmp r0, r1`
			`blo 1b`
			`mcr p15, 0, r3, c7, c10, 4 @ data write barrier`
			`mov pc, lr`


			`ENTRY(fa_flush_kern_tlb_range)`
			`mov r3, #0`
			`mcr p15, 0, r3, c7, c10, 4 @ drain WB`
			`bic r0, r0, #0x0ff`
			`bic r0, r0, #0xf00`
			`1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry`
			`add r0, r0, #PAGE_SZ`
			`cmp r0, r1`
			`blo 1b`
			`mcr p15, 0, r3, c7, c10, 4 @ data write barrier`
ARM: btc: avoid invalidating the branch target cache on kernel TLB maintanence Kernel space needs very little in the way of BTC maintanence as most mappings which are created and destroyed are non-executable, and so could never enter the instruction stream. The case which does warrant BTC maintanence is when a module is loaded. This creates a new executable mapping, but at that point the pages have not been initialized with code and data, so at that point they contain unpredictable information. Invalidating the BTC at this stage serves little useful purpose. Before we execute module code, we call flush_icache_range(), which deals with the BTC maintanence requirements. This ensures that we have a BTC maintanence operation before we execute code via the newly created mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2011-07-05 09:01:13 +01:00			`mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)`
ARM: Add support for FA526 v2 Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 2009-03-25 13:10:01 +02:00			`mov pc, lr`

			`__INITDATA`

ARM: mm: tlb-fa: Use the new processor struct macros Signed-off-by: Dave Martin <dave.martin@linaro.org> 2011-06-23 17:28:50 +01:00			`/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */`
			`define_tlb_functions fa, fa_tlb_flags`