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linux/arch/mips/ralink/mt7620.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-04 10:11:33 +02:00
// SPDX-License-Identifier: GPL-2.0-only
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
/*
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
MIPS: Change my email address The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-05 09:57:56 +02:00
* Copyright (C) 2013 John Crispin <john@phrozen.org>
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
*/
#include <linux/kernel.h>
#include <linux/init.h>
MIPS: ralink: mt7620: Add missing header Fix a build error caused by not including <linux/bug.h>. The following compilation errors are caused by the missing header: arch/mips/ralink/mt7620.c: In function ‘mt7620_get_cpu_pll_rate’: arch/mips/ralink/mt7620.c:431:2: error: implicit declaration of function ‘WARN_ON’ [-Werror=implicit-function-declaration] WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); ^ arch/mips/ralink/mt7620.c: In function ‘mt7620_get_sys_rate’: arch/mips/ralink/mt7620.c:500:2: error: implicit declaration of function ‘WARN’ [-Werror=implicit-function-declaration] if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) ^ arch/mips/ralink/mt7620.c: In function ‘mt7620_dram_init’: arch/mips/ralink/mt7620.c:619:3: error: implicit declaration of function ‘BUG’ [-Werror=implicit-function-declaration] BUG(); ^ cc1: some warnings being treated as errors scripts/Makefile.build:302: recipe for target 'arch/mips/ralink/mt7620.o' failed Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-18 14:25:46 +01:00
#include <linux/bug.h>
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7620.h>
#include "common.h"
MIPS: ralink: add verbose pmu info Print the PMU and LDO settings on boot. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/7999/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-27 09:16:50 +01:00
/* analog */
#define PMU0_CFG 0x88
#define PMU_SW_SET BIT(28)
#define A_DCDC_EN BIT(24)
#define A_SSC_PERI BIT(19)
#define A_SSC_GEN BIT(18)
#define A_SSC_M 0x3
#define A_SSC_S 16
#define A_DLY_M 0x7
#define A_DLY_S 8
#define A_VTUNE_M 0xff
/* digital */
#define PMU1_CFG 0x8C
#define DIG_SW_SEL BIT(25)
MIPS: ralink: Fix usb issue during frequency scaling If the USB HCD is running and the cpu is scaled too low, then the USB stops working. Increase the idle speed of the core to fix this if the kernel is built with USB support. The "magic" values are taken from the Ralink SDK Kernel. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11441/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:08 +01:00
/* clock scaling */
#define CLKCFG_FDIV_MASK 0x1f00
#define CLKCFG_FDIV_USB_VAL 0x0300
#define CLKCFG_FFRAC_MASK 0x001f
#define CLKCFG_FFRAC_USB_VAL 0x0003
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
/* EFUSE bits */
#define EFUSE_MT7688 0x100000
/* DRAM type bit */
#define DRAM_TYPE_MT7628_MASK 0x1
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
/* does the board have sdram or ddram */
static int dram_type;
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
static __init u32
mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
{
u64 t;
t = ref_rate;
t *= mul;
do_div(t, div);
return t;
}
#define MHZ(x) ((x) * 1000 * 1000)
static __init unsigned long
mt7620_get_xtal_rate(void)
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
{
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
u32 reg;
reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
if (reg & SYSCFG0_XTAL_FREQ_SEL)
return MHZ(40);
return MHZ(20);
}
static __init unsigned long
mt7620_get_periph_rate(unsigned long xtal_rate)
{
u32 reg;
reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
if (reg & CLKCFG0_PERI_CLK_SEL)
return xtal_rate;
return MHZ(40);
}
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
static __init unsigned long
mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
{
u32 reg;
u32 mul;
u32 div;
reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
if (reg & CPLL_CFG0_BYPASS_REF_CLK)
return xtal_rate;
if ((reg & CPLL_CFG0_SW_CFG) == 0)
return MHZ(600);
mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
CPLL_CFG0_PLL_MULT_RATIO_MASK;
mul += 24;
if (reg & CPLL_CFG0_LC_CURFCK)
mul *= 2;
div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
CPLL_CFG0_PLL_DIV_RATIO_MASK;
WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
}
static __init unsigned long
mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
{
u32 reg;
reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
if (reg & CPLL_CFG1_CPU_AUX1)
return xtal_rate;
if (reg & CPLL_CFG1_CPU_AUX0)
return MHZ(480);
return cpu_pll_rate;
}
static __init unsigned long
mt7620_get_cpu_rate(unsigned long pll_rate)
{
u32 reg;
u32 mul;
u32 div;
reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
CPU_SYS_CLKCFG_CPU_FDIV_MASK;
return mt7620_calc_rate(pll_rate, mul, div);
}
static const u32 mt7620_ocp_dividers[16] __initconst = {
[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
};
static __init unsigned long
mt7620_get_dram_rate(unsigned long pll_rate)
{
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
return pll_rate / 4;
return pll_rate / 3;
}
static __init unsigned long
mt7620_get_sys_rate(unsigned long cpu_rate)
{
u32 reg;
u32 ocp_ratio;
u32 div;
reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
CPU_SYS_CLKCFG_OCP_RATIO_MASK;
if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
return cpu_rate;
div = mt7620_ocp_dividers[ocp_ratio];
if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
return cpu_rate;
return cpu_rate / div;
}
void __init ralink_clk_init(void)
{
unsigned long xtal_rate;
unsigned long cpu_pll_rate;
unsigned long pll_rate;
unsigned long cpu_rate;
unsigned long sys_rate;
unsigned long dram_rate;
unsigned long periph_rate;
MIPS: ralink: Add missing I2C and I2S clocks. This patch adds two additional clocks required by the audio interface of the SoCs. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14897/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-12-20 19:12:41 +01:00
unsigned long pcmi2s_rate;
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
xtal_rate = mt7620_get_xtal_rate();
#define RFMT(label) label ":%lu.%03luMHz "
#define RINT(x) ((x) / 1000000)
#define RFRAC(x) (((x) / 1000) % 1000)
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
if (is_mt76x8()) {
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
if (xtal_rate == MHZ(40))
cpu_rate = MHZ(580);
else
cpu_rate = MHZ(575);
dram_rate = sys_rate = cpu_rate / 3;
periph_rate = MHZ(40);
MIPS: ralink: Add missing I2C and I2S clocks. This patch adds two additional clocks required by the audio interface of the SoCs. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14897/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-12-20 19:12:41 +01:00
pcmi2s_rate = MHZ(480);
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
ralink_clk_add("10000d00.uartlite", periph_rate);
ralink_clk_add("10000e00.uartlite", periph_rate);
} else {
cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
cpu_rate = mt7620_get_cpu_rate(pll_rate);
dram_rate = mt7620_get_dram_rate(pll_rate);
sys_rate = mt7620_get_sys_rate(cpu_rate);
periph_rate = mt7620_get_periph_rate(xtal_rate);
MIPS: ralink: Add missing I2C and I2S clocks. This patch adds two additional clocks required by the audio interface of the SoCs. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14897/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-12-20 19:12:41 +01:00
pcmi2s_rate = periph_rate;
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
RINT(xtal_rate), RFRAC(xtal_rate),
RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
RINT(pll_rate), RFRAC(pll_rate));
ralink_clk_add("10000500.uart", periph_rate);
}
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
RINT(cpu_rate), RFRAC(cpu_rate),
RINT(dram_rate), RFRAC(dram_rate),
RINT(sys_rate), RFRAC(sys_rate),
RINT(periph_rate), RFRAC(periph_rate));
#undef RFRAC
#undef RINT
#undef RFMT
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
ralink_clk_add("cpu", cpu_rate);
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
ralink_clk_add("10000100.timer", periph_rate);
MIPS: ralink: mt7620: Add wdt clock definition The watchdog driver of the SoC uses the clk API to get the clock associated with the watchdog device. However the MT7620 specific setup code does not register a clock for the watchdog device yet which leads to the following error: rt2880_wdt: probe of 10000120.watchdog failed with error -2 Register a clock device for the watchdog in order to avoid the error and make the watchdog usable. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5756/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:31 +02:00
ralink_clk_add("10000120.watchdog", periph_rate);
MIPS: ralink: Add missing I2C and I2S clocks. This patch adds two additional clocks required by the audio interface of the SoCs. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14897/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-12-20 19:12:41 +01:00
ralink_clk_add("10000900.i2c", periph_rate);
ralink_clk_add("10000a00.i2s", pcmi2s_rate);
MIPS: ralink: mt7620: Add spi clock definition Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:32 +02:00
ralink_clk_add("10000b00.spi", sys_rate);
MIPS: ralink: Add a few missing clocks Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11995/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-04 20:24:00 +01:00
ralink_clk_add("10000b40.spi", sys_rate);
MIPS: ralink: mt7620: Improve clock frequency detection The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-23 08:31:30 +02:00
ralink_clk_add("10000c00.uartlite", periph_rate);
MIPS: ralink: Add a few missing clocks Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11995/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-04 20:24:00 +01:00
ralink_clk_add("10000d00.uart1", periph_rate);
ralink_clk_add("10000e00.uart2", periph_rate);
MIPS: ralink: add support for MT7620n This is the small version of MT7620a. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8030/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-27 09:23:36 +01:00
ralink_clk_add("10180000.wmac", xtal_rate);
MIPS: ralink: Fix usb issue during frequency scaling If the USB HCD is running and the cpu is scaled too low, then the USB stops working. Increase the idle speed of the core to fix this if the kernel is built with USB support. The "magic" values are taken from the Ralink SDK Kernel. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11441/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:08 +01:00
MIPS: ralink: fix USB frequency scaling Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully correct. The logic for the SoC check got inverted. We need to check if it is not a MT76x8. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11992/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-04 20:23:57 +01:00
if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
MIPS: ralink: Fix usb issue during frequency scaling If the USB HCD is running and the cpu is scaled too low, then the USB stops working. Increase the idle speed of the core to fix this if the kernel is built with USB support. The "magic" values are taken from the Ralink SDK Kernel. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11441/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:08 +01:00
/*
* When the CPU goes into sleep mode, the BUS clock will be
* too low for USB to function properly. Adjust the busses
* fractional divider to fix this
*/
u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
}
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
}
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
}
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
static __init void
mt7620_dram_init(struct ralink_soc_info *soc_info)
{
switch (dram_type) {
case SYSCFG0_DRAM_TYPE_SDRAM:
pr_info("Board has SDRAM\n");
soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
break;
case SYSCFG0_DRAM_TYPE_DDR1:
pr_info("Board has DDR1\n");
soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
break;
case SYSCFG0_DRAM_TYPE_DDR2:
pr_info("Board has DDR2\n");
soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
break;
default:
BUG();
}
}
static __init void
mt7628_dram_init(struct ralink_soc_info *soc_info)
{
switch (dram_type) {
case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
pr_info("Board has DDR1\n");
soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
break;
case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
pr_info("Board has DDR2\n");
soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
break;
default:
BUG();
}
}
MIPS: ralink: annotate prom_soc_init() with __init prom_soc_init is only called from prom_init in arch/mips/ralink/prom.c, which is already annotated with __init, so annotate prom_soc_init with __init too. Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-03-26 22:38:39 -07:00
void __init prom_soc_init(struct ralink_soc_info *soc_info)
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
{
void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
unsigned char *name = NULL;
u32 n0;
u32 n1;
u32 rev;
u32 cfg0;
MIPS: ralink: add verbose pmu info Print the PMU and LDO settings on boot. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/7999/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-27 09:16:50 +01:00
u32 pmu0;
u32 pmu1;
MIPS: ralink: add support for MT7620n This is the small version of MT7620a. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8030/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-27 09:23:36 +01:00
u32 bga;
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
MIPS: ralink: add support for MT7620n This is the small version of MT7620a. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8030/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-27 09:23:36 +01:00
rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
if (bga) {
MIPS: ralink: Unify SoC id handling This makes detection a lot easier for audio, wifi, ... drivers. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11440/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:07 +01:00
ralink_soc = MT762X_SOC_MT7620A;
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
name = "MT7620A";
soc_info->compatible = "ralink,mt7620a-soc";
} else {
MIPS: ralink: Unify SoC id handling This makes detection a lot easier for audio, wifi, ... drivers. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11440/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:07 +01:00
ralink_soc = MT762X_SOC_MT7620N;
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
name = "MT7620N";
soc_info->compatible = "ralink,mt7620n-soc";
}
} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
if (efuse & EFUSE_MT7688) {
MIPS: ralink: Unify SoC id handling This makes detection a lot easier for audio, wifi, ... drivers. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11440/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:07 +01:00
ralink_soc = MT762X_SOC_MT7688;
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
name = "MT7688";
} else {
MIPS: ralink: Unify SoC id handling This makes detection a lot easier for audio, wifi, ... drivers. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11440/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:07 +01:00
ralink_soc = MT762X_SOC_MT7628AN;
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
name = "MT7628AN";
}
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
soc_info->compatible = "ralink,mt7628an-soc";
} else {
panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
}
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
MIPS: ralink: Fix vendor string for mt7620 Ralink was acquired by Mediatek. Represent this in the cpuinfo. It apparently confused people. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-04 20:23:59 +01:00
"MediaTek %s ver:%u eco:%u",
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
name,
(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
(rev & CHIP_REV_ECO_MASK));
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used. However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM. The patch below reflects that. Signed-off-by: Sashka Nochkin <linux-mips@durdom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13135/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-04-19 23:44:45 -04:00
if (is_mt76x8()) {
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used. However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM. The patch below reflects that. Signed-off-by: Sashka Nochkin <linux-mips@durdom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13135/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-04-19 23:44:45 -04:00
} else {
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
SYSCFG0_DRAM_TYPE_MASK;
mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used. However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM. The patch below reflects that. Signed-off-by: Sashka Nochkin <linux-mips@durdom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13135/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-04-19 23:44:45 -04:00
if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
}
MIPS: ralink: add memory definition for MT7620 Populate struct soc_info with the data that describes our RAM window. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5183/
2013-04-14 09:55:29 +02:00
soc_info->mem_base = MT7620_DRAM_BASE;
MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-11-04 11:50:06 +01:00
if (is_mt76x8())
MIPS: ralink: add mt7628an support Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-08 23:30:24 +02:00
mt7628_dram_init(soc_info);
else
mt7620_dram_init(soc_info);
MIPS: ralink: add verbose pmu info Print the PMU and LDO settings on boot. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/7999/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-27 09:16:50 +01:00
pmu0 = __raw_readl(sysc + PMU0_CFG);
pmu1 = __raw_readl(sysc + PMU1_CFG);
pr_info("Analog PMU set to %s control\n",
(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
pr_info("Digital PMU set to %s control\n",
(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
MIPS: ralink: adds support for MT7620 SoC family Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
2013-03-21 17:49:02 +01:00
}
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