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/*
* Copyright ( C ) 2004 , 2005 MIPS Technologies , Inc . All rights reserved .
*
*/
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# ifndef __ASM_RTLX_H
# define __ASM_RTLX_H_
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# define LX_NODE_BASE 10
# define MIPSCPU_INT_BASE 16
# define MIPS_CPU_RTLX_IRQ 0
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# define RTLX_VERSION 2
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# define RTLX_xID 0x12345600
# define RTLX_ID (RTLX_xID | RTLX_VERSION)
# define RTLX_CHANNELS 8
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# define RTLX_CHANNEL_STDIO 0
# define RTLX_CHANNEL_DBG 1
# define RTLX_CHANNEL_SYSIO 2
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extern int rtlx_open ( int index , int can_sleep ) ;
extern int rtlx_release ( int index ) ;
extern ssize_t rtlx_read ( int index , void * buff , size_t count , int user ) ;
extern ssize_t rtlx_write ( int index , void * buffer , size_t count , int user ) ;
extern unsigned int rtlx_read_poll ( int index , int can_sleep ) ;
extern unsigned int rtlx_write_poll ( int index ) ;
enum rtlx_state {
RTLX_STATE_UNUSED ,
RTLX_STATE_INITIALISED ,
RTLX_STATE_REMOTE_READY ,
RTLX_STATE_OPENED
} ;
# define RTLX_BUFFER_SIZE 1024
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/* each channel supports read and write.
linux ( vpe0 ) reads lx_buffer and writes rt_buffer
SP ( vpe1 ) reads rt_buffer and writes lx_buffer
*/
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struct rtlx_channel {
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enum rtlx_state rt_state ;
enum rtlx_state lx_state ;
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int buffer_size ;
/* read and write indexes per buffer */
int rt_write , rt_read ;
char * rt_buffer ;
int lx_write , lx_read ;
char * lx_buffer ;
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} ;
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struct rtlx_info {
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unsigned long id ;
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enum rtlx_state state ;
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struct rtlx_channel channel [ RTLX_CHANNELS ] ;
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} ;
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# endif /* __ASM_RTLX_H_ */