2007-07-25 02:17:33 +04:00
/ * head. S : I n i t i a l b o o t c o d e f o r t h e S p a r c64 p o r t o f L i n u x .
2005-04-17 02:20:36 +04:00
*
2007-07-25 02:17:33 +04:00
* Copyright ( C ) 1 9 9 6 , 1 9 9 7 , 2 0 0 7 D a v i d S . M i l l e r ( d a v e m @davemloft.net)
2005-04-17 02:20:36 +04:00
* Copyright ( C ) 1 9 9 6 D a v i d S i t s k y ( D a v i d . S i t s k y @anu.edu.au)
2007-07-25 02:17:33 +04:00
* Copyright ( C ) 1 9 9 7 , 1 9 9 8 J a k u b J e l i n e k ( j j @sunsite.mff.cuni.cz)
2005-04-17 02:20:36 +04:00
* Copyright ( C ) 1 9 9 7 M i g u e l d e I c a z a ( m i g u e l @nuclecu.unam.mx)
* /
# include < l i n u x / v e r s i o n . h >
# include < l i n u x / e r r n o . h >
2006-05-31 12:24:02 +04:00
# include < l i n u x / t h r e a d s . h >
2007-07-25 02:17:33 +04:00
# include < l i n u x / i n i t . h >
2008-09-01 14:13:17 +04:00
# include < l i n u x / l i n k a g e . h >
2005-04-17 02:20:36 +04:00
# include < a s m / t h r e a d _ i n f o . h >
# include < a s m / a s i . h >
# include < a s m / p s t a t e . h >
# include < a s m / p t r a c e . h >
# include < a s m / s p i t f i r e . h >
# include < a s m / p a g e . h >
# include < a s m / p g t a b l e . h >
# include < a s m / e r r n o . h >
# include < a s m / s i g n a l . h >
# include < a s m / p r o c e s s o r . h >
# include < a s m / l s u . h >
# include < a s m / d c r . h >
# include < a s m / d c u . h >
# include < a s m / h e a d . h >
# include < a s m / t t a b l e . h >
# include < a s m / m m u . h >
2006-02-27 10:24:22 +03:00
# include < a s m / c p u d a t a . h >
2008-04-28 11:47:20 +04:00
# include < a s m / p i l . h >
# include < a s m / e s t a t e . h >
# include < a s m / s f a f s r . h >
# include < a s m / u n i s t d . h >
2005-04-17 02:20:36 +04:00
/ * This s e c t i o n f r o m f r o m _ s t a r t t o s p a r c64 _ b o o t _ e n d s h o u l d f i t i n t o
2005-10-12 23:22:46 +04:00
* 0 x0 0 0 0 0 0 0 0 0 0 4 0 4 0 0 0 t o 0 x00 0 0 0 0 0 0 0 0 4 0 8 0 0 0 .
2005-04-17 02:20:36 +04:00
* /
.text
.globl _ s t a r t , s t e x t , _ s t e x t
_start :
start :
_stext :
stext :
! 0 x0 0 0 0 0 0 0 0 0 0 4 0 4 0 0 0
b s p a r c64 _ b o o t
flushw / * F l u s h r e g i s t e r f i l e . * /
/ * This s t u f f h a s t o b e i n s y n c w i t h S I L O a n d o t h e r p o t e n t i a l b o o t l o a d e r s
* Fields s h o u l d b e k e p t u p w a r d c o m p a t i b l e a n d w h e n e v e r a n y c h a n g e i s m a d e ,
* HdrS v e r s i o n s h o u l d b e i n c r e m e n t e d .
* /
.global _ f l a g s , r a m _ f l a g s , r o o t _ d e v
.global _ r a m d i s k _ i m a g e , s p a r c _ r a m d i s k _ s i z e
.global sparc_ramdisk_image64
.ascii " HdrS"
.word LINUX_VERSION_CODE
/ * History :
*
* 0 x0 3 0 0 : S u p p o r t s b e i n g l o c a t e d a t o t h e r t h a n 0 x40 0 0
* 0 x0 2 0 2 : S u p p o r t s k e r n e l p a r a m s s t r i n g
* 0 x0 2 0 1 : S u p p o r t s r e b o o t _ c o m m a n d
* /
.half 0x0301 /* HdrS version */
root_flags :
.half 1
root_dev :
.half 0
ram_flags :
.half 0
sparc_ramdisk_image :
.word 0
sparc_ramdisk_size :
.word 0
.xword reboot_command
.xword bootstr_info
sparc_ramdisk_image64 :
.xword 0
.word _end
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
/* PROM cif handler code address is in %o4. */
sparc64_boot :
2006-12-12 08:06:55 +03:00
mov % o 4 , % l 7
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
2011-03-31 05:57:33 +04:00
/ * We n e e d t o r e m a p t h e k e r n e l . U s e p o s i t i o n i n d e p e n d e n t
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
* code t o r e m a p u s t o K E R N B A S E .
2005-04-17 02:20:36 +04:00
*
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
* SILO c a n i n v o k e u s w i t h 3 2 - b i t a d d r e s s m a s k i n g e n a b l e d ,
* so m a k e s u r e t h a t ' s c l e a r .
2005-04-17 02:20:36 +04:00
* /
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
rdpr % p s t a t e , % g 1
andn % g 1 , P S T A T E _ A M , % g 1
wrpr % g 1 , 0 x0 , % p s t a t e
ba,a ,p t % x c c , 1 f
2006-02-09 13:52:44 +03:00
.globl _ f i n d d e v _ n a m e , p r o m _ c h o s e n _ p a t h , p r o m _ r o o t _ n o d e
.globl _ g e t p r o p _ n a m e , p r o m _ m m u _ n a m e , p r o m _ p e e r _ n a m e
.globl _ c a l l m e t h o d _ n a m e , p r o m _ t r a n s l a t e _ n a m e , p r o m _ r o o t _ c o m p a t i b l e
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
.globl _ m a p _ n a m e , p r o m _ u n m a p _ n a m e , p r o m _ m m u _ i h a n d l e _ c a c h e
.globl _ b o o t _ m a p p e d _ p c , p r o m _ b o o t _ m a p p i n g _ m o d e
.globl _ b o o t _ m a p p i n g _ p h y s _ h i g h , p r o m _ b o o t _ m a p p i n g _ p h y s _ l o w
2007-08-09 04:11:39 +04:00
.globl _ c o m p a t i b l e _ n a m e , p r o m _ c p u _ p a t h , p r o m _ c p u _ c o m p a t i b l e
2007-09-16 22:51:15 +04:00
.globl _ s u n 4 v , s u n 4 v _ c h i p _ t y p e , p r o m _ s e t _ t r a p _ t a b l e _ n a m e
2006-02-09 13:52:44 +03:00
prom_peer_name :
.asciz " peer"
prom_compatible_name :
.asciz " compatible"
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
prom_finddev_name :
.asciz " finddevice"
prom_chosen_path :
.asciz " / chosen"
2007-08-09 04:11:39 +04:00
prom_cpu_path :
.asciz " / cpu"
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
prom_getprop_name :
.asciz " getprop"
prom_mmu_name :
.asciz " mmu"
prom_callmethod_name :
.asciz " call- m e t h o d "
prom_translate_name :
.asciz " translate"
prom_map_name :
.asciz " map"
prom_unmap_name :
.asciz " unmap"
2007-09-16 22:51:15 +04:00
prom_set_trap_table_name :
.asciz " SUNW,s e t - t r a p - t a b l e "
2006-02-09 13:52:44 +03:00
prom_sun4v_name :
2006-02-11 21:56:43 +03:00
.asciz " sun4 v "
2007-08-09 04:11:39 +04:00
prom_niagara_prefix :
.asciz " SUNW,U l t r a S P A R C - T "
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
prom_sparc_prefix :
2011-09-11 21:42:20 +04:00
.asciz " SPARC- "
2013-03-06 03:47:59 +04:00
prom_sparc64x_prefix :
.asciz " SPARC6 4 - X "
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
.align 4
2006-02-09 13:52:44 +03:00
prom_root_compatible :
.skip 64
2007-08-09 04:11:39 +04:00
prom_cpu_compatible :
.skip 64
2006-02-09 13:52:44 +03:00
prom_root_node :
.word 0
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
prom_mmu_ihandle_cache :
.word 0
prom_boot_mapped_pc :
.word 0
prom_boot_mapping_mode :
.word 0
.align 8
prom_boot_mapping_phys_high :
.xword 0
prom_boot_mapping_phys_low :
.xword 0
2006-02-09 13:52:44 +03:00
is_sun4v :
.word 0
2007-08-09 04:11:39 +04:00
sun4v_chip_type :
.word SUN4V_CHIP_INVALID
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
1 :
rd % p c , % l 0
2006-02-09 13:52:44 +03:00
mov ( 1 b - p r o m _ p e e r _ n a m e ) , % l 1
sub % l 0 , % l 1 , % l 1
mov 0 , % l 2
/* prom_root_node = prom_peer(0) */
stx % l 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ] ! s e r v i c e , " p e e r "
mov 1 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 1
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 1
stx % l 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 , 0
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] ! r e t 1
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
ldx [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] , % l 4 ! p r o m r o o t n o d e
mov ( 1 b - p r o m _ r o o t _ n o d e ) , % l 1
sub % l 0 , % l 1 , % l 1
stw % l 4 , [ % l 1 ]
mov ( 1 b - p r o m _ g e t p r o p _ n a m e ) , % l 1
mov ( 1 b - p r o m _ c o m p a t i b l e _ n a m e ) , % l 2
mov ( 1 b - p r o m _ r o o t _ c o m p a t i b l e ) , % l 5
sub % l 0 , % l 1 , % l 1
sub % l 0 , % l 2 , % l 2
sub % l 0 , % l 5 , % l 5
/ * prom_ g e t p r o p e r t y ( p r o m _ r o o t _ n o d e , " c o m p a t i b l e " ,
* & prom_ r o o t _ c o m p a t i b l e , 6 4 )
* /
stx % l 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ] ! s e r v i c e , " g e t p r o p "
mov 4 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 4
mov 1 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 1
stx % l 4 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 , p r o m _ r o o t _ n o d e
stx % l 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] ! a r g 2 , " c o m p a t i b l e "
stx % l 5 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x28 ] ! a r g 3 , & p r o m _ r o o t _ c o m p a t i b l e
mov 6 4 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x30 ] ! a r g 4 , s i z e
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x38 ] ! r e t 1
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
mov ( 1 b - p r o m _ f i n d d e v _ n a m e ) , % l 1
mov ( 1 b - p r o m _ c h o s e n _ p a t h ) , % l 2
mov ( 1 b - p r o m _ b o o t _ m a p p e d _ p c ) , % l 3
sub % l 0 , % l 1 , % l 1
sub % l 0 , % l 2 , % l 2
sub % l 0 , % l 3 , % l 3
stw % l 0 , [ % l 3 ]
sub % s p , ( 1 9 2 + 1 2 8 ) , % s p
/* chosen_node = prom_finddevice("/chosen") */
stx % l 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ] ! s e r v i c e , " f i n d d e v i c e "
mov 1 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 1
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 1
stx % l 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 , " / c h o s e n "
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] ! r e t 1
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
ldx [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] , % l 4 ! c h o s e n d e v i c e n o d e
mov ( 1 b - p r o m _ g e t p r o p _ n a m e ) , % l 1
mov ( 1 b - p r o m _ m m u _ n a m e ) , % l 2
mov ( 1 b - p r o m _ m m u _ i h a n d l e _ c a c h e ) , % l 5
sub % l 0 , % l 1 , % l 1
sub % l 0 , % l 2 , % l 2
sub % l 0 , % l 5 , % l 5
/* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
stx % l 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ] ! s e r v i c e , " g e t p r o p "
mov 4 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 4
mov 1 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 1
stx % l 4 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 , c h o s e n _ n o d e
stx % l 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] ! a r g 2 , " m m u "
stx % l 5 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x28 ] ! a r g 3 , & p r o m _ m m u _ i h a n d l e _ c a c h e
mov 4 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x30 ] ! a r g 4 , s i z e o f ( a r g 3 )
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x38 ] ! r e t 1
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
mov ( 1 b - p r o m _ c a l l m e t h o d _ n a m e ) , % l 1
mov ( 1 b - p r o m _ t r a n s l a t e _ n a m e ) , % l 2
sub % l 0 , % l 1 , % l 1
sub % l 0 , % l 2 , % l 2
lduw [ % l 5 ] , % l 5 ! p r o m _ m m u _ i h a n d l e _ c a c h e
stx % l 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ] ! s e r v i c e , " c a l l - m e t h o d "
mov 3 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 3
mov 5 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 5
stx % l 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 : " t r a n s l a t e "
stx % l 5 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] ! a r g 2 : p r o m _ m m u _ i h a n d l e _ c a c h e
2005-10-12 02:45:16 +04:00
/* PAGE align */
srlx % l 0 , 1 3 , % l 3
sllx % l 3 , 1 3 , % l 3
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x28 ] ! a r g 3 : v a d d r , o u r P C
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x30 ] ! r e s1
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x38 ] ! r e s2
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x40 ] ! r e s3
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x48 ] ! r e s4
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x50 ] ! r e s5
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
ldx [ % s p + 2 0 4 7 + 1 2 8 + 0 x40 ] , % l 1 ! t r a n s l a t i o n m o d e
mov ( 1 b - p r o m _ b o o t _ m a p p i n g _ m o d e ) , % l 4
sub % l 0 , % l 4 , % l 4
stw % l 1 , [ % l 4 ]
mov ( 1 b - p r o m _ b o o t _ m a p p i n g _ p h y s _ h i g h ) , % l 4
sub % l 0 , % l 4 , % l 4
ldx [ % s p + 2 0 4 7 + 1 2 8 + 0 x48 ] , % l 2 ! p h y s a d d r h i g h
stx % l 2 , [ % l 4 + 0 x0 ]
ldx [ % s p + 2 0 4 7 + 1 2 8 + 0 x50 ] , % l 3 ! p h y s a d d r l o w
2005-10-12 02:45:16 +04:00
/* 4MB align */
srlx % l 3 , 2 2 , % l 3
sllx % l 3 , 2 2 , % l 3
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
stx % l 3 , [ % l 4 + 0 x8 ]
/* Leave service as-is, "call-method" */
mov 7 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 7
mov 1 , % l 3
2005-09-23 07:31:29 +04:00
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 1
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
mov ( 1 b - p r o m _ m a p _ n a m e ) , % l 3
sub % l 0 , % l 3 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 : " m a p "
/* Leave arg2 as-is, prom_mmu_ihandle_cache */
mov - 1 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x28 ] ! a r g 3 : m o d e ( - 1 d e f a u l t )
2008-03-22 03:01:38 +03:00
/* 4MB align the kernel image size. */
set ( _ e n d - K E R N B A S E ) , % l 3
set ( ( 4 * 1 0 2 4 * 1 0 2 4 ) - 1 ) , % l 4
add % l 3 , % l 4 , % l 3
andn % l 3 , % l 4 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x30 ] ! a r g 4 : r o u n d u p ( k s i z e , 4 M B )
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
sethi % h i ( K E R N B A S E ) , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x38 ] ! a r g 5 : v a d d r ( K E R N B A S E )
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x40 ] ! a r g 6 : e m p t y
mov ( 1 b - p r o m _ b o o t _ m a p p i n g _ p h y s _ l o w ) , % l 3
sub % l 0 , % l 3 , % l 3
ldx [ % l 3 ] , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x48 ] ! a r g 7 : p h y s a d d r
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
add % s p , ( 1 9 2 + 1 2 8 ) , % s p
2006-02-09 13:52:44 +03:00
sethi % h i ( p r o m _ r o o t _ c o m p a t i b l e ) , % g 1
or % g 1 , % l o ( p r o m _ r o o t _ c o m p a t i b l e ) , % g 1
sethi % h i ( p r o m _ s u n 4 v _ n a m e ) , % g 7
or % g 7 , % l o ( p r o m _ s u n 4 v _ n a m e ) , % g 7
2006-02-11 21:56:43 +03:00
mov 5 , % g 3
2007-08-09 04:11:39 +04:00
90 : ldub [ % g 7 ] , % g 2
2006-02-09 13:52:44 +03:00
ldub [ % g 1 ] , % g 4
cmp % g 2 , % g 4
2007-08-09 04:11:39 +04:00
bne,p n % i c c , 8 0 f
2006-02-09 13:52:44 +03:00
add % g 7 , 1 , % g 7
subcc % g 3 , 1 , % g 3
2007-08-09 04:11:39 +04:00
bne,p t % x c c , 9 0 b
2006-02-09 13:52:44 +03:00
add % g 1 , 1 , % g 1
sethi % h i ( i s _ s u n 4 v ) , % g 1
or % g 1 , % l o ( i s _ s u n 4 v ) , % g 1
mov 1 , % g 7
stw % g 7 , [ % g 1 ]
2007-08-09 04:11:39 +04:00
/* cpu_node = prom_finddevice("/cpu") */
mov ( 1 b - p r o m _ f i n d d e v _ n a m e ) , % l 1
mov ( 1 b - p r o m _ c p u _ p a t h ) , % l 2
sub % l 0 , % l 1 , % l 1
sub % l 0 , % l 2 , % l 2
sub % s p , ( 1 9 2 + 1 2 8 ) , % s p
stx % l 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ] ! s e r v i c e , " f i n d d e v i c e "
mov 1 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 1
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 1
stx % l 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 , " / c p u "
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] ! r e t 1
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
ldx [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] , % l 4 ! c p u d e v i c e n o d e
mov ( 1 b - p r o m _ g e t p r o p _ n a m e ) , % l 1
mov ( 1 b - p r o m _ c o m p a t i b l e _ n a m e ) , % l 2
mov ( 1 b - p r o m _ c p u _ c o m p a t i b l e ) , % l 5
sub % l 0 , % l 1 , % l 1
sub % l 0 , % l 2 , % l 2
sub % l 0 , % l 5 , % l 5
/ * prom_ g e t p r o p e r t y ( c p u _ n o d e , " c o m p a t i b l e " ,
* & prom_ c p u _ c o m p a t i b l e , 6 4 )
* /
stx % l 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ] ! s e r v i c e , " g e t p r o p "
mov 4 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ] ! n u m _ a r g s , 4
mov 1 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ] ! n u m _ r e t s , 1
stx % l 4 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ] ! a r g 1 , c p u _ n o d e
stx % l 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ] ! a r g 2 , " c o m p a t i b l e "
stx % l 5 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x28 ] ! a r g 3 , & p r o m _ c p u _ c o m p a t i b l e
mov 6 4 , % l 3
stx % l 3 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x30 ] ! a r g 4 , s i z e
stx % g 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x38 ] ! r e t 1
call % l 7
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0 ! a r g u m e n t a r r a y
add % s p , ( 1 9 2 + 1 2 8 ) , % s p
sethi % h i ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
or % g 1 , % l o ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
sethi % h i ( p r o m _ n i a g a r a _ p r e f i x ) , % g 7
or % g 7 , % l o ( p r o m _ n i a g a r a _ p r e f i x ) , % g 7
mov 1 7 , % g 3
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
90 : ldub [ % g 7 ] , % g 2
ldub [ % g 1 ] , % g 4
cmp % g 2 , % g 4
bne,p n % i c c , 8 9 f
add % g 7 , 1 , % g 7
subcc % g 3 , 1 , % g 3
bne,p t % x c c , 9 0 b
add % g 1 , 1 , % g 1
ba,p t % x c c , 9 1 f
nop
89 : sethi % h i ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
or % g 1 , % l o ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
sethi % h i ( p r o m _ s p a r c _ p r e f i x ) , % g 7
or % g 7 , % l o ( p r o m _ s p a r c _ p r e f i x ) , % g 7
2011-09-11 21:42:20 +04:00
mov 6 , % g 3
2007-08-09 04:11:39 +04:00
90 : ldub [ % g 7 ] , % g 2
ldub [ % g 1 ] , % g 4
cmp % g 2 , % g 4
bne,p n % i c c , 4 f
add % g 7 , 1 , % g 7
subcc % g 3 , 1 , % g 3
bne,p t % x c c , 9 0 b
add % g 1 , 1 , % g 1
sethi % h i ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
or % g 1 , % l o ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
2011-09-11 21:42:20 +04:00
ldub [ % g 1 + 6 ] , % g 2
cmp % g 2 , ' T '
be,p t % x c c , 7 0 f
cmp % g 2 , ' M '
2013-03-06 03:47:59 +04:00
bne,p n % x c c , 4 9 f
2011-09-11 21:42:20 +04:00
nop
70 : ldub [ % g 1 + 7 ] , % g 2
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
cmp % g 2 , ' 3 '
be,p t % x c c , 5 f
mov S U N 4 V _ C H I P _ N I A G A R A 3 , % g 4
2011-09-11 21:42:20 +04:00
cmp % g 2 , ' 4 '
be,p t % x c c , 5 f
mov S U N 4 V _ C H I P _ N I A G A R A 4 , % g 4
cmp % g 2 , ' 5 '
be,p t % x c c , 5 f
mov S U N 4 V _ C H I P _ N I A G A R A 5 , % g 4
2013-03-06 03:47:59 +04:00
ba,p t % x c c , 4 9 f
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
nop
91 : sethi % h i ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
2007-08-09 04:11:39 +04:00
or % g 1 , % l o ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
ldub [ % g 1 + 1 7 ] , % g 2
cmp % g 2 , ' 1 '
be,p t % x c c , 5 f
mov S U N 4 V _ C H I P _ N I A G A R A 1 , % g 4
cmp % g 2 , ' 2 '
be,p t % x c c , 5 f
mov S U N 4 V _ C H I P _ N I A G A R A 2 , % g 4
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
2007-08-09 04:11:39 +04:00
4 :
2013-03-06 03:47:59 +04:00
/* Athena */
sethi % h i ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
or % g 1 , % l o ( p r o m _ c p u _ c o m p a t i b l e ) , % g 1
sethi % h i ( p r o m _ s p a r c64 x _ p r e f i x ) , % g 7
or % g 7 , % l o ( p r o m _ s p a r c64 x _ p r e f i x ) , % g 7
mov 9 , % g 3
41 : ldub [ % g 7 ] , % g 2
ldub [ % g 1 ] , % g 4
cmp % g 2 , % g 4
bne,p n % i c c , 4 9 f
add % g 7 , 1 , % g 7
subcc % g 3 , 1 , % g 3
bne,p t % x c c , 4 1 b
add % g 1 , 1 , % g 1
mov S U N 4 V _ C H I P _ S P A R C 6 4 X , % g 4
ba,p t % x c c , 5 f
nop
49 :
2007-08-09 04:11:39 +04:00
mov S U N 4 V _ C H I P _ U N K N O W N , % g 4
5 : sethi % h i ( s u n 4 v _ c h i p _ t y p e ) , % g 2
or % g 2 , % l o ( s u n 4 v _ c h i p _ t y p e ) , % g 2
stw % g 4 , [ % g 2 ]
80 :
2006-02-09 13:52:44 +03:00
BRANCH_ I F _ S U N 4 V ( g 1 , j u m p _ t o _ s u n 4 u _ i n i t )
2005-04-17 02:20:36 +04:00
BRANCH_ I F _ C H E E T A H _ B A S E ( g 1 ,g 7 ,c h e e t a h _ b o o t )
BRANCH_ I F _ C H E E T A H _ P L U S _ O R _ F O L L O W O N ( g 1 ,g 7 ,c h e e t a h _ p l u s _ b o o t )
ba,p t % x c c , s p i t f i r e _ b o o t
nop
cheetah_plus_boot :
/* Preserve OBP chosen DCU and DCR register settings. */
ba,p t % x c c , c h e e t a h _ g e n e r i c _ b o o t
nop
cheetah_boot :
mov D C R _ B P E | D C R _ R P E | D C R _ S I | D C R _ I F P O E | D C R _ M S , % g 1
wr % g 1 , % a s r18
sethi % u h i ( D C U _ M E | D C U _ R E | D C U _ H P E | D C U _ S P E | D C U _ S L | D C U _ W E ) , % g 7
or % g 7 , % u l o ( D C U _ M E | D C U _ R E | D C U _ H P E | D C U _ S P E | D C U _ S L | D C U _ W E ) , % g 7
sllx % g 7 , 3 2 , % g 7
or % g 7 , D C U _ D M | D C U _ I M | D C U _ D C | D C U _ I C , % g 7
stxa % g 7 , [ % g 0 ] A S I _ D C U _ C O N T R O L _ R E G
membar #S y n c
cheetah_generic_boot :
mov T S B _ E X T E N S I O N _ P , % g 3
stxa % g 0 , [ % g 3 ] A S I _ D M M U
stxa % g 0 , [ % g 3 ] A S I _ I M M U
membar #S y n c
mov T S B _ E X T E N S I O N _ S , % g 3
stxa % g 0 , [ % g 3 ] A S I _ D M M U
membar #S y n c
mov T S B _ E X T E N S I O N _ N , % g 3
stxa % g 0 , [ % g 3 ] A S I _ D M M U
stxa % g 0 , [ % g 3 ] A S I _ I M M U
membar #S y n c
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
ba,a ,p t % x c c , j u m p _ t o _ s u n 4 u _ i n i t
2005-04-17 02:20:36 +04:00
spitfire_boot :
/ * Typically P R O M h a s a l r e a d y e n a b l e d b o t h M M U ' s a n d b o t h o n - c h i p
* caches, b u t w e d o i t h e r e a n y w a y j u s t t o b e p a r a n o i d .
* /
mov ( L S U _ C O N T R O L _ I C | L S U _ C O N T R O L _ D C | L S U _ C O N T R O L _ I M | L S U _ C O N T R O L _ D M ) , % g 1
stxa % g 1 , [ % g 0 ] A S I _ L S U _ C O N T R O L
membar #S y n c
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-23 07:11:33 +04:00
jump_to_sun4u_init :
2005-04-17 02:20:36 +04:00
/ *
* Make s u r e w e a r e i n p r i v i l e g e d m o d e , h a v e a d d r e s s m a s k i n g ,
* using t h e o r d i n a r y g l o b a l s a n d h a v e e n a b l e d f l o a t i n g
* point.
*
* Again, t y p i c a l l y P R O M h a s l e f t % p i l a t 1 3 o r s i m i l a r , a n d
* ( PSTATE_ P R I V | P S T A T E _ P E F | P S T A T E _ I E ) i n % p s t a t e .
* /
wrpr % g 0 , ( P S T A T E _ P R I V | P S T A T E _ P E F | P S T A T E _ I E ) , % p s t a t e
wr % g 0 , 0 , % f p r s
set s u n 4 u _ i n i t , % g 2
jmpl % g 2 + % g 0 , % g 0
nop
2009-04-27 22:02:26 +04:00
_ _ REF
2005-04-17 02:20:36 +04:00
sun4u_init :
2006-02-11 21:56:43 +03:00
BRANCH_ I F _ S U N 4 V ( g 1 , s u n 4 v _ i n i t )
2005-04-17 02:20:36 +04:00
/* Set ctx 0 */
2006-02-08 09:13:05 +03:00
mov P R I M A R Y _ C O N T E X T , % g 7
2006-02-11 21:56:43 +03:00
stxa % g 0 , [ % g 7 ] A S I _ D M M U
2006-02-08 09:13:05 +03:00
membar #S y n c
mov S E C O N D A R Y _ C O N T E X T , % g 7
2006-02-11 21:56:43 +03:00
stxa % g 0 , [ % g 7 ] A S I _ D M M U
membar #S y n c
ba,p t % x c c , s u n 4 u _ c o n t i n u e
nop
2006-02-08 09:13:05 +03:00
2006-02-11 21:56:43 +03:00
sun4v_init :
/* Set ctx 0 */
mov P R I M A R Y _ C O N T E X T , % g 7
2006-02-08 09:13:05 +03:00
stxa % g 0 , [ % g 7 ] A S I _ M M U
2006-02-11 21:56:43 +03:00
membar #S y n c
2005-04-17 02:20:36 +04:00
2006-02-11 21:56:43 +03:00
mov S E C O N D A R Y _ C O N T E X T , % g 7
stxa % g 0 , [ % g 7 ] A S I _ M M U
membar #S y n c
ba,p t % x c c , n i a g a r a _ t l b _ f i x u p
nop
2005-04-17 02:20:36 +04:00
2006-02-11 21:56:43 +03:00
sun4u_continue :
2006-02-09 13:52:44 +03:00
BRANCH_ I F _ A N Y _ C H E E T A H ( g 1 , g 7 , c h e e t a h _ t l b _ f i x u p )
2005-04-17 02:20:36 +04:00
ba,p t % x c c , s p i t f i r e _ t l b _ f i x u p
nop
2006-02-08 03:09:12 +03:00
niagara_tlb_fixup :
mov 3 , % g 2 / * S e t T L B t y p e t o h y p e r v i s o r . * /
sethi % h i ( t l b _ t y p e ) , % g 1
stw % g 2 , [ % g 1 + % l o ( t l b _ t y p e ) ]
/* Patch copy/clear ops. */
2007-08-09 04:11:39 +04:00
sethi % h i ( s u n 4 v _ c h i p _ t y p e ) , % g 1
lduw [ % g 1 + % l o ( s u n 4 v _ c h i p _ t y p e ) ] , % g 1
cmp % g 1 , S U N 4 V _ C H I P _ N I A G A R A 1
be,p t % x c c , n i a g a r a _ p a t c h
cmp % g 1 , S U N 4 V _ C H I P _ N I A G A R A 2
2007-08-16 12:47:25 +04:00
be,p t % x c c , n i a g a r a2 _ p a t c h
2007-08-09 04:11:39 +04:00
nop
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
cmp % g 1 , S U N 4 V _ C H I P _ N I A G A R A 3
2011-09-11 21:42:20 +04:00
be,p t % x c c , n i a g a r a2 _ p a t c h
nop
cmp % g 1 , S U N 4 V _ C H I P _ N I A G A R A 4
2012-09-27 08:11:01 +04:00
be,p t % x c c , n i a g a r a4 _ p a t c h
2011-09-11 21:42:20 +04:00
nop
cmp % g 1 , S U N 4 V _ C H I P _ N I A G A R A 5
2012-09-27 08:11:01 +04:00
be,p t % x c c , n i a g a r a4 _ p a t c h
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-28 08:06:16 +04:00
nop
2007-08-09 04:11:39 +04:00
call g e n e r i c _ p a t c h _ c o p y o p s
nop
call g e n e r i c _ p a t c h _ b z e r o
nop
call g e n e r i c _ p a t c h _ p a g e o p s
nop
ba,a ,p t % x c c , 8 0 f
2012-09-27 08:11:01 +04:00
niagara4_patch :
call n i a g a r a4 _ p a t c h _ c o p y o p s
nop
2012-10-06 00:45:26 +04:00
call n i a g a r a4 _ p a t c h _ b z e r o
2012-09-27 08:11:01 +04:00
nop
call n i a g a r a4 _ p a t c h _ p a g e o p s
nop
ba,a ,p t % x c c , 8 0 f
2007-08-16 12:47:25 +04:00
niagara2_patch :
call n i a g a r a2 _ p a t c h _ c o p y o p s
nop
call n i a g a r a _ p a t c h _ b z e r o
nop
2011-08-02 05:18:57 +04:00
call n i a g a r a _ p a t c h _ p a g e o p s
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nop
ba,a ,p t % x c c , 8 0 f
2007-08-09 04:11:39 +04:00
niagara_patch :
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call n i a g a r a _ p a t c h _ c o p y o p s
nop
2006-02-22 01:29:42 +03:00
call n i a g a r a _ p a t c h _ b z e r o
nop
2006-02-08 03:09:12 +03:00
call n i a g a r a _ p a t c h _ p a g e o p s
nop
2007-08-09 04:11:39 +04:00
80 :
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/* Patch TLB/cache ops. */
call h y p e r v i s o r _ p a t c h _ c a c h e t l b o p s
nop
2006-02-09 13:52:44 +03:00
ba,p t % x c c , t l b _ f i x u p _ d o n e
nop
2005-04-17 02:20:36 +04:00
cheetah_tlb_fixup :
mov 2 , % g 2 / * S e t T L B t y p e t o c h e e t a h + . * /
BRANCH_ I F _ C H E E T A H _ P L U S _ O R _ F O L L O W O N ( g 1 ,g 7 ,1 f )
mov 1 , % g 2 / * S e t T L B t y p e t o c h e e t a h . * /
1 : sethi % h i ( t l b _ t y p e ) , % g 1
stw % g 2 , [ % g 1 + % l o ( t l b _ t y p e ) ]
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/* Patch copy/page operations to cheetah optimized versions. */
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call c h e e t a h _ p a t c h _ c o p y o p s
nop
2005-08-30 22:26:15 +04:00
call c h e e t a h _ p a t c h _ c o p y _ p a g e
nop
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call c h e e t a h _ p a t c h _ c a c h e t l b o p s
nop
ba,p t % x c c , t l b _ f i x u p _ d o n e
nop
spitfire_tlb_fixup :
/* Set TLB type to spitfire. */
mov 0 , % g 2
sethi % h i ( t l b _ t y p e ) , % g 1
stw % g 2 , [ % g 1 + % l o ( t l b _ t y p e ) ]
tlb_fixup_done :
sethi % h i ( i n i t _ t h r e a d _ u n i o n ) , % g 6
or % g 6 , % l o ( i n i t _ t h r e a d _ u n i o n ) , % g 6
ldx [ % g 6 + T I _ T A S K ] , % g 4
mov % s p , % l 6
wr % g 0 , A S I _ P , % a s i
mov 1 , % g 1
sllx % g 1 , T H R E A D _ S H I F T , % g 1
sub % g 1 , ( S T A C K F R A M E _ S Z + S T A C K _ B I A S ) , % g 1
add % g 6 , % g 1 , % s p
mov 0 , % f p
/ * Set p e r - c p u p o i n t e r i n i t i a l l y t o z e r o , t h i s m a k e s
* the b o o t - c p u u s e t h e i n - k e r n e l - i m a g e p e r - c p u a r e a s
* before s e t u p _ p e r _ c p u _ a r e a ( ) i s i n v o k e d .
* /
clr % g 5
wrpr % g 0 , 0 , % w s t a t e
wrpr % g 0 , 0 x0 , % t l
/* Clear the bss */
sethi % h i ( _ _ b s s _ s t a r t ) , % o 0
or % o 0 , % l o ( _ _ b s s _ s t a r t ) , % o 0
sethi % h i ( _ e n d ) , % o 1
or % o 1 , % l o ( _ e n d ) , % o 1
call _ _ b z e r o
sub % o 1 , % o 0 , % o 1
2006-11-17 00:38:57 +03:00
# ifdef C O N F I G _ L O C K D E P
/ * We h a v e t h i s c a l l t h i s s u p e r e a r l y , a s e v e n p r o m _ i n i t c a n g r a b
* spinlocks a n d t h u s c a l l i n t o t h e l o c k d e p c o d e .
* /
call l o c k d e p _ i n i t
nop
# endif
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mov % l 6 , % o 1 ! O p e n P R O M s t a c k
call p r o m _ i n i t
mov % l 7 , % o 0 ! O p e n P R O M c i f h a n d l e r
2006-05-31 12:24:02 +04:00
/ * Initialize c u r r e n t _ t h r e a d _ i n f o ( ) - > c p u a s e a r l y a s p o s s i b l e .
* In o r d e r t o d o t h a t a c c u r a t e l y w e h a v e t o p a t c h u p t h e g e t _ c p u i d ( )
* assembler s e q u e n c e s . A n d t h a t , i n t u r n , r e q u i r e s t h a t w e k n o w
* if w e a r e o n a S t a r f i r e b o x o r n o t . W h i l e w e ' r e h e r e , p a t c h u p
* the s u n 4 v s e q u e n c e s a s w e l l .
* /
call c h e c k _ i f _ s t a r f i r e
nop
call p e r _ c p u _ p a t c h
nop
call s u n 4 v _ p a t c h
nop
# ifdef C O N F I G _ S M P
call h a r d _ s m p _ p r o c e s s o r _ i d
nop
cmp % o 0 , N R _ C P U S
blu,p t % x c c , 1 f
nop
call b o o t _ c p u _ i d _ t o o _ l a r g e
nop
/* Not reached... */
1 :
# else
mov 0 , % o 0
# endif
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sth % o 0 , [ % g 6 + T I _ C P U ]
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2008-02-07 13:14:48 +03:00
call p r o m _ i n i t _ r e p o r t
nop
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/* Off we go.... */
call s t a r t _ k e r n e l
nop
/* Not reached... */
2007-07-25 02:17:33 +04:00
.previous
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/ * This i s m e a n t t o a l l o w t h e s h a r i n g o f t h i s c o d e b e t w e e n
* boot p r o c e s s o r i n v o c a t i o n ( v i a s e t u p _ t b a ( ) b e l o w ) a n d
* secondary p r o c e s s o r s t a r t u p ( v i a t r a m p o l i n e . S ) . T h e
* former d o e s u s e t h i s c o d e , t h e l a t t e r d o e s n o t y e t d u e
* to s o m e c o m p l e x i t i e s . T h a t s h o u l d b e f i x e d u p a t s o m e
* point.
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*
* There u s e d t o b e e n o r m o u s c o m p l e x i t y w r t . t r a n s f e r r i n g
2009-01-26 13:06:57 +03:00
* over f r o m t h e f i r m w a r e ' s t r a p t a b l e t o t h e L i n u x k e r n e l ' s .
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* For e x a m p l e , t h e r e w a s a c h i c k e n & e g g p r o b l e m w r t . b u i l d i n g
* the O B P p a g e t a b l e s , y e t n e e d i n g t o b e o n t h e L i n u x k e r n e l
* trap t a b l e ( t o t r a n s l a t e P A G E _ O F F S E T a d d r e s s e s ) i n o r d e r t o
* do t h a t .
*
* We n o w h a n d l e O B P t l b m i s s e s d i f f e r e n t l y , v i a l i n e a r l o o k u p s
* into t h e p r o m _ t r a n s [ ] a r r a y . S o t h a t s p e c i f i c p r o b l e m n o
* longer e x i s t s . Y e t , u n f o r t u n a t e l y t h e r e a r e s t i l l s o m e i s s u e s
* preventing t r a m p o l i n e . S f r o m u s i n g t h i s c o d e . . . h o h u m .
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* /
.globl setup_trap_table
setup_trap_table :
save % s p , - 1 9 2 , % s p
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/* Force interrupts to be disabled. */
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rdpr % p s t a t e , % l 0
andn % l 0 , P S T A T E _ I E , % o 1
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wrpr % o 1 , 0 x0 , % p s t a t e
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rdpr % p i l , % l 1
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wrpr % g 0 , P I L _ N O R M A L _ M A X , % p i l
2005-04-17 02:20:36 +04:00
2005-10-12 23:22:46 +04:00
/* Make the firmware call to jump over to the Linux trap table. */
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sethi % h i ( i s _ s u n 4 v ) , % o 0
lduw [ % o 0 + % l o ( i s _ s u n 4 v ) ] , % o 0
brz,p t % o 0 , 1 f
nop
TRAP_ L O A D _ T R A P _ B L O C K ( % g 2 , % g 3 )
add % g 2 , T R A P _ P E R _ C P U _ F A U L T _ I N F O , % g 2
stxa % g 2 , [ % g 0 ] A S I _ S C R A T C H P A D
/ * Compute p h y s i c a l a d d r e s s :
*
* paddr = k e r n _ b a s e + ( m m f s a _ v a d d r - K E R N B A S E )
* /
sethi % h i ( K E R N B A S E ) , % g 3
sub % g 2 , % g 3 , % g 2
sethi % h i ( k e r n _ b a s e ) , % g 3
ldx [ % g 3 + % l o ( k e r n _ b a s e ) ] , % g 3
add % g 2 , % g 3 , % o 1
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sethi % h i ( s p a r c64 _ t t a b l e _ t l 0 ) , % o 0
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set p r o m _ s e t _ t r a p _ t a b l e _ n a m e , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ]
mov 2 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ]
mov 0 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ]
stx % o 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ]
stx % o 1 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x20 ]
sethi % h i ( p12 7 5 b u f ) , % g 2
or % g 2 , % l o ( p12 7 5 b u f ) , % g 2
ldx [ % g 2 + 0 x08 ] , % o 1
call % o 1
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0
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ba,p t % x c c , 2 f
nop
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1 : sethi % h i ( s p a r c64 _ t t a b l e _ t l 0 ) , % o 0
set p r o m _ s e t _ t r a p _ t a b l e _ n a m e , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x00 ]
mov 1 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x08 ]
mov 0 , % g 2
stx % g 2 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x10 ]
stx % o 0 , [ % s p + 2 0 4 7 + 1 2 8 + 0 x18 ]
sethi % h i ( p12 7 5 b u f ) , % g 2
or % g 2 , % l o ( p12 7 5 b u f ) , % g 2
ldx [ % g 2 + 0 x08 ] , % o 1
call % o 1
add % s p , ( 2 0 4 7 + 1 2 8 ) , % o 0
2005-10-11 03:12:13 +04:00
/* Start using proper page size encodings in ctx register. */
2006-02-11 02:39:51 +03:00
2 : sethi % h i ( s p a r c64 _ k e r n _ p r i _ c o n t e x t ) , % g 3
2005-10-11 03:12:13 +04:00
ldx [ % g 3 + % l o ( s p a r c64 _ k e r n _ p r i _ c o n t e x t ) ] , % g 2
2006-02-08 09:13:05 +03:00
mov P R I M A R Y _ C O N T E X T , % g 1
661 : stxa % g 2 , [ % g 1 ] A S I _ D M M U
.section .sun4v_1insn_patch , " ax"
.word 661b
stxa % g 2 , [ % g 1 ] A S I _ M M U
.previous
2005-10-11 03:12:13 +04:00
membar #S y n c
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BRANCH_ I F _ S U N 4 V ( o 2 , 1 f )
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/* Kill PROM timer */
sethi % h i ( 0 x80 0 0 0 0 0 0 ) , % o 2
sllx % o 2 , 3 2 , % o 2
wr % o 2 , 0 , % t i c k _ c m p r
2006-02-09 13:52:44 +03:00
BRANCH_ I F _ A N Y _ C H E E T A H ( o 2 , o 3 , 1 f )
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ba,p t % x c c , 2 f
nop
/* Disable STICK_INT interrupts. */
1 :
sethi % h i ( 0 x80 0 0 0 0 0 0 ) , % o 2
sllx % o 2 , 3 2 , % o 2
wr % o 2 , % a s r25
2 :
wrpr % g 0 , % g 0 , % w s t a t e
call i n i t _ i r q w o r k _ c u r c p u
nop
2006-07-14 03:05:26 +04:00
/* Now we can restore interrupt state. */
wrpr % l 0 , 0 , % p s t a t e
wrpr % l 1 , 0 x0 , % p i l
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ret
restore
.globl setup_tba
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setup_tba :
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save % s p , - 1 9 2 , % s p
/ * The b o o t p r o c e s s o r i s t h e o n l y c p u w h i c h i n v o k e s t h i s
* routine, t h e o t h e r c p u s s e t t h i n g s u p v i a t r a m p o l i n e . S .
* So s a v e t h e O B P t r a p t a b l e a d d r e s s h e r e .
* /
rdpr % t b a , % g 7
sethi % h i ( p r o m _ t b a ) , % o 1
or % o 1 , % l o ( p r o m _ t b a ) , % o 1
stx % g 7 , [ % o 1 ]
call s e t u p _ t r a p _ t a b l e
nop
2005-04-17 02:20:36 +04:00
ret
restore
2005-10-12 23:22:46 +04:00
sparc64_boot_end :
2008-12-03 14:11:52 +03:00
# include " e t r a p _ 6 4 . S "
# include " r t r a p _ 6 4 . S "
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# include " w i n f i x u p . S "
2008-04-28 11:47:20 +04:00
# include " f p u _ t r a p s . S "
# include " i v e c . S "
# include " g e t s e t c c . S "
# include " u t r a p . S "
# include " s p i t e r r s . S "
# include " c h e r r s . S "
# include " m i s c t r a p . S "
# include " s y s c a l l s . S "
# include " h e l p e r s . S "
# include " h v c a l l s . S "
2006-02-08 13:53:50 +03:00
# include " s u n 4 v _ t l b _ m i s s . S "
# include " s u n 4 v _ i v e c . S "
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# include " k t l b . S "
# include " t s b . S "
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/ *
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* The f o l l o w i n g s k i p m a k e s s u r e t h e t r a p t a b l e i n t t a b l e . S i s a l i g n e d
2005-04-17 02:20:36 +04:00
* on a 3 2 K b o u n d a r y a s r e q u i r e d b y t h e v9 s p e c s f o r T B A r e g i s t e r .
2006-02-01 05:33:49 +03:00
*
* We a l i g n t o a 3 2 K b o u n d a r y , t h e n w e h a v e t h e 3 2 K k e r n e l T S B ,
2007-05-29 12:58:31 +04:00
* the 6 4 K k e r n e l 4 M B T S B , a n d t h e n t h e 3 2 K a l i g n e d t r a p t a b l e .
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* /
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1 :
.skip 0x4000 + _ start - 1 b
2005-04-17 02:20:36 +04:00
2007-05-29 12:58:31 +04:00
! 0 x0 0 0 0 0 0 0 0 0 0 4 0 8 0 0 0
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.globl swapper_tsb
swapper_tsb :
.skip ( 3 2 * 1 0 2 4 )
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2007-05-29 12:58:31 +04:00
.globl swapper_4m_tsb
swapper_4m_tsb :
.skip ( 6 4 * 1 0 2 4 )
! 0 x0 0 0 0 0 0 0 0 0 0 4 2 0 0 0 0
2005-04-17 02:20:36 +04:00
2007-05-29 12:58:31 +04:00
/ * Some c a r e n e e d s t o b e e x e r c i s e d i f y o u t r y t o m o v e t h e
* location o f t h e t r a p t a b l e r e l a t i v e t o o t h e r t h i n g s . F o r
* one t h i n g t h e r e a r e b r * i n s t r u c t i o n s i n s o m e o f t h e
* trap t a b l e e n t i r e s w h i c h b r a n c h b a c k t o c o d e i n k t l b . S
* Those i n s t r u c t i o n s c a n o n l y h a n d l e a s i g n e d 1 6 - b i t
* displacement.
*
* There i s a b i n u t i l s b u g ( b u g z i l l a #4558 ) w h i c h c a u s e s
* the r e l o c a t i o n o v e r f l o w c h e c k s f o r s u c h i n s t r u c t i o n s t o
* not b e d o n e c o r r e c t l y . S o b i n t u i l s w i l l n o t n o t i c e t h e
* error a n d w i l l i n s t e a d w r i t e j u n k i n t o t h e r e l o c a t i o n a n d
* you' l l h a v e a n u n b o o t a b l e k e r n e l .
* /
2012-05-20 00:02:44 +04:00
# include " t t a b l e _ 6 4 . S "
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2007-05-29 12:58:31 +04:00
! 0 x0 0 0 0 0 0 0 0 0 0 4 2 8 0 0 0
2008-12-03 14:11:52 +03:00
# include " s y s t b l s _ 6 4 . S "
2006-02-23 13:28:25 +03:00
2005-04-17 02:20:36 +04:00
.data
.align 8
.globl _ t b a , t l b _ t y p e
prom_tba : .xword 0
tlb_type : .word 0 /* Must NOT end up in BSS */
.section " .fixup " , # alloc,#e x e c i n s t r
2005-09-29 07:41:45 +04:00
2009-02-09 09:00:55 +03:00
.globl _ _ ret_ e f a u l t , _ _ r e t l _ e f a u l t , _ _ r e t _ o n e , _ _ r e t l _ o n e
ENTRY( _ _ r e t _ e f a u l t )
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ret
restore % g 0 , - E F A U L T , % o 0
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ENDPROC( _ _ r e t _ e f a u l t )
ENTRY( _ _ r e t l _ e f a u l t )
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retl
mov - E F A U L T , % o 0
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ENDPROC( _ _ r e t l _ e f a u l t )
ENTRY( _ _ r e t l _ o n e )
retl
mov 1 , % o 0
ENDPROC( _ _ r e t l _ o n e )
ENTRY( _ _ r e t _ o n e _ a s i )
wr % g 0 , A S I _ A I U S , % a s i
ret
restore % g 0 , 1 , % o 0
ENDPROC( _ _ r e t _ o n e _ a s i )
ENTRY( _ _ r e t l _ o n e _ a s i )
wr % g 0 , A S I _ A I U S , % a s i
retl
mov 1 , % o 0
ENDPROC( _ _ r e t l _ o n e _ a s i )
ENTRY( _ _ r e t l _ o 1 )
retl
mov % o 1 , % o 0
ENDPROC( _ _ r e t l _ o 1 )
