2012-06-18 00:47:26 -06:00
/*
* AM33XX Power Management register bits
*
* This file is automatically generated from the AM33XX hardware databases .
* Vaibhav Hiremath < hvaibhav @ ti . com >
*
* Copyright ( C ) 2011 - 2012 Texas Instruments Incorporated - http : //www.ti.com/
*
* This program is free software ; you can redistribute it and / or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed " as is " WITHOUT ANY WARRANTY of any
* kind , whether express or implied ; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the
* GNU General Public License for more details .
*/
# ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
# define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
# define AM33XX_CLKOUT2DIV_SHIFT 3
2012-09-19 18:05:15 -06:00
# define AM33XX_CLKOUT2DIV_WIDTH 3
2012-06-18 00:47:26 -06:00
# define AM33XX_CLKOUT2EN_SHIFT 7
2012-09-19 18:05:15 -06:00
# define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
2012-06-18 00:47:26 -06:00
# define AM33XX_CLKSEL_0_0_SHIFT 0
2012-09-19 18:05:15 -06:00
# define AM33XX_CLKSEL_0_0_WIDTH 1
2012-06-18 00:47:26 -06:00
# define AM33XX_CLKSEL_0_0_MASK (1 << 0)
# define AM33XX_CLKSEL_0_1_MASK (3 << 0)
# define AM33XX_CLKSEL_0_2_MASK (7 << 0)
# define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
# define AM33XX_CLKTRCTRL_SHIFT 0
# define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
# define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
2012-09-19 18:05:15 -06:00
# define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
2012-06-18 00:47:26 -06:00
# define AM33XX_DPLL_DIV_MASK (0x7f << 0)
# define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
# define AM33XX_DPLL_EN_MASK (0x7 << 0)
# define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
# define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
# define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
2012-09-19 18:05:15 -06:00
# define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
2012-06-18 00:47:26 -06:00
# define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
2012-09-19 18:05:15 -06:00
# define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
2012-06-18 00:47:26 -06:00
# define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
2012-09-19 18:05:15 -06:00
# define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
2012-06-18 00:47:26 -06:00
# define AM33XX_IDLEST_SHIFT 16
# define AM33XX_IDLEST_MASK (0x3 << 16)
# define AM33XX_MODULEMODE_SHIFT 0
# define AM33XX_MODULEMODE_MASK (0x3 << 0)
# define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
# define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
# define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
# define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
# define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
# define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
# define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
2012-09-19 18:05:15 -06:00
# define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
2012-06-18 00:47:26 -06:00
# define AM33XX_STM_PMD_CLKSEL_SHIFT 22
2012-09-19 18:05:15 -06:00
# define AM33XX_STM_PMD_CLKSEL_WIDTH 2
2012-06-18 00:47:26 -06:00
# define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
# define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
# define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
2012-09-19 18:05:15 -06:00
# define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
2012-06-18 00:47:26 -06:00
# define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
2012-09-19 18:05:15 -06:00
# define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
2012-06-18 00:47:26 -06:00
# endif
