irqchip: add basic infrastructure
With the recent creation of the drivers/irqchip/ directory, it is
desirable to move irq controller drivers here. At the moment, the only
driver here is irq-bcm2835, the driver for the irq controller found in
the ARM BCM2835 SoC, present in Rasberry Pi systems. This irq
controller driver was exporting its initialization function and its
irq handling function through a header file in
<linux/irqchip/bcm2835.h>.
When proposing to also move another irq controller driver in
drivers/irqchip, Rob Herring raised the very valid point that moving
things to drivers/irqchip was good in order to remove more stuff from
arch/arm, but if it means adding gazillions of headers files in
include/linux/irqchip/, it would not be very nice.
So, upon the suggestion of Rob Herring and Arnd Bergmann, this commit
introduces a small infrastructure that defines a central
irqchip_init() function in drivers/irqchip/irqchip.c, which is meant
to be called as the ->init_irq() callback of ARM platforms. This
function calls of_irq_init() with an array of match strings and init
functions generated from a special linker section.
Note that the irq controller driver initialization function is
responsible for setting the global handle_arch_irq() variable, so that
ARM platforms no longer have to define the ->handle_irq field in their
DT_MACHINE structure.
A global header, <linux/irqchip.h> is also added to expose the single
irqchip_init() function to the reset of the kernel.
A further commit moves the BCM2835 irq controller driver to this new
small infrastructure, therefore removing the include/linux/irqchip/
directory.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[rob.herring: reword commit message to reflect use of linker sections.]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-11-21 02:00:52 +04:00
config IRQCHIP
def_bool y
depends on OF_IRQ
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config ARM_GIC
bool
select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select MULTI_IRQ_HANDLER
irqchip/gic: Add platform driver for non-root GICs that require RPM
Add a platform driver to support non-root GICs that require runtime
power-management. Currently, only non-root GICs are supported because
the functions, smp_cross_call() and set_handle_irq(), that need to
be called for a root controller are located in the __init section and
so cannot be called by the platform driver.
The GIC platform driver re-uses many functions from the existing GIC
driver including some functions to save and restore the GIC context
during power transitions. The functions for saving and restoring the
GIC context are currently only defined if CONFIG_CPU_PM is enabled and
to ensure that these functions are always defined when the platform
driver is enabled, a dependency on CONFIG_ARM_GIC_PM (which selects the
platform driver) has been added.
In order to re-use the private GIC initialisation code, a new public
function, gic_of_init_child(), has been added which calls various
private functions to initialise the GIC. This is different from the
existing gic_of_init() because it only supports non-root GICs (ie. does
not call smp_cross_call() is set_handle_irq()) and is not located in
the __init section (so can be used by platform drivers). Furthermore,
gic_of_init_child() dynamically allocates memory for the GIC chip data
which is also different from gic_of_init().
There is no specific suspend handling for GICs registered as platform
devices. Non-wakeup interrupts will be disabled by the kernel during
late suspend, however, this alone will not power down the GIC if
interrupts have been requested and not freed. Therefore, requestors of
non-wakeup interrupts will need to free them on entering suspend in
order to power-down the GIC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-06-07 18:12:34 +03:00
config ARM_GIC_PM
bool
depends on PM
select ARM_GIC
select PM_CLK
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config ARM_GIC_MAX_NR
int
default 2 if ARCH_REALVIEW
default 1
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config ARM_GIC_V2M
bool
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depends on PCI
select ARM_GIC
select PCI_MSI
2014-11-25 21:47:22 +03:00
2012-11-21 07:21:40 +04:00
config GIC_NON_BANKED
bool
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config ARM_GIC_V3
bool
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
2014-06-30 19:01:31 +04:00
2014-11-24 17:35:19 +03:00
config ARM_GIC_V3_ITS
bool
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depends on PCI
depends on PCI_MSI
2014-06-30 19:01:31 +04:00
2013-06-26 11:18:48 +04:00
config ARM_NVIC
bool
select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_CHIP
2012-10-28 02:25:26 +04:00
config ARM_VIC
bool
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
config ARM_VIC_NR
int
default 4 if ARCH_S5PV210
default 2
depends on ARM_VIC
help
The maximum number of VICs available in the system, for
power management.
2016-02-10 17:46:56 +03:00
config ARMADA_370_XP_IRQ
bool
select GENERIC_IRQ_CHIP
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select PCI_MSI if PCI
2016-02-10 17:46:56 +03:00
2016-02-19 18:22:44 +03:00
config ALPINE_MSI
bool
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depends on PCI
select PCI_MSI
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select GENERIC_IRQ_CHIP
2014-07-10 21:14:18 +04:00
config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
config ATMEL_AIC5_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
2015-07-08 15:46:08 +03:00
config I8259
bool
select IRQ_DOMAIN
2015-11-22 17:30:14 +03:00
config BCM6345_L1_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-25 20:49:06 +03:00
config BCM7038_L1_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config BCM7120_L2_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config BRCMSTB_L2_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config DW_APB_ICTL
bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config HISILICON_IRQ_MBIGEN
bool
select ARM_GIC_V3
select ARM_GIC_V3_ITS
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config IMGPDC_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config IRQ_MIPS_CPU
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
2014-02-02 12:07:46 +04:00
config CLPS711X_IRQCHIP
bool
depends on ARCH_CLPS711X
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
default y
2014-05-27 00:31:42 +04:00
config OR1K_PIC
bool
select IRQ_DOMAIN
2014-09-16 01:15:02 +04:00
config OMAP_IRQCHIP
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config ORION_IRQCHIP
bool
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
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config PIC32_EVIC
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config RENESAS_INTC_IRQPIN
bool
select IRQ_DOMAIN
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config RENESAS_IRQC
bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ST_IRQCHIP
bool
select REGMAP
select MFD_SYSCON
help
Enables SysCfg Controlled IRQs on STi based platforms.
2016-01-20 21:07:17 +03:00
config TANGO_IRQ
bool
select IRQ_DOMAIN
select GENERIC_IRQ_CHIP
2013-06-25 20:29:57 +04:00
config TB10X_IRQC
bool
select IRQ_DOMAIN
select GENERIC_IRQ_CHIP
2015-12-21 23:11:23 +03:00
config TS4800_IRQ
tristate "TS-4800 IRQ controller"
select IRQ_DOMAIN
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depends on HAS_IOMEM
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depends on SOC_IMX51 || COMPILE_TEST
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help
Support for the TS-4800 FPGA IRQ controller
2012-11-01 01:04:31 +04:00
config VERSATILE_FPGA_IRQ
bool
select IRQ_DOMAIN
config VERSATILE_FPGA_IRQ_NR
int
default 4
depends on VERSATILE_FPGA_IRQ
2013-12-01 12:04:57 +04:00
config XTENSA_MX
bool
select IRQ_DOMAIN
2013-12-03 14:27:23 +04:00
config IRQ_CROSSBAR
bool
help
2014-09-18 07:09:42 +04:00
Support for a CROSSBAR ip that precedes the main interrupt controller.
2013-12-03 14:27:23 +04:00
The primary irqchip invokes the crossbar's callback which inturn allocates
a free irq and configures the IP. Thus the peripheral interrupts are
routed to one of the free irqchip interrupt lines.
2014-07-23 18:40:30 +04:00
config KEYSTONE_IRQ
tristate "Keystone 2 IRQ controller IP"
depends on ARCH_KEYSTONE
help
Support for Texas Instruments Keystone 2 IRQ controller IP which
is part of the Keystone 2 IPC mechanism
2014-09-19 01:47:19 +04:00
config MIPS_GIC
bool
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select GENERIC_IRQ_IPI
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select IRQ_DOMAIN_HIERARCHY
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select MIPS_CM
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2015-05-24 18:11:31 +03:00
config INGENIC_IRQ
bool
depends on MACH_INGENIC
default y
2015-06-27 22:44:34 +03:00
2015-05-09 20:30:47 +03:00
config RENESAS_H8300H_INTC
bool
select IRQ_DOMAIN
config RENESAS_H8S_INTC
bool
2015-06-27 22:44:34 +03:00
select IRQ_DOMAIN
2015-08-24 22:04:15 +03:00
config IMX_GPCV2
bool
select IRQ_DOMAIN
help
Enables the wakeup IRQs for IMX platforms with GPCv2 block
2015-10-12 22:15:34 +03:00
config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
2016-02-19 16:34:43 +03:00
config MVEBU_ODMI
bool
irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 11:57:53 +03:00
2016-03-23 14:08:20 +03:00
config LS_SCFG_MSI
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
depends on PCI && PCI_MSI
irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 11:57:53 +03:00
config PARTITION_PERCPU
bool
2016-05-19 19:46:18 +03:00
2015-10-29 01:26:22 +03:00
config EZNPS_GIC
bool "NPS400 Global Interrupt Manager (GIM)"
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depends on ARC || (COMPILE_TEST && !64BIT)
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select IRQ_DOMAIN
help
Support the EZchip NPS400 global interrupt controller
