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/*
* Copyright 2014 Advanced Micro Devices , Inc .
*
* Permission is hereby granted , free of charge , to any person obtaining a
* copy of this software and associated documentation files ( the " Software " ) ,
* to deal in the Software without restriction , including without limitation
* the rights to use , copy , modify , merge , publish , distribute , sublicense ,
* and / or sell copies of the Software , and to permit persons to whom the
* Software is furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL
* THE COPYRIGHT HOLDER ( S ) OR AUTHOR ( S ) BE LIABLE FOR ANY CLAIM , DAMAGES OR
* OTHER LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE ,
* ARISING FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE .
*
*/
# ifndef __AMDGPU_UVD_H__
# define __AMDGPU_UVD_H__
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# define AMDGPU_DEFAULT_UVD_HANDLES 10
# define AMDGPU_MAX_UVD_HANDLES 40
# define AMDGPU_UVD_STACK_SIZE (200*1024)
# define AMDGPU_UVD_HEAP_SIZE (256*1024)
# define AMDGPU_UVD_SESSION_SIZE (50*1024)
# define AMDGPU_UVD_FIRMWARE_OFFSET 256
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# define AMDGPU_MAX_UVD_INSTANCES 2
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# define AMDGPU_UVD_FIRMWARE_SIZE(adev) \
( AMDGPU_GPU_PAGE_ALIGN ( le32_to_cpu ( ( ( const struct common_firmware_header * ) ( adev ) - > uvd . fw - > data ) - > ucode_size_bytes ) + \
8 ) - AMDGPU_UVD_FIRMWARE_OFFSET )
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struct amdgpu_uvd_inst {
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struct amdgpu_bo * vcpu_bo ;
void * cpu_addr ;
uint64_t gpu_addr ;
void * saved_bo ;
struct amdgpu_ring ring ;
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struct amdgpu_ring ring_enc [ AMDGPU_MAX_UVD_ENC_RINGS ] ;
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struct amdgpu_irq_src irq ;
uint32_t srbm_soft_reset ;
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} ;
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# define AMDGPU_UVD_HARVEST_UVD0 (1 << 0)
# define AMDGPU_UVD_HARVEST_UVD1 (1 << 1)
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struct amdgpu_uvd {
const struct firmware * fw ; /* UVD firmware */
unsigned fw_version ;
unsigned max_handles ;
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unsigned num_enc_rings ;
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uint8_t num_uvd_inst ;
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bool address_64_bit ;
bool use_ctx_buf ;
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struct amdgpu_uvd_inst inst [ AMDGPU_MAX_UVD_INSTANCES ] ;
struct drm_file * filp [ AMDGPU_MAX_UVD_HANDLES ] ;
atomic_t handles [ AMDGPU_MAX_UVD_HANDLES ] ;
struct drm_sched_entity entity ;
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struct delayed_work idle_work ;
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unsigned harvest_config ;
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} ;
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int amdgpu_uvd_sw_init ( struct amdgpu_device * adev ) ;
int amdgpu_uvd_sw_fini ( struct amdgpu_device * adev ) ;
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int amdgpu_uvd_entity_init ( struct amdgpu_device * adev ) ;
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int amdgpu_uvd_suspend ( struct amdgpu_device * adev ) ;
int amdgpu_uvd_resume ( struct amdgpu_device * adev ) ;
int amdgpu_uvd_get_create_msg ( struct amdgpu_ring * ring , uint32_t handle ,
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struct dma_fence * * fence ) ;
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int amdgpu_uvd_get_destroy_msg ( struct amdgpu_ring * ring , uint32_t handle ,
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bool direct , struct dma_fence * * fence ) ;
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void amdgpu_uvd_free_handles ( struct amdgpu_device * adev ,
struct drm_file * filp ) ;
int amdgpu_uvd_ring_parse_cs ( struct amdgpu_cs_parser * parser , uint32_t ib_idx ) ;
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void amdgpu_uvd_ring_begin_use ( struct amdgpu_ring * ring ) ;
void amdgpu_uvd_ring_end_use ( struct amdgpu_ring * ring ) ;
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int amdgpu_uvd_ring_test_ib ( struct amdgpu_ring * ring , long timeout ) ;
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uint32_t amdgpu_uvd_used_handles ( struct amdgpu_device * adev ) ;
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# endif