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/ * arch/ a r m / m a c h - i m x / i n c l u d e / m a c h / d e b u g - m a c r o . S
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*
* Debugging m a c r o i n c l u d e h e a d e r
*
* Copyright ( C ) 1 9 9 4 - 1 9 9 9 R u s s e l l K i n g
* Moved f r o m l i n u x / a r c h / a r m / k e r n e l / d e b u g . S b y B e n D o o k s
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
*
* /
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# include < m a c h / h a r d w a r e . h >
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# ifdef C O N F I G _ D E B U G _ I M X 1 _ U A R T
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# define U A R T _ P A D D R M X 1 _ U A R T 1 _ B A S E _ A D D R
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# elif d e f i n e d ( C O N F I G _ D E B U G _ I M X 2 5 _ U A R T )
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# define U A R T _ P A D D R M X 2 5 _ U A R T 1 _ B A S E _ A D D R
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# elif d e f i n e d ( C O N F I G _ D E B U G _ I M X 2 1 _ I M X 2 7 _ U A R T )
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# define U A R T _ P A D D R M X 2 x _ U A R T 1 _ B A S E _ A D D R
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# elif d e f i n e d ( C O N F I G _ D E B U G _ I M X 3 1 _ I M X 3 5 _ U A R T )
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# define U A R T _ P A D D R M X 3 x _ U A R T 1 _ B A S E _ A D D R
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# elif d e f i n e d ( C O N F I G _ D E B U G _ I M X 5 1 _ U A R T )
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# define U A R T _ P A D D R M X 5 1 _ U A R T 1 _ B A S E _ A D D R
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# elif d e f i n e d ( C O N F I G _ D E B U G _ I M X 5 0 _ I M X 5 3 _ U A R T )
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# define U A R T _ P A D D R M X 5 3 _ U A R T 1 _ B A S E _ A D D R
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# elif d e f i n e d ( C O N F I G _ D E B U G _ I M X 6 Q _ U A R T 2 )
# define U A R T _ P A D D R M X 6 Q _ U A R T 2 _ B A S E _ A D D R
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# elif d e f i n e d ( C O N F I G _ D E B U G _ I M X 6 Q _ U A R T 4 )
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# define U A R T _ P A D D R M X 6 Q _ U A R T 4 _ B A S E _ A D D R
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# endif
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# define U A R T _ V A D D R I M X _ I O _ A D D R E S S ( U A R T _ P A D D R )
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.macro r p , r v , t m p
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ldr \ r p , =UART_PADDR @ physical
ldr \ r v , =UART_VADDR @ virtual
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.endm
.macro r d ,r x
str \ r d , [ \ r x , #0x40 ] @ TXDATA
.endm
.macro r d ,r x
.endm
.macro r d ,r x
1002 : ldr \ r d , [ \ r x , #0x98 ] @ SR2
tst \ r d , #1 < < 3 @ TXDC
beq 1 0 0 2 b @ wait until transmit done
.endm
