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linux/drivers/pmdomain/mediatek/mt8195-pm-domains.h

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soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
*/
#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
#include "mtk-pm-domains.h"
#include <dt-bindings/power/mt8195-power.h>
/*
* MT8195 power domain support
*/
static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
[MT8195_POWER_DOMAIN_PCIE_MAC_P0] = {
.name = "pcie_mac_p0",
.sta_mask = BIT(11),
.ctl_offs = 0x328,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_MAC_P1] = {
.name = "pcie_mac_p1",
.sta_mask = BIT(12),
.ctl_offs = 0x32C,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
},
[MT8195_POWER_DOMAIN_PCIE_PHY] = {
.name = "pcie_phy",
.sta_mask = BIT(13),
.ctl_offs = 0x330,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = {
.name = "ssusb_pcie_phy",
.sta_mask = BIT(14),
.ctl_offs = 0x334,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
soc: mediatek: pm-domains: Add support always on flag There is a t-phy shared by PCIe and USB3 on mt8195, if the t-phy is used by PCIe, when power off its mtcmos, need software reset it (workaround way, usually hardware do it, but has an issue on mt8195), but it has side effect to USB2 phy(works with USB3 phy to support USB3.2 Gen1), so add support GENPD_FLAG_ALWAYS_ON flag, and make its power always on. Another reason is that USB3.2 Gen1/2 need keep power always on when support runtime-pm due to hardware limitation until now. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220617095841.23031-1-chunfeng.yun@mediatek.com [mb: smaller nit fixes on commit message] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-17 17:58:41 +08:00
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_ALWAYS_ON,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
},
[MT8195_POWER_DOMAIN_CSI_RX_TOP] = {
.name = "csi_rx_top",
.sta_mask = BIT(18),
.ctl_offs = 0x3C4,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_ETHER] = {
.name = "ether",
.sta_mask = BIT(3),
.ctl_offs = 0x344,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_ADSP] = {
.name = "adsp",
.sta_mask = BIT(10),
.ctl_offs = 0x360,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_2_ADSP,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
},
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_AUDIO] = {
.name = "audio",
.sta_mask = BIT(8),
.ctl_offs = 0x358,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_2_AUDIO,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
},
},
[MT8195_POWER_DOMAIN_MFG0] = {
.name = "mfg0",
.sta_mask = BIT(1),
.ctl_offs = 0x300,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8195_POWER_DOMAIN_MFG1] = {
.name = "mfg1",
.sta_mask = BIT(2),
.ctl_offs = 0x304,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MFG1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_2_MFG1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_1_MFG1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_1_SET,
MT8195_TOP_AXI_PROT_EN_1_CLR,
MT8195_TOP_AXI_PROT_EN_1_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
soc: mediatek: mtk-pm-domains: Allow probing vreg supply on two MFGs MediaTek SoCs have multiple MFG power-domains, exclusively used for the GPU which, in turn, requires external power supplies: make sure to have the MTK_SCPD_DOMAIN_SUPPLY cap on the two topmost MFGs to allow voting for regulators on/off upon usage of these power domains. This also ensures that the SRAM is actually powered and that we're not relying on the bootloader leaving this supply on when performing the first (and latter) poweron sequence for these domains' sram. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220623123850.110225-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-06-23 14:38:49 +02:00
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
},
[MT8195_POWER_DOMAIN_MFG2] = {
.name = "mfg2",
.sta_mask = BIT(3),
.ctl_offs = 0x308,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG3] = {
.name = "mfg3",
.sta_mask = BIT(4),
.ctl_offs = 0x30C,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG4] = {
.name = "mfg4",
.sta_mask = BIT(5),
.ctl_offs = 0x310,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG5] = {
.name = "mfg5",
.sta_mask = BIT(6),
.ctl_offs = 0x314,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_MFG6] = {
.name = "mfg6",
.sta_mask = BIT(7),
.ctl_offs = 0x318,
.pwr_sta_offs = 0x174,
.pwr_sta2nd_offs = 0x178,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VPPSYS0] = {
.name = "vppsys0",
.sta_mask = BIT(11),
.ctl_offs = 0x364,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VPPSYS0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS0] = {
.name = "vdosys0",
.sta_mask = BIT(13),
.ctl_offs = 0x36C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VDOSYS0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SET,
MT8195_TOP_AXI_PROT_EN_CLR,
MT8195_TOP_AXI_PROT_EN_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
},
},
[MT8195_POWER_DOMAIN_VPPSYS1] = {
.name = "vppsys1",
.sta_mask = BIT(12),
.ctl_offs = 0x368,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDOSYS1] = {
.name = "vdosys1",
.sta_mask = BIT(14),
.ctl_offs = 0x370,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_DP_TX] = {
.name = "dp_tx",
.sta_mask = BIT(16),
.ctl_offs = 0x378,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_EPD_TX] = {
.name = "epd_tx",
.sta_mask = BIT(17),
.ctl_offs = 0x37C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_HDMI_TX] = {
.name = "hdmi_tx",
.sta_mask = BIT(18),
.ctl_offs = 0x380,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
},
[MT8195_POWER_DOMAIN_WPESYS] = {
.name = "wpesys",
.sta_mask = BIT(15),
.ctl_offs = 0x374,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
},
[MT8195_POWER_DOMAIN_VDEC0] = {
.name = "vdec0",
.sta_mask = BIT(20),
.ctl_offs = 0x388,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VDEC1] = {
.name = "vdec1",
.sta_mask = BIT(21),
.ctl_offs = 0x38C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VDEC2] = {
.name = "vdec2",
.sta_mask = BIT(22),
.ctl_offs = 0x390,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VENC] = {
.name = "venc",
.sta_mask = BIT(23),
.ctl_offs = 0x394,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VENC,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_VENC_CORE1] = {
.name = "venc_core1",
.sta_mask = BIT(24),
.ctl_offs = 0x398,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_IMG] = {
.name = "img",
.sta_mask = BIT(29),
.ctl_offs = 0x3AC,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_IMG,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_DIP] = {
.name = "dip",
.sta_mask = BIT(30),
.ctl_offs = 0x3B0,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_IPE] = {
.name = "ipe",
.sta_mask = BIT(31),
.ctl_offs = 0x3B4,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_IPE,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM] = {
.name = "cam",
.sta_mask = BIT(25),
.ctl_offs = 0x39C,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_2_CAM,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_2_SET,
MT8195_TOP_AXI_PROT_EN_2_CLR,
MT8195_TOP_AXI_PROT_EN_2_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_CAM,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_1_CAM,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_1_SET,
MT8195_TOP_AXI_PROT_EN_1_CLR,
MT8195_TOP_AXI_PROT_EN_1_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_SET,
MT8195_TOP_AXI_PROT_EN_MM_CLR,
MT8195_TOP_AXI_PROT_EN_MM_STA1),
pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2023-09-18 11:37:49 +02:00
BUS_PROT_WR(INFRA,
MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
soc: mediatek: pm-domains: Add support for mt8195 Add domain control data including bus protection data size change due to more protection steps in mt8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220130012104.5292-6-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-01-30 09:21:04 +08:00
MT8195_TOP_AXI_PROT_EN_MM_2_SET,
MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
},
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM_RAWA] = {
.name = "cam_rawa",
.sta_mask = BIT(26),
.ctl_offs = 0x3A0,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM_RAWB] = {
.name = "cam_rawb",
.sta_mask = BIT(27),
.ctl_offs = 0x3A4,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8195_POWER_DOMAIN_CAM_MRAW] = {
.name = "cam_mraw",
.sta_mask = BIT(28),
.ctl_offs = 0x3A8,
.pwr_sta_offs = 0x16c,
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
};
static const struct scpsys_soc_data mt8195_scpsys_data = {
.domains_data = scpsys_domain_data_mt8195,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195),
};
#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */
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