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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
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$id : http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
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$schema : http://devicetree.org/meta-schemas/core.yaml#
title : Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
maintainers :
- Iskren Chernev <iskren.chernev@gmail.com>
description :
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Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
SoCs.
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properties :
compatible :
const : qcom,sm6115-tlmm
reg :
maxItems : 3
reg-names :
items :
- const : west
- const : south
- const : east
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interrupts :
maxItems : 1
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interrupt-controller : true
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"#interrupt-cells": true
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gpio-controller : true
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"#gpio-cells": true
gpio-ranges : true
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gpio-reserved-ranges : true
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wakeup-parent : true
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patternProperties :
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"-state$" :
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oneOf :
- $ref : "#/$defs/qcom-sm6115-tlmm-state"
- patternProperties :
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"-pins$" :
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$ref : "#/$defs/qcom-sm6115-tlmm-state"
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additionalProperties : false
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$defs :
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qcom-sm6115-tlmm-state :
type : object
description :
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
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$ref : qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties : false
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properties :
pins :
description :
List of gpio pins affected by the properties specified in this
subnode.
items :
oneOf :
- pattern : "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
- enum : [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
minItems : 1
maxItems : 36
function :
description :
Specify the alternative function to be configured for the specified
pins.
enum : [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
wlan1_adc0, elan1_adc1 ]
required :
- pins
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allOf :
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- $ref : /schemas/pinctrl/qcom,tlmm-common.yaml#
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required :
- compatible
- reg
- reg-names
additionalProperties : false
examples :
- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm : pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x500000 0x400000>,
<0x900000 0x400000>,
<0xd00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 114>;
sdc2_on_state : sdc2-on-state {
clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd-pins {
pins = "gpio88";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
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};
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};