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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright ( c ) 2012 - 2020 , Intel Corporation . All rights reserved .
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* Intel Management Engine Interface ( Intel MEI ) Linux driver
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*/
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# ifndef _MEI_INTERFACE_H_
# define _MEI_INTERFACE_H_
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# include <linux/irqreturn.h>
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# include <linux/pci.h>
# include <linux/mei.h>
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# include "mei_dev.h"
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# include "client.h"
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/*
* mei_cfg - mei device configuration
*
* @ fw_status : FW status
* @ quirk_probe : device exclusion quirk
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* @ kind : MEI head kind
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* @ dma_size : device DMA buffers size
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* @ fw_ver_supported : is fw version retrievable from FW
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* @ hw_trc_supported : does the hw support trc register
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*/
struct mei_cfg {
const struct mei_fw_status fw_status ;
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bool ( * quirk_probe ) ( const struct pci_dev * pdev ) ;
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const char * kind ;
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size_t dma_size [ DMA_DSCR_NUM ] ;
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u32 fw_ver_supported : 1 ;
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u32 hw_trc_supported : 1 ;
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} ;
# define MEI_PCI_DEVICE(dev, cfg) \
. vendor = PCI_VENDOR_ID_INTEL , . device = ( dev ) , \
. subvendor = PCI_ANY_ID , . subdevice = PCI_ANY_ID , \
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. driver_data = ( kernel_ulong_t ) ( cfg ) ,
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# define MEI_ME_RPM_TIMEOUT 500 /* ms */
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/**
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* struct mei_me_hw - me hw specific data
*
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* @ cfg : per device generation config and ops
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* @ mem_addr : io memory address
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* @ irq : irq number
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* @ pg_state : power gating state
* @ d0i3_supported : di03 support
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* @ hbuf_depth : depth of hardware host / write buffer in slots
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* @ read_fws : read FW status register handler
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*/
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struct mei_me_hw {
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const struct mei_cfg * cfg ;
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void __iomem * mem_addr ;
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int irq ;
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enum mei_pg_state pg_state ;
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bool d0i3_supported ;
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u8 hbuf_depth ;
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int ( * read_fws ) ( const struct mei_device * dev , int where , u32 * val ) ;
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} ;
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# define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
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/**
* enum mei_cfg_idx - indices to platform specific configurations .
*
* Note : has to be synchronized with mei_cfg_list [ ]
*
* @ MEI_ME_UNDEF_CFG : Lower sentinel .
* @ MEI_ME_ICH_CFG : I / O Controller Hub legacy devices .
* @ MEI_ME_ICH10_CFG : I / O Controller Hub platforms Gen10
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* @ MEI_ME_PCH6_CFG : Platform Controller Hub platforms ( Gen6 ) .
* @ MEI_ME_PCH7_CFG : Platform Controller Hub platforms ( Gen7 ) .
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* @ MEI_ME_PCH_CPT_PBG_CFG : Platform Controller Hub workstations
* with quirk for Node Manager exclusion .
* @ MEI_ME_PCH8_CFG : Platform Controller Hub Gen8 and newer
* client platforms .
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* @ MEI_ME_PCH8_ITOUCH_CFG : Platform Controller Hub Gen8 and newer
* client platforms ( iTouch ) .
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* @ MEI_ME_PCH8_SPS_4_CFG : Platform Controller Hub Gen8 and newer
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* servers platforms with quirk for
* SPS firmware exclusion .
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* @ MEI_ME_PCH12_CFG : Platform Controller Hub Gen12 and newer
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* @ MEI_ME_PCH12_SPS_4_CFG : Platform Controller Hub Gen12 up to 4.0
* servers platforms with quirk for
* SPS firmware exclusion .
* @ MEI_ME_PCH12_SPS_CFG : Platform Controller Hub Gen12 5.0 and newer
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* servers platforms with quirk for
* SPS firmware exclusion .
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* @ MEI_ME_PCH15_CFG : Platform Controller Hub Gen15 and newer
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* @ MEI_ME_PCH15_SPS_CFG : Platform Controller Hub Gen15 and newer
* servers platforms with quirk for
* SPS firmware exclusion .
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* @ MEI_ME_NUM_CFG : Upper Sentinel .
*/
enum mei_cfg_idx {
MEI_ME_UNDEF_CFG ,
MEI_ME_ICH_CFG ,
MEI_ME_ICH10_CFG ,
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MEI_ME_PCH6_CFG ,
MEI_ME_PCH7_CFG ,
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MEI_ME_PCH_CPT_PBG_CFG ,
MEI_ME_PCH8_CFG ,
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MEI_ME_PCH8_ITOUCH_CFG ,
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MEI_ME_PCH8_SPS_4_CFG ,
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MEI_ME_PCH12_CFG ,
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MEI_ME_PCH12_SPS_4_CFG ,
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MEI_ME_PCH12_SPS_CFG ,
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MEI_ME_PCH12_SPS_ITOUCH_CFG ,
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MEI_ME_PCH15_CFG ,
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MEI_ME_PCH15_SPS_CFG ,
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MEI_ME_NUM_CFG ,
} ;
const struct mei_cfg * mei_me_get_cfg ( kernel_ulong_t idx ) ;
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struct mei_device * mei_me_dev_init ( struct device * parent ,
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const struct mei_cfg * cfg ) ;
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int mei_me_pg_enter_sync ( struct mei_device * dev ) ;
int mei_me_pg_exit_sync ( struct mei_device * dev ) ;
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irqreturn_t mei_me_irq_quick_handler ( int irq , void * dev_id ) ;
irqreturn_t mei_me_irq_thread_handler ( int irq , void * dev_id ) ;
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# endif /* _MEI_INTERFACE_H_ */