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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/ *
* arch/ a r m / m a c h - t e g r a / s l e e p . S
*
* Copyright ( c ) 2 0 1 0 - 2 0 1 1 , N V I D I A C o r p o r a t i o n .
* Copyright ( c ) 2 0 1 1 , G o o g l e , I n c .
*
* Author : Colin C r o s s < c c r o s s @android.com>
* Gary K i n g < g k i n g @nvidia.com>
* /
# include < l i n u x / l i n k a g e . h >
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# include < a s m / a s s e m b l e r . h >
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# include < a s m / c a c h e . h >
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# include < a s m / c p15 . h >
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# include < a s m / h a r d w a r e / c a c h e - l 2 x0 . h >
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# include " i o m a p . h "
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# include " s l e e p . h "
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# define C L K _ R E S E T _ C C L K _ B U R S T 0 x20
# define C L K _ R E S E T _ C C L K _ D I V I D E R 0 x24
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# if d e f i n e d ( C O N F I G _ H O T P L U G _ C P U ) | | d e f i n e d ( C O N F I G _ P M _ S L E E P )
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/ *
* tegra_ d i s a b l e _ c l e a n _ i n v _ d c a c h e
*
* disable, c l e a n & i n v a l i d a t e t h e D - c a c h e
*
* Corrupted r e g i s t e r s : r1 - r3 , r6 , r8 , r9 - r11
* /
ENTRY( t e g r a _ d i s a b l e _ c l e a n _ i n v _ d c a c h e )
stmfd s p ! , { r0 , r4 - r5 , r7 , r9 - r11 , l r }
dmb @ ensure ordering
/* Disable the D-cache */
mrc p15 , 0 , r2 , c1 , c0 , 0
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tst r2 , #C R _ C @ s e e t e g r a _ s l e e p _ c p u ( )
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bic r2 , r2 , #C R _ C
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mcrne p15 , 0 , r2 , c1 , c0 , 0
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isb
/* Flush the D-cache */
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cmp r0 , #T E G R A _ F L U S H _ C A C H E _ A L L
blne v7 _ f l u s h _ d c a c h e _ l o u i s
bleq v7 _ f l u s h _ d c a c h e _ a l l
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/* Trun off coherency */
exit_ s m p r4 , r5
ldmfd s p ! , { r0 , r4 - r5 , r7 , r9 - r11 , p c }
ENDPROC( t e g r a _ d i s a b l e _ c l e a n _ i n v _ d c a c h e )
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# endif
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# ifdef C O N F I G _ P M _ S L E E P
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/ *
* tegra_ i n i t _ l 2 _ f o r _ a15
*
* set u p t h e c o r r e c t L 2 c a c h e d a t a R A M l a t e n c y
* /
ENTRY( t e g r a _ i n i t _ l 2 _ f o r _ a15 )
mrc p15 , 0 , r0 , c0 , c0 , 5
ubfx r0 , r0 , #8 , #4
tst r0 , #1 @ only need for cluster 0
bne _ e x i t _ i n i t _ l 2 _ a15
mrc p15 , 0 x1 , r0 , c9 , c0 , 2
and r0 , r0 , #7
cmp r0 , #2
bicne r0 , r0 , #7
orrne r0 , r0 , #2
mcrne p15 , 0 x1 , r0 , c9 , c0 , 2
_exit_init_l2_a15 :
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ret l r
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ENDPROC( t e g r a _ i n i t _ l 2 _ f o r _ a15 )
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/ *
* tegra_ s l e e p _ c p u _ f i n i s h ( u n s i g n e d l o n g v2 p )
*
* enters s u s p e n d i n L P 2 b y t u r n i n g o f f t h e m m u a n d j u m p i n g t o
* tegra? _ t e a r _ d o w n _ c p u
* /
ENTRY( t e g r a _ s l e e p _ c p u _ f i n i s h )
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mov r4 , r0
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/* Flush and disable the L1 data cache */
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mov r0 , #T E G R A _ F L U S H _ C A C H E _ A L L
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bl t e g r a _ d i s a b l e _ c l e a n _ i n v _ d c a c h e
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mov r0 , r4
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mov3 2 r6 , t e g r a _ t e a r _ d o w n _ c p u
ldr r1 , [ r6 ]
add r1 , r1 , r0
mov3 2 r3 , t e g r a _ s h u t _ o f f _ m m u
add r3 , r3 , r0
mov r0 , r1
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ret r3
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ENDPROC( t e g r a _ s l e e p _ c p u _ f i n i s h )
/ *
* tegra_ s h u t _ o f f _ m m u
*
* r0 = p h y s i c a l a d d r e s s t o j u m p t o w i t h m m u o f f
*
* called w i t h V A =PA m a p p i n g
* turns o f f M M U , i c a c h e , d c a c h e a n d b r a n c h p r e d i c t i o n
* /
.align L1_CACHE_SHIFT
.pushsection .idmap .text , " ax"
ENTRY( t e g r a _ s h u t _ o f f _ m m u )
mrc p15 , 0 , r3 , c1 , c0 , 0
movw r2 , #C R _ I | C R _ Z | C R _ C | C R _ M
bic r3 , r3 , r2
dsb
mcr p15 , 0 , r3 , c1 , c0 , 0
isb
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# ifdef C O N F I G _ C A C H E _ L 2 X 0
/* Disable L2 cache */
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check_ c p u _ p a r t _ n u m 0 x c09 , r9 , r10
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retne r0
mov3 2 r2 , T E G R A _ A R M _ P E R I F _ B A S E + 0 x30 0 0
ldr r3 , [ r2 , #L 2 X 0 _ C T R L ]
tst r3 , #L 2 X 0 _ C T R L _ E N @ see tegra_sleep_cpu()
mov r3 , #0
strne r3 , [ r2 , #L 2 X 0 _ C T R L ]
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# endif
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ret r0
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ENDPROC( t e g r a _ s h u t _ o f f _ m m u )
.popsection
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/ *
* tegra_ s w i t c h _ c p u _ t o _ p l l p
*
* In L P 2 t h e n o r m a l c p u c l o c k p l l x w i l l b e t u r n e d o f f . S w i t c h t h e C P U t o p l l p
* /
ENTRY( t e g r a _ s w i t c h _ c p u _ t o _ p l l p )
/* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
mov3 2 r5 , T E G R A _ C L K _ R E S E T _ B A S E
mov r0 , #( 2 < < 2 8 ) @ burst policy = run mode
orr r0 , r0 , #( 4 < < 4 ) @ use PLLP in run mode burst
str r0 , [ r5 , #C L K _ R E S E T _ C C L K _ B U R S T ]
mov r0 , #0
str r0 , [ r5 , #C L K _ R E S E T _ C C L K _ D I V I D E R ]
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ret l r
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ENDPROC( t e g r a _ s w i t c h _ c p u _ t o _ p l l p )
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# endif
