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# ifndef _ASM_M32R_ASSEMBLER_H
# define _ASM_M32R_ASSEMBLER_H
/*
* linux / asm - m32r / assembler . h
*
* Copyright ( C ) 2004 Hirokazu Takata < takata at linux - m32r . org >
*
* This file contains M32R architecture specific macro definitions .
*/
# ifndef __STR
# ifdef __ASSEMBLY__
# define __STR(x) x
# else
# define __STR(x) #x
# endif
# endif /* __STR */
# ifdef CONFIG_SMP
# define M32R_LOCK __STR(lock)
# define M32R_UNLOCK __STR(unlock)
# else
# define M32R_LOCK __STR(ld)
# define M32R_UNLOCK __STR(st)
# endif
# ifdef __ASSEMBLY__
# undef ENTRY
# define ENTRY(name) ENTRY_M name
. macro ENTRY_M name
. global \ name
ALIGN
\ name :
. endm
# endif
/**
* LDIMM - load immediate value
* STI - enable interruption
* CLI - disable interruption
*/
# ifdef __ASSEMBLY__
# define LDIMM(reg,x) LDIMM reg x
. macro LDIMM reg x
seth \ reg , # high ( \ x )
or3 \ reg , \ reg , # low ( \ x )
. endm
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# if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
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# define STI(reg) STI_M reg
. macro STI_M reg
setpsw # 0x40 - > nop
; WORKAROUND : " -> nop " is a workaround for the M32700 ( TS1 ) .
. endm
# define CLI(reg) CLI_M reg
. macro CLI_M reg
clrpsw # 0x40 - > nop
; WORKAROUND : " -> nop " is a workaround for the M32700 ( TS1 ) .
. endm
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# else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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# define STI(reg) STI_M reg
. macro STI_M reg
mvfc \ reg , psw
or3 \ reg , \ reg , # 0x0040
mvtc \ reg , psw
. endm
# define CLI(reg) CLI_M reg
. macro CLI_M reg
mvfc \ reg , psw
and3 \ reg , \ reg , # 0xffbf
mvtc \ reg , psw
. endm
# endif /* CONFIG_CHIP_M32102 */
. macro SAVE_ALL
push r0 ; orig_r0
push sp ; spi ( r15 )
push lr ; r14
push r13
mvfc r13 , cr3 ; spu
push r13
mvfc r13 , bbpc
push r13
mvfc r13 , bbpsw
push r13
mvfc r13 , bpc
push r13
mvfc r13 , psw
push r13
# if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
mvfaclo r13 , a1
push r13
mvfachi r13 , a1
push r13
mvfaclo r13 , a0
push r13
mvfachi r13 , a0
push r13
# elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
mvfaclo r13
push r13
mvfachi r13
push r13
[PATCH] m32r: Fix pt_regs for !COFNIG_ISA_DSP_LEVEL2 target
This modification is required to fix debugging function for m32r targets
with !CONFIG_ISA_DSP_LEVEL2, by unifying 'struct pt_regs' and 'struct
sigcontext' size for all M32R ISA.
Some m32r processor core with !CONFIG_ISA_DSP_LEVEL2 configuration has only
single accumulator a0 (ex. VDEC2 core, M32102 core, etc.), the others with
CONFIG_ISA_DSP_LEVEL2 has two accumulators, a0 and a1.
This means there are two variations of thread context. So far, we reduced
and changed stackframe size at a syscall for their context size. However,
this causes a problem that a GDB for processors with CONFIG_ISA_DSP_LEVEL2
cannot be used for processors with !CONFIG_ISA_DSP_LEVEL2.
From the viewpoint of GDB support, we should reduce such variation of
stackframe size for simplicity.
In this patch, dummy members are added to 'struct pt_regs' and 'struct
sigcontext' to adjust their size for !CONFIG_ISA_DSP_LEVEL2.
This modification is also a one step for a GDB update in future.
Currently, on the m32r, GDB can access process's context by using ptrace
functions in a simple way of register by register access. By unifying
stackframe size, we have a possibility to make use of ptrace functions of
not only a single register access but also block register access,
PTRACE_{GETREGS,PUTREGS}.
However, for this purpose, we might have to modify stackframe structure
some more; for example, PSW (processor status word) register should be
pre-processed before pushing to stack at a syscall, and so on. In this
case, we must update carefully both kernel and GDB at a time...
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Cc: Kei Sakamoto <ksakamot@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-19 09:21:20 +04:00
ldi r13 , # 0
push r13 ; dummy push acc1h
push r13 ; dummy push acc1l
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# else
# error unknown isa configuration
# endif
ldi r13 , # - 1
push r13 ; syscall_nr ( default : - 1 )
push r12
push r11
push r10
push r9
push r8
push r7
push r3
push r2
push r1
push r0
addi sp , # - 4 ; room for implicit pt_regs parameter
push r6
push r5
push r4
. endm
. macro RESTORE_ALL
pop r4
pop r5
pop r6
addi sp , # 4
pop r0
pop r1
pop r2
pop r3
pop r7
pop r8
pop r9
pop r10
pop r11
pop r12
addi r15 , # 4 ; Skip syscall number
# if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
pop r13
mvtachi r13 , a0
pop r13
mvtaclo r13 , a0
pop r13
mvtachi r13 , a1
pop r13
mvtaclo r13 , a1
# elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
[PATCH] m32r: Fix pt_regs for !COFNIG_ISA_DSP_LEVEL2 target
This modification is required to fix debugging function for m32r targets
with !CONFIG_ISA_DSP_LEVEL2, by unifying 'struct pt_regs' and 'struct
sigcontext' size for all M32R ISA.
Some m32r processor core with !CONFIG_ISA_DSP_LEVEL2 configuration has only
single accumulator a0 (ex. VDEC2 core, M32102 core, etc.), the others with
CONFIG_ISA_DSP_LEVEL2 has two accumulators, a0 and a1.
This means there are two variations of thread context. So far, we reduced
and changed stackframe size at a syscall for their context size. However,
this causes a problem that a GDB for processors with CONFIG_ISA_DSP_LEVEL2
cannot be used for processors with !CONFIG_ISA_DSP_LEVEL2.
From the viewpoint of GDB support, we should reduce such variation of
stackframe size for simplicity.
In this patch, dummy members are added to 'struct pt_regs' and 'struct
sigcontext' to adjust their size for !CONFIG_ISA_DSP_LEVEL2.
This modification is also a one step for a GDB update in future.
Currently, on the m32r, GDB can access process's context by using ptrace
functions in a simple way of register by register access. By unifying
stackframe size, we have a possibility to make use of ptrace functions of
not only a single register access but also block register access,
PTRACE_{GETREGS,PUTREGS}.
However, for this purpose, we might have to modify stackframe structure
some more; for example, PSW (processor status word) register should be
pre-processed before pushing to stack at a syscall, and so on. In this
case, we must update carefully both kernel and GDB at a time...
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Cc: Kei Sakamoto <ksakamot@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-19 09:21:20 +04:00
pop r13 ; dummy pop acc1h
pop r13 ; dummy pop acc1l
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pop r13
mvtachi r13
pop r13
mvtaclo r13
# else
# error unknown isa configuration
# endif
pop r14
mvtc r14 , psw
pop r14
mvtc r14 , bpc
addi sp , # 8 ; Skip bbpsw , bbpc
pop r14
mvtc r14 , cr3 ; spu
pop r13
pop lr ; r14
pop sp ; spi ( r15 )
addi sp , # 4 ; Skip orig_r0
. fillinsn
1 : rte
. section . fixup , " ax "
2 : bl do_exit
. previous
. section __ex_table , " a "
ALIGN
. long 1 b , 2 b
. previous
. endm
# define GET_CURRENT(reg) get_current reg
. macro get_current reg
ldi \ reg , # - 8192
and \ reg , sp
. endm
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# if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
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. macro SWITCH_TO_KERNEL_STACK
; switch to kernel stack ( spi )
clrpsw # 0x80 - > nop
. endm
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# else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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. macro SWITCH_TO_KERNEL_STACK
push r0 ; save r0 for working
mvfc r0 , psw
and3 r0 , r0 , # 0x00ff7f
mvtc r0 , psw
slli r0 , # 16
bltz r0 , 1f ; check BSM - bit
;
; ; called from kernel context : previous stack = spi
pop r0 ; retrieve r0
bra 2f
. fillinsn
1 :
; ; called from user context : previous stack = spu
mvfc r0 , cr3 ; spu
addi r0 , # 4
mvtc r0 , cr3 ; spu
ld r0 , @ ( - 4 , r0 ) ; retrieve r0
. fillinsn
2 :
. endm
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# endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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# endif /* __ASSEMBLY__ */
# endif /* _ASM_M32R_ASSEMBLER_H */