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/*
* Copyright ( C ) 2005 Stephen Street / StreetFire Sound Labs
* Copyright ( C ) 2013 , Intel Corporation
*
* This program is free software ; you can redistribute it and / or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation .
*/
# ifndef SPI_PXA2XX_H
# define SPI_PXA2XX_H
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# include <linux/atomic.h>
# include <linux/dmaengine.h>
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# include <linux/errno.h>
# include <linux/io.h>
# include <linux/interrupt.h>
# include <linux/platform_device.h>
# include <linux/pxa2xx_ssp.h>
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# include <linux/scatterlist.h>
# include <linux/sizes.h>
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# include <linux/spi/spi.h>
# include <linux/spi/pxa2xx_spi.h>
struct driver_data {
/* Driver model hookup */
struct platform_device * pdev ;
/* SSP Info */
struct ssp_device * ssp ;
/* SPI framework hookup */
enum pxa_ssp_type ssp_type ;
struct spi_master * master ;
/* PXA hookup */
struct pxa2xx_spi_master * master_info ;
/* SSP register addresses */
void __iomem * ioaddr ;
u32 ssdr_physical ;
/* SSP masks*/
u32 dma_cr1 ;
u32 int_cr1 ;
u32 clear_sr ;
u32 mask_sr ;
/* Message Transfer pump */
struct tasklet_struct pump_transfers ;
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/* DMA engine support */
atomic_t dma_running ;
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/* Current message transfer state info */
struct spi_message * cur_msg ;
struct spi_transfer * cur_transfer ;
struct chip_data * cur_chip ;
size_t len ;
void * tx ;
void * tx_end ;
void * rx ;
void * rx_end ;
u8 n_bytes ;
int ( * write ) ( struct driver_data * drv_data ) ;
int ( * read ) ( struct driver_data * drv_data ) ;
irqreturn_t ( * transfer_handler ) ( struct driver_data * drv_data ) ;
void ( * cs_control ) ( u32 command ) ;
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void __iomem * lpss_base ;
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} ;
struct chip_data {
u32 cr1 ;
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u32 dds_rate ;
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u32 timeout ;
u8 n_bytes ;
u32 dma_burst_size ;
u32 threshold ;
u32 dma_threshold ;
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u16 lpss_rx_threshold ;
u16 lpss_tx_threshold ;
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u8 enable_dma ;
union {
int gpio_cs ;
unsigned int frm ;
} ;
int gpio_cs_inverted ;
int ( * write ) ( struct driver_data * drv_data ) ;
int ( * read ) ( struct driver_data * drv_data ) ;
void ( * cs_control ) ( u32 command ) ;
} ;
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static inline u32 pxa2xx_spi_read ( const struct driver_data * drv_data ,
unsigned reg )
{
return __raw_readl ( drv_data - > ioaddr + reg ) ;
}
static inline void pxa2xx_spi_write ( const struct driver_data * drv_data ,
unsigned reg , u32 val )
{
__raw_writel ( val , drv_data - > ioaddr + reg ) ;
}
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# define START_STATE ((void *)0)
# define RUNNING_STATE ((void *)1)
# define DONE_STATE ((void *)2)
# define ERROR_STATE ((void *)-1)
# define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
# define DMA_ALIGNMENT 8
static inline int pxa25x_ssp_comp ( struct driver_data * drv_data )
{
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switch ( drv_data - > ssp_type ) {
case PXA25x_SSP :
case CE4100_SSP :
case QUARK_X1000_SSP :
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return 1 ;
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default :
return 0 ;
}
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}
static inline void write_SSSR_CS ( struct driver_data * drv_data , u32 val )
{
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if ( drv_data - > ssp_type = = CE4100_SSP | |
drv_data - > ssp_type = = QUARK_X1000_SSP )
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val | = pxa2xx_spi_read ( drv_data , SSSR ) & SSSR_ALT_FRM_MASK ;
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pxa2xx_spi_write ( drv_data , SSSR , val ) ;
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}
extern int pxa2xx_spi_flush ( struct driver_data * drv_data ) ;
extern void * pxa2xx_spi_next_transfer ( struct driver_data * drv_data ) ;
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# define MAX_DMA_LEN SZ_64K
# define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
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extern irqreturn_t pxa2xx_spi_dma_transfer ( struct driver_data * drv_data ) ;
extern int pxa2xx_spi_dma_prepare ( struct driver_data * drv_data , u32 dma_burst ) ;
extern void pxa2xx_spi_dma_start ( struct driver_data * drv_data ) ;
extern int pxa2xx_spi_dma_setup ( struct driver_data * drv_data ) ;
extern void pxa2xx_spi_dma_release ( struct driver_data * drv_data ) ;
extern int pxa2xx_spi_set_dma_burst_and_threshold ( struct chip_data * chip ,
struct spi_device * spi ,
u8 bits_per_word ,
u32 * burst_code ,
u32 * threshold ) ;
# endif /* SPI_PXA2XX_H */