2005-06-25 14:58:02 -07:00
/ *
* relocate_ k e r n e l . S - p u t t h e k e r n e l i m a g e i n p l a c e t o b o o t
* Copyright ( C ) 2 0 0 2 - 2 0 0 5 E r i c B i e d e r m a n < e b i e d e r m @xmission.com>
*
* This s o u r c e c o d e i s l i c e n s e d u n d e r t h e G N U G e n e r a l P u b l i c L i c e n s e ,
* Version 2 . S e e t h e f i l e C O P Y I N G f o r m o r e d e t a i l s .
* /
# include < l i n u x / l i n k a g e . h >
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# include < a s m / p a g e _ t y p e s . h >
2006-09-26 10:52:38 +02:00
# include < a s m / k e x e c . h >
2008-03-23 00:00:08 +03:00
# include < a s m / p r o c e s s o r - f l a g s . h >
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# include < a s m / p g t a b l e _ t y p e s . h >
2005-06-25 14:58:02 -07:00
2006-09-26 10:52:38 +02:00
/ *
* Must b e r e l o c a t a b l e P I C c o d e c a l l a b l e a s a C f u n c t i o n
* /
# define P T R ( x ) ( x < < 3 )
2008-03-23 00:00:09 +03:00
# define P A G E _ A T T R ( _ P A G E _ P R E S E N T | _ P A G E _ R W | _ P A G E _ A C C E S S E D | _ P A G E _ D I R T Y )
2006-09-26 10:52:38 +02:00
2009-03-10 10:57:16 +08:00
/ *
* control_ p a g e + K E X E C _ C O N T R O L _ C O D E _ M A X _ S I Z E
* ~ control_ p a g e + P A G E _ S I Z E a r e u s e d a s d a t a s t o r a g e a n d s t a c k f o r
* jumping b a c k
* /
# define D A T A ( o f f s e t ) ( K E X E C _ C O N T R O L _ C O D E _ M A X _ S I Z E + ( o f f s e t ) )
/* Minimal CPU state */
# define R S P D A T A ( 0 x0 )
# define C R 0 D A T A ( 0 x8 )
# define C R 3 D A T A ( 0 x10 )
# define C R 4 D A T A ( 0 x18 )
/* other data */
# define C P _ P A _ T A B L E _ P A G E D A T A ( 0 x20 )
# define C P _ P A _ S W A P _ P A G E D A T A ( 0 x28 )
# define C P _ P A _ B A C K U P _ P A G E S _ M A P D A T A ( 0 x30 )
2006-09-26 10:52:38 +02:00
.text
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.align PAGE_SIZE
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.code64
2006-09-26 10:52:38 +02:00
.globl relocate_kernel
relocate_kernel :
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/ *
* % rdi i n d i r e c t i o n _ p a g e
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* % rsi p a g e _ l i s t
* % rdx s t a r t a d d r e s s
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* % rcx p r e s e r v e _ c o n t e x t
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* /
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/* Save the CPU context, used for jumping back */
pushq % r b x
pushq % r b p
pushq % r12
pushq % r13
pushq % r14
pushq % r15
pushf
movq P T R ( V A _ C O N T R O L _ P A G E ) ( % r s i ) , % r11
movq % r s p , R S P ( % r11 )
movq % c r0 , % r a x
movq % r a x , C R 0 ( % r11 )
movq % c r3 , % r a x
movq % r a x , C R 3 ( % r11 )
movq % c r4 , % r a x
movq % r a x , C R 4 ( % r11 )
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/* zero out flags, and disable interrupts */
pushq $ 0
popfq
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/ *
* get p h y s i c a l a d d r e s s o f c o n t r o l p a g e n o w
* this i s i m p o s s i b l e a f t e r p a g e t a b l e s w i t c h
* /
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movq P T R ( P A _ C O N T R O L _ P A G E ) ( % r s i ) , % r8
/* get physical address of page table now too */
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movq P T R ( P A _ T A B L E _ P A G E ) ( % r s i ) , % r9
/* get physical address of swap page now */
movq P T R ( P A _ S W A P _ P A G E ) ( % r s i ) , % r10
/* save some information for jumping back */
movq % r9 , C P _ P A _ T A B L E _ P A G E ( % r11 )
movq % r10 , C P _ P A _ S W A P _ P A G E ( % r11 )
movq % r d i , C P _ P A _ B A C K U P _ P A G E S _ M A P ( % r11 )
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/* Switch to the identity mapped page tables */
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movq % r9 , % c r3
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/* setup a new stack at the end of the physical control page */
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lea P A G E _ S I Z E ( % r8 ) , % r s p
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/* jump to identity mapped page */
addq $ ( i d e n t i t y _ m a p p e d - r e l o c a t e _ k e r n e l ) , % r8
pushq % r8
ret
identity_mapped :
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/* set return address to 0 if not preserving context */
pushq $ 0
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/* store the start address on the stack */
pushq % r d x
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2009-03-10 10:56:57 +08:00
/ *
* Set c r0 t o a k n o w n s t a t e :
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* - Paging e n a b l e d
* - Alignment c h e c k d i s a b l e d
* - Write p r o t e c t d i s a b l e d
* - No t a s k s w i t c h
* - Don' t d o F P s o f t w a r e e m u l a t i o n .
* - Proctected m o d e e n a b l e d
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* /
movq % c r0 , % r a x
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andq $ ~ ( X 8 6 _ C R 0 _ A M | X 8 6 _ C R 0 _ W P | X 8 6 _ C R 0 _ T S | X 8 6 _ C R 0 _ E M ) , % r a x
orl $ ( X 8 6 _ C R 0 _ P G | X 8 6 _ C R 0 _ P E ) , % e a x
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movq % r a x , % c r0
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/ *
* Set c r4 t o a k n o w n s t a t e :
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* - physical a d d r e s s e x t e n s i o n e n a b l e d
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* /
2015-03-31 19:00:10 +02:00
movl $ X 8 6 _ C R 4 _ P A E , % e a x
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movq % r a x , % c r4
jmp 1 f
1 :
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/* Flush the TLB (needed?) */
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movq % r9 , % c r3
movq % r c x , % r11
call s w a p _ p a g e s
/ *
* To b e c e r t a i n o f a v o i d i n g p r o b l e m s w i t h s e l f - m o d i f y i n g c o d e
* I n e e d t o e x e c u t e a s e r i a l i z i n g i n s t r u c t i o n h e r e .
* So I f l u s h t h e T L B b y r e l o a d i n g % c r3 h e r e , i t ' s h a n d y ,
* and n o t p r o c e s s o r d e p e n d e n t .
* /
movq % c r3 , % r a x
movq % r a x , % c r3
/ *
* set a l l o f t h e r e g i s t e r s t o k n o w n v a l u e s
* leave % r s p a l o n e
* /
testq % r11 , % r11
jnz 1 f
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xorl % e a x , % e a x
xorl % e b x , % e b x
xorl % e c x , % e c x
xorl % e d x , % e d x
xorl % e s i , % e s i
xorl % e d i , % e d i
xorl % e b p , % e b p
xorl % r8 d , % r8 d
xorl % r9 d , % r9 d
xorl % r10 d , % r10 d
xorl % r11 d , % r11 d
xorl % r12 d , % r12 d
xorl % r13 d , % r13 d
xorl % r14 d , % r14 d
xorl % r15 d , % r15 d
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ret
1 :
popq % r d x
leaq P A G E _ S I Z E ( % r10 ) , % r s p
call * % r d x
/* get the re-entry point of the peer system */
movq 0 ( % r s p ) , % r b p
call 1 f
1 :
popq % r8
subq $ ( 1 b - r e l o c a t e _ k e r n e l ) , % r8
movq C P _ P A _ S W A P _ P A G E ( % r8 ) , % r10
movq C P _ P A _ B A C K U P _ P A G E S _ M A P ( % r8 ) , % r d i
movq C P _ P A _ T A B L E _ P A G E ( % r8 ) , % r a x
movq % r a x , % c r3
lea P A G E _ S I Z E ( % r8 ) , % r s p
call s w a p _ p a g e s
movq $ v i r t u a l _ m a p p e d , % r a x
pushq % r a x
ret
virtual_mapped :
movq R S P ( % r8 ) , % r s p
movq C R 4 ( % r8 ) , % r a x
movq % r a x , % c r4
movq C R 3 ( % r8 ) , % r a x
movq C R 0 ( % r8 ) , % r8
movq % r a x , % c r3
movq % r8 , % c r0
movq % r b p , % r a x
popf
popq % r15
popq % r14
popq % r13
popq % r12
popq % r b p
popq % r b x
ret
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/* Do the copies */
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swap_pages :
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movq % r d i , % r c x / * P u t t h e p a g e _ l i s t i n % r c x * /
2013-06-20 21:16:00 -07:00
xorl % e d i , % e d i
xorl % e s i , % e s i
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jmp 1 f
0 : /* top, read another word for the indirection page */
movq ( % r b x ) , % r c x
addq $ 8 , % r b x
1 :
x86/asm: Optimize unnecessarily wide TEST instructions
By the nature of the TEST operation, it is often possible to test
a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
This results in shorter instructions, because the TEST instruction
has no sign-entending byte-immediate forms unlike other ALU ops.
Note that this change does not create any LCP (Length-Changing Prefix)
stalls, which happen when adding a 0x66 prefix, which happens when
16-bit immediates are used, which changes such TEST instructions:
[test_opcode] [modrm] [imm32]
to:
[0x66] [test_opcode] [modrm] [imm16]
where [imm16] has a *different length* now: 2 bytes instead of 4.
This confuses the decoder and slows down execution.
REX prefixes were carefully designed to almost never hit this case:
adding REX prefix does not change instruction length except MOVABS
and MOV [addr],RAX instruction.
This patch does not add instructions which would use a 0x66 prefix,
code changes in assembly are:
-48 f7 07 01 00 00 00 testq $0x1,(%rdi)
+f6 07 01 testb $0x1,(%rdi)
-48 f7 c1 01 00 00 00 test $0x1,%rcx
+f6 c1 01 test $0x1,%cl
-48 f7 c1 02 00 00 00 test $0x2,%rcx
+f6 c1 02 test $0x2,%cl
-41 f7 c2 01 00 00 00 test $0x1,%r10d
+41 f6 c2 01 test $0x1,%r10b
-48 f7 c1 04 00 00 00 test $0x4,%rcx
+f6 c1 04 test $0x4,%cl
-48 f7 c1 08 00 00 00 test $0x8,%rcx
+f6 c1 08 test $0x8,%cl
Linus further notes:
"There are no stalls from using 8-bit instruction forms.
Now, changing from 64-bit or 32-bit 'test' instructions to 8-bit ones
*could* cause problems if it ends up having forwarding issues, so that
instead of just forwarding the result, you end up having to wait for
it to be stable in the L1 cache (or possibly the register file). The
forwarding from the store buffer is simplest and most reliable if the
read is done at the exact same address and the exact same size as the
write that gets forwarded.
But that's true only if:
(a) the write was very recent and is still in the write queue. I'm
not sure that's the case here anyway.
(b) on at least most Intel microarchitectures, you have to test a
different byte than the lowest one (so forwarding a 64-bit write
to a 8-bit read ends up working fine, as long as the 8-bit read
is of the low 8 bits of the written data).
A very similar issue *might* show up for registers too, not just
memory writes, if you use 'testb' with a high-byte register (where
instead of forwarding the value from the original producer it needs to
go through the register file and then shifted). But it's mainly a
problem for store buffers.
But afaik, the way Denys changed the test instructions, neither of the
above issues should be true.
The real problem for store buffer forwarding tends to be "write 8
bits, read 32 bits". That can be really surprisingly expensive,
because the read ends up having to wait until the write has hit the
cacheline, and we might talk tens of cycles of latency here. But
"write 32 bits, read the low 8 bits" *should* be fast on pretty much
all x86 chips, afaik."
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1425675332-31576-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-03-06 21:55:32 +01:00
testb $ 0 x1 , % c l / * i s i t a d e s t i n a t i o n p a g e ? * /
2005-06-25 14:58:02 -07:00
jz 2 f
movq % r c x , % r d i
andq $ 0 x f f f f f f f f f f f f f00 0 , % r d i
jmp 0 b
2 :
x86/asm: Optimize unnecessarily wide TEST instructions
By the nature of the TEST operation, it is often possible to test
a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
This results in shorter instructions, because the TEST instruction
has no sign-entending byte-immediate forms unlike other ALU ops.
Note that this change does not create any LCP (Length-Changing Prefix)
stalls, which happen when adding a 0x66 prefix, which happens when
16-bit immediates are used, which changes such TEST instructions:
[test_opcode] [modrm] [imm32]
to:
[0x66] [test_opcode] [modrm] [imm16]
where [imm16] has a *different length* now: 2 bytes instead of 4.
This confuses the decoder and slows down execution.
REX prefixes were carefully designed to almost never hit this case:
adding REX prefix does not change instruction length except MOVABS
and MOV [addr],RAX instruction.
This patch does not add instructions which would use a 0x66 prefix,
code changes in assembly are:
-48 f7 07 01 00 00 00 testq $0x1,(%rdi)
+f6 07 01 testb $0x1,(%rdi)
-48 f7 c1 01 00 00 00 test $0x1,%rcx
+f6 c1 01 test $0x1,%cl
-48 f7 c1 02 00 00 00 test $0x2,%rcx
+f6 c1 02 test $0x2,%cl
-41 f7 c2 01 00 00 00 test $0x1,%r10d
+41 f6 c2 01 test $0x1,%r10b
-48 f7 c1 04 00 00 00 test $0x4,%rcx
+f6 c1 04 test $0x4,%cl
-48 f7 c1 08 00 00 00 test $0x8,%rcx
+f6 c1 08 test $0x8,%cl
Linus further notes:
"There are no stalls from using 8-bit instruction forms.
Now, changing from 64-bit or 32-bit 'test' instructions to 8-bit ones
*could* cause problems if it ends up having forwarding issues, so that
instead of just forwarding the result, you end up having to wait for
it to be stable in the L1 cache (or possibly the register file). The
forwarding from the store buffer is simplest and most reliable if the
read is done at the exact same address and the exact same size as the
write that gets forwarded.
But that's true only if:
(a) the write was very recent and is still in the write queue. I'm
not sure that's the case here anyway.
(b) on at least most Intel microarchitectures, you have to test a
different byte than the lowest one (so forwarding a 64-bit write
to a 8-bit read ends up working fine, as long as the 8-bit read
is of the low 8 bits of the written data).
A very similar issue *might* show up for registers too, not just
memory writes, if you use 'testb' with a high-byte register (where
instead of forwarding the value from the original producer it needs to
go through the register file and then shifted). But it's mainly a
problem for store buffers.
But afaik, the way Denys changed the test instructions, neither of the
above issues should be true.
The real problem for store buffer forwarding tends to be "write 8
bits, read 32 bits". That can be really surprisingly expensive,
because the read ends up having to wait until the write has hit the
cacheline, and we might talk tens of cycles of latency here. But
"write 32 bits, read the low 8 bits" *should* be fast on pretty much
all x86 chips, afaik."
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1425675332-31576-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-03-06 21:55:32 +01:00
testb $ 0 x2 , % c l / * i s i t a n i n d i r e c t i o n p a g e ? * /
2005-06-25 14:58:02 -07:00
jz 2 f
movq % r c x , % r b x
andq $ 0 x f f f f f f f f f f f f f00 0 , % r b x
jmp 0 b
2 :
x86/asm: Optimize unnecessarily wide TEST instructions
By the nature of the TEST operation, it is often possible to test
a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
This results in shorter instructions, because the TEST instruction
has no sign-entending byte-immediate forms unlike other ALU ops.
Note that this change does not create any LCP (Length-Changing Prefix)
stalls, which happen when adding a 0x66 prefix, which happens when
16-bit immediates are used, which changes such TEST instructions:
[test_opcode] [modrm] [imm32]
to:
[0x66] [test_opcode] [modrm] [imm16]
where [imm16] has a *different length* now: 2 bytes instead of 4.
This confuses the decoder and slows down execution.
REX prefixes were carefully designed to almost never hit this case:
adding REX prefix does not change instruction length except MOVABS
and MOV [addr],RAX instruction.
This patch does not add instructions which would use a 0x66 prefix,
code changes in assembly are:
-48 f7 07 01 00 00 00 testq $0x1,(%rdi)
+f6 07 01 testb $0x1,(%rdi)
-48 f7 c1 01 00 00 00 test $0x1,%rcx
+f6 c1 01 test $0x1,%cl
-48 f7 c1 02 00 00 00 test $0x2,%rcx
+f6 c1 02 test $0x2,%cl
-41 f7 c2 01 00 00 00 test $0x1,%r10d
+41 f6 c2 01 test $0x1,%r10b
-48 f7 c1 04 00 00 00 test $0x4,%rcx
+f6 c1 04 test $0x4,%cl
-48 f7 c1 08 00 00 00 test $0x8,%rcx
+f6 c1 08 test $0x8,%cl
Linus further notes:
"There are no stalls from using 8-bit instruction forms.
Now, changing from 64-bit or 32-bit 'test' instructions to 8-bit ones
*could* cause problems if it ends up having forwarding issues, so that
instead of just forwarding the result, you end up having to wait for
it to be stable in the L1 cache (or possibly the register file). The
forwarding from the store buffer is simplest and most reliable if the
read is done at the exact same address and the exact same size as the
write that gets forwarded.
But that's true only if:
(a) the write was very recent and is still in the write queue. I'm
not sure that's the case here anyway.
(b) on at least most Intel microarchitectures, you have to test a
different byte than the lowest one (so forwarding a 64-bit write
to a 8-bit read ends up working fine, as long as the 8-bit read
is of the low 8 bits of the written data).
A very similar issue *might* show up for registers too, not just
memory writes, if you use 'testb' with a high-byte register (where
instead of forwarding the value from the original producer it needs to
go through the register file and then shifted). But it's mainly a
problem for store buffers.
But afaik, the way Denys changed the test instructions, neither of the
above issues should be true.
The real problem for store buffer forwarding tends to be "write 8
bits, read 32 bits". That can be really surprisingly expensive,
because the read ends up having to wait until the write has hit the
cacheline, and we might talk tens of cycles of latency here. But
"write 32 bits, read the low 8 bits" *should* be fast on pretty much
all x86 chips, afaik."
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1425675332-31576-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-03-06 21:55:32 +01:00
testb $ 0 x4 , % c l / * i s i t t h e d o n e i n d i c a t o r ? * /
2005-06-25 14:58:02 -07:00
jz 2 f
jmp 3 f
2 :
x86/asm: Optimize unnecessarily wide TEST instructions
By the nature of the TEST operation, it is often possible to test
a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
This results in shorter instructions, because the TEST instruction
has no sign-entending byte-immediate forms unlike other ALU ops.
Note that this change does not create any LCP (Length-Changing Prefix)
stalls, which happen when adding a 0x66 prefix, which happens when
16-bit immediates are used, which changes such TEST instructions:
[test_opcode] [modrm] [imm32]
to:
[0x66] [test_opcode] [modrm] [imm16]
where [imm16] has a *different length* now: 2 bytes instead of 4.
This confuses the decoder and slows down execution.
REX prefixes were carefully designed to almost never hit this case:
adding REX prefix does not change instruction length except MOVABS
and MOV [addr],RAX instruction.
This patch does not add instructions which would use a 0x66 prefix,
code changes in assembly are:
-48 f7 07 01 00 00 00 testq $0x1,(%rdi)
+f6 07 01 testb $0x1,(%rdi)
-48 f7 c1 01 00 00 00 test $0x1,%rcx
+f6 c1 01 test $0x1,%cl
-48 f7 c1 02 00 00 00 test $0x2,%rcx
+f6 c1 02 test $0x2,%cl
-41 f7 c2 01 00 00 00 test $0x1,%r10d
+41 f6 c2 01 test $0x1,%r10b
-48 f7 c1 04 00 00 00 test $0x4,%rcx
+f6 c1 04 test $0x4,%cl
-48 f7 c1 08 00 00 00 test $0x8,%rcx
+f6 c1 08 test $0x8,%cl
Linus further notes:
"There are no stalls from using 8-bit instruction forms.
Now, changing from 64-bit or 32-bit 'test' instructions to 8-bit ones
*could* cause problems if it ends up having forwarding issues, so that
instead of just forwarding the result, you end up having to wait for
it to be stable in the L1 cache (or possibly the register file). The
forwarding from the store buffer is simplest and most reliable if the
read is done at the exact same address and the exact same size as the
write that gets forwarded.
But that's true only if:
(a) the write was very recent and is still in the write queue. I'm
not sure that's the case here anyway.
(b) on at least most Intel microarchitectures, you have to test a
different byte than the lowest one (so forwarding a 64-bit write
to a 8-bit read ends up working fine, as long as the 8-bit read
is of the low 8 bits of the written data).
A very similar issue *might* show up for registers too, not just
memory writes, if you use 'testb' with a high-byte register (where
instead of forwarding the value from the original producer it needs to
go through the register file and then shifted). But it's mainly a
problem for store buffers.
But afaik, the way Denys changed the test instructions, neither of the
above issues should be true.
The real problem for store buffer forwarding tends to be "write 8
bits, read 32 bits". That can be really surprisingly expensive,
because the read ends up having to wait until the write has hit the
cacheline, and we might talk tens of cycles of latency here. But
"write 32 bits, read the low 8 bits" *should* be fast on pretty much
all x86 chips, afaik."
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1425675332-31576-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-03-06 21:55:32 +01:00
testb $ 0 x8 , % c l / * i s i t t h e s o u r c e i n d i c a t o r ? * /
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jz 0 b / * I g n o r e i t o t h e r w i s e * /
movq % r c x , % r s i / * F o r e v e r s o u r c e p a g e d o a c o p y * /
andq $ 0 x f f f f f f f f f f f f f00 0 , % r s i
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movq % r d i , % r d x
movq % r s i , % r a x
movq % r10 , % r d i
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movl $ 5 1 2 , % e c x
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rep ; movsq
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movq % r a x , % r d i
movq % r d x , % r s i
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movl $ 5 1 2 , % e c x
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rep ; movsq
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movq % r d x , % r d i
movq % r10 , % r s i
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movl $ 5 1 2 , % e c x
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rep ; movsq
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lea P A G E _ S I Z E ( % r a x ) , % r s i
jmp 0 b
3 :
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ret
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.globl kexec_control_code_size
.set _ c o n t r o l _ c o d e _ s i z e , . - r e l o c a t e _ k e r n e l
