2018-07-30 10:49:55 +03:00
// SPDX-License-Identifier: GPL-2.0
2015-11-10 04:15:09 +03:00
/*
* CS2000 - - CIRRUS LOGIC Fractional - N Clock Synthesizer & Clock Multiplier
*
* Copyright ( C ) 2015 Renesas Electronics Corporation
* Kuninori Morimoto < kuninori . morimoto . gx @ renesas . com >
*/
# include <linux/clk-provider.h>
# include <linux/delay.h>
# include <linux/clk.h>
# include <linux/i2c.h>
# include <linux/of_device.h>
# include <linux/module.h>
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# include <linux/regmap.h>
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# define CH_MAX 4
# define RATIO_REG_SIZE 4
# define DEVICE_ID 0x1
# define DEVICE_CTRL 0x2
# define DEVICE_CFG1 0x3
# define DEVICE_CFG2 0x4
# define GLOBAL_CFG 0x5
# define Ratio_Add(x, nth) (6 + (x * 4) + (nth))
# define Ratio_Val(x, nth) ((x >> (24 - (8 * nth))) & 0xFF)
# define Val_Ratio(x, nth) ((x & 0xFF) << (24 - (8 * nth)))
# define FUNC_CFG1 0x16
# define FUNC_CFG2 0x17
/* DEVICE_ID */
# define REVISION_MASK (0x7)
# define REVISION_B2_B3 (0x4)
# define REVISION_C1 (0x6)
/* DEVICE_CTRL */
# define PLL_UNLOCK (1 << 7)
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# define AUXOUTDIS (1 << 1)
# define CLKOUTDIS (1 << 0)
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/* DEVICE_CFG1 */
# define RSEL(x) (((x) & 0x3) << 3)
# define RSEL_MASK RSEL(0x3)
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# define AUXOUTSRC(x) (((x) & 0x3) << 1)
# define AUXOUTSRC_MASK AUXOUTSRC(0x3)
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# define ENDEV1 (0x1)
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/* DEVICE_CFG2 */
# define AUTORMOD (1 << 3)
# define LOCKCLK(x) (((x) & 0x3) << 1)
# define LOCKCLK_MASK LOCKCLK(0x3)
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# define FRACNSRC_MASK (1 << 0)
# define FRACNSRC_STATIC (0 << 0)
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
# define FRACNSRC_DYNAMIC (1 << 0)
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/* GLOBAL_CFG */
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# define FREEZE (1 << 7)
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# define ENDEV2 (0x1)
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/* FUNC_CFG1 */
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# define CLKSKIPEN (1 << 7)
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# define REFCLKDIV(x) (((x) & 0x3) << 3)
# define REFCLKDIV_MASK REFCLKDIV(0x3)
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/* FUNC_CFG2 */
# define LFRATIO_MASK (1 << 3)
# define LFRATIO_20_12 (0 << 3)
# define LFRATIO_12_20 (1 << 3)
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# define CH_SIZE_ERR(ch) ((ch < 0) || (ch >= CH_MAX))
# define hw_to_priv(_hw) container_of(_hw, struct cs2000_priv, hw)
# define priv_to_client(priv) (priv->client)
# define priv_to_dev(priv) (&(priv_to_client(priv)->dev))
# define CLK_IN 0
# define REF_CLK 1
# define CLK_MAX 2
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static bool cs2000_readable_reg ( struct device * dev , unsigned int reg )
{
return reg > 0 ;
}
static bool cs2000_writeable_reg ( struct device * dev , unsigned int reg )
{
return reg ! = DEVICE_ID ;
}
static bool cs2000_volatile_reg ( struct device * dev , unsigned int reg )
{
return reg = = DEVICE_CTRL ;
}
static const struct regmap_config cs2000_regmap_config = {
. reg_bits = 8 ,
. val_bits = 8 ,
. max_register = FUNC_CFG2 ,
. readable_reg = cs2000_readable_reg ,
. writeable_reg = cs2000_writeable_reg ,
. volatile_reg = cs2000_volatile_reg ,
} ;
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struct cs2000_priv {
struct clk_hw hw ;
struct i2c_client * client ;
struct clk * clk_in ;
struct clk * ref_clk ;
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struct regmap * regmap ;
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clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
bool dynamic_mode ;
bool lf_ratio ;
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bool clk_skip ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
2017-01-10 09:50:58 +03:00
/* suspend/resume */
unsigned long saved_rate ;
unsigned long saved_parent_rate ;
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} ;
static const struct of_device_id cs2000_of_match [ ] = {
{ . compatible = " cirrus,cs2000-cp " , } ,
{ } ,
} ;
MODULE_DEVICE_TABLE ( of , cs2000_of_match ) ;
static const struct i2c_device_id cs2000_id [ ] = {
{ " cs2000-cp " , } ,
{ }
} ;
MODULE_DEVICE_TABLE ( i2c , cs2000_id ) ;
static int cs2000_enable_dev_config ( struct cs2000_priv * priv , bool enable )
{
int ret ;
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ret = regmap_update_bits ( priv - > regmap , DEVICE_CFG1 , ENDEV1 ,
enable ? ENDEV1 : 0 ) ;
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if ( ret < 0 )
return ret ;
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ret = regmap_update_bits ( priv - > regmap , GLOBAL_CFG , ENDEV2 ,
enable ? ENDEV2 : 0 ) ;
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if ( ret < 0 )
return ret ;
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ret = regmap_update_bits ( priv - > regmap , FUNC_CFG1 , CLKSKIPEN ,
( enable & & priv - > clk_skip ) ? CLKSKIPEN : 0 ) ;
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if ( ret < 0 )
return ret ;
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return 0 ;
}
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
static int cs2000_ref_clk_bound_rate ( struct cs2000_priv * priv ,
u32 rate_in )
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{
u32 val ;
if ( rate_in > = 32000000 & & rate_in < 56000000 )
val = 0x0 ;
else if ( rate_in > = 16000000 & & rate_in < 28000000 )
val = 0x1 ;
else if ( rate_in > = 8000000 & & rate_in < 14000000 )
val = 0x2 ;
else
return - EINVAL ;
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return regmap_update_bits ( priv - > regmap , FUNC_CFG1 ,
REFCLKDIV_MASK ,
REFCLKDIV ( val ) ) ;
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}
static int cs2000_wait_pll_lock ( struct cs2000_priv * priv )
{
struct device * dev = priv_to_dev ( priv ) ;
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unsigned int i , val ;
int ret ;
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for ( i = 0 ; i < 256 ; i + + ) {
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ret = regmap_read ( priv - > regmap , DEVICE_CTRL , & val ) ;
if ( ret < 0 )
return ret ;
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if ( ! ( val & PLL_UNLOCK ) )
return 0 ;
udelay ( 1 ) ;
}
dev_err ( dev , " pll lock failed \n " ) ;
return - ETIMEDOUT ;
}
static int cs2000_clk_out_enable ( struct cs2000_priv * priv , bool enable )
{
/* enable both AUX_OUT, CLK_OUT */
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return regmap_update_bits ( priv - > regmap , DEVICE_CTRL ,
( AUXOUTDIS | CLKOUTDIS ) ,
enable ? 0 :
( AUXOUTDIS | CLKOUTDIS ) ) ;
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}
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
static u32 cs2000_rate_to_ratio ( u32 rate_in , u32 rate_out , bool lf_ratio )
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{
u64 ratio ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
u32 multiplier = lf_ratio ? 12 : 20 ;
2015-11-10 04:15:09 +03:00
/*
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
* ratio = rate_out / rate_in * 2 ^ multiplier
2015-11-10 04:15:09 +03:00
*
* To avoid over flow , rate_out is u64 .
* The result should be u32 .
*/
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
ratio = ( u64 ) rate_out < < multiplier ;
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do_div ( ratio , rate_in ) ;
return ratio ;
}
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
static unsigned long cs2000_ratio_to_rate ( u32 ratio , u32 rate_in , bool lf_ratio )
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{
u64 rate_out ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
u32 multiplier = lf_ratio ? 12 : 20 ;
2015-11-10 04:15:09 +03:00
/*
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
* ratio = rate_out / rate_in * 2 ^ multiplier
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*
* To avoid over flow , rate_out is u64 .
* The result should be u32 or unsigned long .
*/
rate_out = ( u64 ) ratio * rate_in ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
return rate_out > > multiplier ;
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}
static int cs2000_ratio_set ( struct cs2000_priv * priv ,
int ch , u32 rate_in , u32 rate_out )
{
u32 val ;
unsigned int i ;
int ret ;
if ( CH_SIZE_ERR ( ch ) )
return - EINVAL ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
val = cs2000_rate_to_ratio ( rate_in , rate_out , priv - > lf_ratio ) ;
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for ( i = 0 ; i < RATIO_REG_SIZE ; i + + ) {
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ret = regmap_write ( priv - > regmap ,
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Ratio_Add ( ch , i ) ,
Ratio_Val ( val , i ) ) ;
if ( ret < 0 )
return ret ;
}
return 0 ;
}
static u32 cs2000_ratio_get ( struct cs2000_priv * priv , int ch )
{
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unsigned int tmp , i ;
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u32 val ;
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int ret ;
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val = 0 ;
for ( i = 0 ; i < RATIO_REG_SIZE ; i + + ) {
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ret = regmap_read ( priv - > regmap , Ratio_Add ( ch , i ) , & tmp ) ;
if ( ret < 0 )
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return 0 ;
val | = Val_Ratio ( tmp , i ) ;
}
return val ;
}
static int cs2000_ratio_select ( struct cs2000_priv * priv , int ch )
{
int ret ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
u8 fracnsrc ;
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if ( CH_SIZE_ERR ( ch ) )
return - EINVAL ;
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ret = regmap_update_bits ( priv - > regmap , DEVICE_CFG1 , RSEL_MASK , RSEL ( ch ) ) ;
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if ( ret < 0 )
return ret ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
fracnsrc = priv - > dynamic_mode ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC ;
2022-01-25 12:33:36 +03:00
ret = regmap_update_bits ( priv - > regmap , DEVICE_CFG2 ,
AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK ,
LOCKCLK ( ch ) | fracnsrc ) ;
2015-11-10 04:15:09 +03:00
if ( ret < 0 )
return ret ;
return 0 ;
}
static unsigned long cs2000_recalc_rate ( struct clk_hw * hw ,
unsigned long parent_rate )
{
struct cs2000_priv * priv = hw_to_priv ( hw ) ;
int ch = 0 ; /* it uses ch0 only at this point */
u32 ratio ;
ratio = cs2000_ratio_get ( priv , ch ) ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
return cs2000_ratio_to_rate ( ratio , parent_rate , priv - > lf_ratio ) ;
2015-11-10 04:15:09 +03:00
}
static long cs2000_round_rate ( struct clk_hw * hw , unsigned long rate ,
unsigned long * parent_rate )
{
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
struct cs2000_priv * priv = hw_to_priv ( hw ) ;
2015-11-10 04:15:09 +03:00
u32 ratio ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
ratio = cs2000_rate_to_ratio ( * parent_rate , rate , priv - > lf_ratio ) ;
return cs2000_ratio_to_rate ( ratio , * parent_rate , priv - > lf_ratio ) ;
}
static int cs2000_select_ratio_mode ( struct cs2000_priv * priv ,
unsigned long rate ,
unsigned long parent_rate )
{
/*
* From the datasheet :
*
* | It is recommended that the 12.20 High - Resolution format be
* | utilized whenever the desired ratio is less than 4096 since
* | the output frequency accuracy of the PLL is directly proportional
* | to the accuracy of the timing reference clock and the resolution
* | of the R_UD .
*
* This mode is only available in dynamic mode .
*/
priv - > lf_ratio = priv - > dynamic_mode & & ( ( rate / parent_rate ) > 4096 ) ;
2015-11-10 04:15:09 +03:00
2022-01-25 12:33:36 +03:00
return regmap_update_bits ( priv - > regmap , FUNC_CFG2 , LFRATIO_MASK ,
priv - > lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20 ) ;
2015-11-10 04:15:09 +03:00
}
static int __cs2000_set_rate ( struct cs2000_priv * priv , int ch ,
unsigned long rate , unsigned long parent_rate )
{
int ret ;
2022-01-25 12:33:36 +03:00
ret = regmap_update_bits ( priv - > regmap , GLOBAL_CFG , FREEZE , FREEZE ) ;
2022-01-25 12:33:35 +03:00
if ( ret < 0 )
return ret ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
ret = cs2000_select_ratio_mode ( priv , rate , parent_rate ) ;
2015-11-10 04:15:09 +03:00
if ( ret < 0 )
return ret ;
ret = cs2000_ratio_set ( priv , ch , parent_rate , rate ) ;
if ( ret < 0 )
return ret ;
ret = cs2000_ratio_select ( priv , ch ) ;
if ( ret < 0 )
return ret ;
2022-01-25 12:33:36 +03:00
ret = regmap_update_bits ( priv - > regmap , GLOBAL_CFG , FREEZE , 0 ) ;
2022-01-25 12:33:35 +03:00
if ( ret < 0 )
return ret ;
2017-01-10 09:50:58 +03:00
priv - > saved_rate = rate ;
priv - > saved_parent_rate = parent_rate ;
2015-11-10 04:15:09 +03:00
return 0 ;
}
static int cs2000_set_rate ( struct clk_hw * hw ,
unsigned long rate , unsigned long parent_rate )
{
struct cs2000_priv * priv = hw_to_priv ( hw ) ;
int ch = 0 ; /* it uses ch0 only at this point */
return __cs2000_set_rate ( priv , ch , rate , parent_rate ) ;
}
2017-04-19 20:46:31 +03:00
static int cs2000_set_saved_rate ( struct cs2000_priv * priv )
{
int ch = 0 ; /* it uses ch0 only at this point */
return __cs2000_set_rate ( priv , ch ,
priv - > saved_rate ,
priv - > saved_parent_rate ) ;
}
2015-11-10 04:15:09 +03:00
static int cs2000_enable ( struct clk_hw * hw )
{
struct cs2000_priv * priv = hw_to_priv ( hw ) ;
int ret ;
ret = cs2000_enable_dev_config ( priv , true ) ;
if ( ret < 0 )
return ret ;
ret = cs2000_clk_out_enable ( priv , true ) ;
if ( ret < 0 )
return ret ;
ret = cs2000_wait_pll_lock ( priv ) ;
if ( ret < 0 )
return ret ;
return ret ;
}
static void cs2000_disable ( struct clk_hw * hw )
{
struct cs2000_priv * priv = hw_to_priv ( hw ) ;
cs2000_enable_dev_config ( priv , false ) ;
cs2000_clk_out_enable ( priv , false ) ;
}
static u8 cs2000_get_parent ( struct clk_hw * hw )
{
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
struct cs2000_priv * priv = hw_to_priv ( hw ) ;
/*
* In dynamic mode , output rates are derived from CLK_IN .
* In static mode , CLK_IN is ignored , so we return REF_CLK instead .
*/
return priv - > dynamic_mode ? CLK_IN : REF_CLK ;
2015-11-10 04:15:09 +03:00
}
static const struct clk_ops cs2000_ops = {
. get_parent = cs2000_get_parent ,
. recalc_rate = cs2000_recalc_rate ,
. round_rate = cs2000_round_rate ,
. set_rate = cs2000_set_rate ,
. prepare = cs2000_enable ,
. unprepare = cs2000_disable ,
} ;
static int cs2000_clk_get ( struct cs2000_priv * priv )
{
2017-04-11 03:35:49 +03:00
struct device * dev = priv_to_dev ( priv ) ;
2015-11-10 04:15:09 +03:00
struct clk * clk_in , * ref_clk ;
clk_in = devm_clk_get ( dev , " clk_in " ) ;
/* not yet provided */
if ( IS_ERR ( clk_in ) )
return - EPROBE_DEFER ;
ref_clk = devm_clk_get ( dev , " ref_clk " ) ;
/* not yet provided */
if ( IS_ERR ( ref_clk ) )
return - EPROBE_DEFER ;
priv - > clk_in = clk_in ;
priv - > ref_clk = ref_clk ;
return 0 ;
}
static int cs2000_clk_register ( struct cs2000_priv * priv )
{
struct device * dev = priv_to_dev ( priv ) ;
struct device_node * np = dev - > of_node ;
struct clk_init_data init ;
const char * name = np - > name ;
static const char * parent_names [ CLK_MAX ] ;
2022-01-25 12:33:32 +03:00
u32 aux_out = 0 ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
int ref_clk_rate ;
2015-11-10 04:15:09 +03:00
int ch = 0 ; /* it uses ch0 only at this point */
int ret ;
of_property_read_string ( np , " clock-output-names " , & name ) ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
priv - > dynamic_mode = of_property_read_bool ( np , " cirrus,dynamic-mode " ) ;
dev_info ( dev , " operating in %s mode \n " ,
priv - > dynamic_mode ? " dynamic " : " static " ) ;
2022-01-25 12:33:32 +03:00
of_property_read_u32 ( np , " cirrus,aux-output-source " , & aux_out ) ;
2022-01-25 12:33:36 +03:00
ret = regmap_update_bits ( priv - > regmap , DEVICE_CFG1 ,
AUXOUTSRC_MASK , AUXOUTSRC ( aux_out ) ) ;
2022-01-25 12:33:32 +03:00
if ( ret < 0 )
return ret ;
2022-01-25 12:33:34 +03:00
priv - > clk_skip = of_property_read_bool ( np , " cirrus,clock-skip " ) ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
ref_clk_rate = clk_get_rate ( priv - > ref_clk ) ;
ret = cs2000_ref_clk_bound_rate ( priv , ref_clk_rate ) ;
2015-11-10 04:15:09 +03:00
if ( ret < 0 )
return ret ;
clk: cs2000-cp: add support for dynamic mode
The CS2000 chip features two input clocks, REF_CLK and CLK_IN.
In static mode, the output clock (CLK_OUT) is directly derived from
REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the
digital PLL.
In dynamic mode, a low-frequency ratio configuration that uses a higher
multiplier factor.
Until now, only the static mode and high-frequency divider rations of
the hardware was supported by the driver. This patch adds support for
dynamic mode and both ratios:
* Parse a new OF property 'cirrus,dynamic-mode' to determine the mode
* In dynamic mode, present CLK_IN as parent clock, else use REF_CLK
* The low-frequency ratio mode is automatically selected, depending
on the mode of operation and the given input and output rates
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25 12:33:33 +03:00
if ( priv - > dynamic_mode ) {
/* Default to low-frequency mode to allow for large ratios */
priv - > lf_ratio = true ;
} else {
/*
* set default rate as 1 / 1.
* otherwise . set_rate which setup ratio
* is never called if user requests 1 / 1 rate
*/
ret = __cs2000_set_rate ( priv , ch , ref_clk_rate , ref_clk_rate ) ;
if ( ret < 0 )
return ret ;
}
2015-11-10 04:15:09 +03:00
parent_names [ CLK_IN ] = __clk_get_name ( priv - > clk_in ) ;
parent_names [ REF_CLK ] = __clk_get_name ( priv - > ref_clk ) ;
init . name = name ;
init . ops = & cs2000_ops ;
init . flags = CLK_SET_RATE_GATE ;
init . parent_names = parent_names ;
init . num_parents = ARRAY_SIZE ( parent_names ) ;
priv - > hw . init = & init ;
2016-06-02 02:15:13 +03:00
ret = clk_hw_register ( dev , & priv - > hw ) ;
if ( ret )
return ret ;
2015-11-10 04:15:09 +03:00
2016-06-02 02:15:13 +03:00
ret = of_clk_add_hw_provider ( np , of_clk_hw_simple_get , & priv - > hw ) ;
2015-11-10 04:15:09 +03:00
if ( ret < 0 ) {
2016-06-02 02:15:13 +03:00
clk_hw_unregister ( & priv - > hw ) ;
2015-11-10 04:15:09 +03:00
return ret ;
}
return 0 ;
}
static int cs2000_version_print ( struct cs2000_priv * priv )
{
2017-04-11 03:35:49 +03:00
struct device * dev = priv_to_dev ( priv ) ;
2015-11-10 04:15:09 +03:00
const char * revision ;
2022-01-25 12:33:36 +03:00
unsigned int val ;
int ret ;
2015-11-10 04:15:09 +03:00
2022-01-25 12:33:36 +03:00
ret = regmap_read ( priv - > regmap , DEVICE_ID , & val ) ;
if ( ret < 0 )
return ret ;
2015-11-10 04:15:09 +03:00
/* CS2000 should be 0x0 */
if ( val > > 3 )
return - EIO ;
switch ( val & REVISION_MASK ) {
case REVISION_B2_B3 :
revision = " B2 / B3 " ;
break ;
case REVISION_C1 :
revision = " C1 " ;
break ;
default :
return - EIO ;
}
dev_info ( dev , " revision - %s \n " , revision ) ;
return 0 ;
}
2022-08-15 11:02:30 +03:00
static void cs2000_remove ( struct i2c_client * client )
2015-11-10 04:15:09 +03:00
{
struct cs2000_priv * priv = i2c_get_clientdata ( client ) ;
2017-04-11 03:35:49 +03:00
struct device * dev = priv_to_dev ( priv ) ;
2015-11-10 04:15:09 +03:00
struct device_node * np = dev - > of_node ;
of_clk_del_provider ( np ) ;
2016-06-02 02:15:13 +03:00
clk_hw_unregister ( & priv - > hw ) ;
2015-11-10 04:15:09 +03:00
}
2022-04-07 18:18:24 +03:00
static int cs2000_probe ( struct i2c_client * client )
2015-11-10 04:15:09 +03:00
{
struct cs2000_priv * priv ;
struct device * dev = & client - > dev ;
int ret ;
priv = devm_kzalloc ( dev , sizeof ( * priv ) , GFP_KERNEL ) ;
if ( ! priv )
return - ENOMEM ;
priv - > client = client ;
i2c_set_clientdata ( client , priv ) ;
2022-01-25 12:33:36 +03:00
priv - > regmap = devm_regmap_init_i2c ( client , & cs2000_regmap_config ) ;
if ( IS_ERR ( priv - > regmap ) )
return PTR_ERR ( priv - > regmap ) ;
2015-11-10 04:15:09 +03:00
ret = cs2000_clk_get ( priv ) ;
if ( ret < 0 )
return ret ;
ret = cs2000_clk_register ( priv ) ;
if ( ret < 0 )
return ret ;
ret = cs2000_version_print ( priv ) ;
if ( ret < 0 )
goto probe_err ;
return 0 ;
probe_err :
cs2000_remove ( client ) ;
return ret ;
}
2018-04-09 13:54:34 +03:00
static int __maybe_unused cs2000_resume ( struct device * dev )
2017-01-10 09:50:58 +03:00
{
struct cs2000_priv * priv = dev_get_drvdata ( dev ) ;
2017-04-19 20:46:31 +03:00
return cs2000_set_saved_rate ( priv ) ;
2017-01-10 09:50:58 +03:00
}
static const struct dev_pm_ops cs2000_pm_ops = {
2018-03-20 11:33:23 +03:00
SET_LATE_SYSTEM_SLEEP_PM_OPS ( NULL , cs2000_resume )
2017-01-10 09:50:58 +03:00
} ;
2015-11-10 04:15:09 +03:00
static struct i2c_driver cs2000_driver = {
. driver = {
. name = " cs2000-cp " ,
2017-01-10 09:50:58 +03:00
. pm = & cs2000_pm_ops ,
2015-11-10 04:15:09 +03:00
. of_match_table = cs2000_of_match ,
} ,
2022-04-07 18:18:24 +03:00
. probe_new = cs2000_probe ,
2015-11-10 04:15:09 +03:00
. remove = cs2000_remove ,
. id_table = cs2000_id ,
} ;
module_i2c_driver ( cs2000_driver ) ;
MODULE_DESCRIPTION ( " CS2000-CP driver " ) ;
MODULE_AUTHOR ( " Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> " ) ;
MODULE_LICENSE ( " GPL v2 " ) ;