2011-02-26 15:23:59 +03:00
/ *
* linux/ a r c h / u n i c o r e 3 2 / k e r n e l / s l e e p . S
*
* Code s p e c i f i c t o P K U n i t y S o C a n d U n i C o r e I S A
*
* Maintained b y G U A N X u e - t a o < g x t @mprc.pku.edu.cn>
* Copyright ( C ) 2 0 0 1 - 2 0 1 0 G u a n X u e t a o
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
* /
# include < l i n u x / l i n k a g e . h >
# include < a s m / a s s e m b l e r . h >
# include < m a c h / h a r d w a r e . h >
.text
pkunity_cpu_save_cp :
@ get coprocessor registers
movc r3 , p0 . c7 , #0 @ PID
movc r4 , p0 . c2 , #0 @ translation table base addr
movc r5 , p0 . c1 , #0 @ control reg
@ store them plus current virtual stack ptr on stack
mov r6 , s p
stm. w ( r3 - r6 ) , [ s p - ]
mov p c , l r
pkunity_cpu_save_sp :
@ preserve phys address of stack
mov r0 , s p
stw. w l r , [ s p + ] , #- 4
b. l s l e e p _ p h y s _ s p
ldw r1 , =sleep_save_sp
stw r0 , [ r1 ]
ldw. w p c , [ s p ] + , #4
/ *
* puv3 _ c p u _ s u s p e n d ( )
*
* Forces C P U i n t o s l e e p s t a t e .
*
* r0 = v a l u e f o r P W R M O D E M f i e l d f o r d e s i r e d s l e e p s t a t e
* /
ENTRY( p u v3 _ c p u _ s u s p e n d )
stm. w ( r16 - r27 , l r ) , [ s p - ] @ save registers on stack
stm. w ( r4 - r15 ) , [ s p - ] @ save registers on stack
# ifdef C O N F I G _ U N I C O R E _ F P U _ F 6 4
sfm. w ( f0 - f7 ) , [ s p - ]
sfm. w ( f8 - f15 ) , [ s p - ]
sfm. w ( f16 - f23 ) , [ s p - ]
sfm. w ( f24 - f31 ) , [ s p - ]
cff r4 , s31
stm. w ( r4 ) , [ s p - ]
# endif
b. l p k u n i t y _ c p u _ s a v e _ c p
b. l p k u n i t y _ c p u _ s a v e _ s p
@ clean data cache
mov r1 , #0
movc p0 . c5 , r1 , #14
nop
nop
nop
nop
@ DDR2 BaseAddr
2011-03-04 13:07:48 +03:00
ldw r0 , = ( P K U N I T Y _ D D R 2 C T R L _ B A S E )
2011-02-26 15:23:59 +03:00
@ PM BaseAddr
2011-03-04 13:07:48 +03:00
ldw r1 , = ( P K U N I T Y _ P M _ B A S E )
2011-02-26 15:23:59 +03:00
@ set PLL_SYS_CFG reg, 275
movl r6 , #0x00002401
stw r6 , [ r1 + ] , #0x18
@ set PLL_DDR_CFG reg, 66MHz
movl r6 , #0x00100c00
stw r6 , [ r1 + ] , #0x1c
@ set wake up source
movl r8 , #0x800001ff @ epip4d
stw r8 , [ r1 + ] , #0xc
@ set PGSR
movl r5 , #0x40000
stw r5 , [ r1 + ] , #0x10
@ prepare DDR2 refresh settings
ldw r5 , [ r0 + ] , #0x24
or r5 , r5 , #0x00000001
@ prepare PMCR for PLL changing
movl r6 , #0xc
@ prepare for closing PLL
movl r7 , #0x1
@ prepare sleep mode
mov r8 , #0x1
@ movl r0, 0x11111111
@ put_word_ocd r0
b p k u n i t y _ c p u _ d o _ s u s p e n d
.ltorg
.align 5
pkunity_cpu_do_suspend :
b 1 0 1 f
@ put DDR2 into self-refresh
100 : stw r5 , [ r0 + ] , #0x24
@ change PLL
stw r6 , [ r1 ]
b 1 f
.ltorg
.align 5
101 : b 1 0 2 f
@ wait for PLL changing complete
1 : ldw r6 , [ r1 + ] , #0x44
csub. a r6 , #0x1
bne 1 b
b 2 f
.ltorg
.align 5
102 : b 1 0 0 b
@ close PLL
2 : stw r7 , [ r1 + ] , #0x4
@ enter sleep mode
stw r8 , [ r1 ]
3 : b 3 b
/ *
* puv3 _ c p u _ r e s u m e ( )
*
* entry p o i n t f r o m b o o t l o a d e r i n t o k e r n e l d u r i n g r e s u m e
*
* Note : Yes, p a r t o f t h e f o l l o w i n g c o d e i s l o c a t e d i n t o t h e . d a t a s e c t i o n .
* This i s t o a l l o w s l e e p _ s a v e _ s p t o b e a c c e s s e d w i t h a r e l a t i v e l o a d
* while w e c a n ' t r e l y o n a n y M M U t r a n s l a t i o n . W e c o u l d h a v e p u t
* sleep_ s a v e _ s p i n t h e . t e x t s e c t i o n a s w e l l , b u t s o m e s e t u p s m i g h t
* insist o n i t t o b e t r u l y r e a d - o n l y .
* /
.data
.align 5
ENTRY( p u v3 _ c p u _ r e s u m e )
@ movl r0, 0x20202020
@ put_word_ocd r0
ldw r0 , s l e e p _ s a v e _ s p @ stack phys addr
ldw r2 , =resume_after_mmu @ its absolute virtual address
ldm ( r3 - r6 ) , [ r0 ] + @ CP regs + virt stack ptr
mov s p , r6 @ CP regs + virt stack ptr
mov r1 , #0
movc p0 . c6 , r1 , #6 @ invalidate I & D TLBs
movc p0 . c5 , r1 , #28 @ invalidate I & D caches, BTB
movc p0 . c7 , r3 , #0 @ PID
movc p0 . c2 , r4 , #0 @ translation table base addr
movc p0 . c1 , r5 , #0 @ control reg, turn on mmu
nop
jump r2
nop
nop
nop
nop
nop
sleep_save_sp :
.word 0 @ preserve stack phys ptr here
.text
resume_after_mmu :
@ movl r0, 0x30303030
@ put_word_ocd r0
# ifdef C O N F I G _ U N I C O R E _ F P U _ F 6 4
lfm. w ( f0 - f7 ) , [ s p ] +
lfm. w ( f8 - f15 ) , [ s p ] +
lfm. w ( f16 - f23 ) , [ s p ] +
lfm. w ( f24 - f31 ) , [ s p ] +
ldm. w ( r4 ) , [ s p ] +
ctf r4 , s31
# endif
ldm. w ( r4 - r15 ) , [ s p ] + @ restore registers from stack
ldm. w ( r16 - r27 , p c ) , [ s p ] + @ return to caller
