2005-04-17 02:20:36 +04:00
/ *
* This f i l e c o n t a i n s l o w l e v e l C P U s e t u p f u n c t i o n s .
* Copyright ( C ) 2 0 0 3 B e n j a m i n H e r r e n s c h m i d t ( b e n h @kernel.crashing.org)
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* as p u b l i s h e d b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version
* 2 of t h e L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* /
# include < a s m / p r o c e s s o r . h >
# include < a s m / p a g e . h >
# include < a s m / c p u t a b l e . h >
# include < a s m / p p c _ a s m . h >
2005-09-09 22:57:26 +04:00
# include < a s m / a s m - o f f s e t s . h >
2005-04-17 02:20:36 +04:00
# include < a s m / c a c h e . h >
2006-08-11 09:07:08 +04:00
_ GLOBAL( _ _ c p u _ p r e i n i t _ p p c97 0 )
/* Do nothing if not running in HV mode */
2005-04-17 02:20:36 +04:00
mfmsr r0
rldicl. r0 ,r0 ,4 ,6 3
beqlr
/ * Make s u r e H I D 4 : r m _ c i i s o f f b e f o r e M M U i s t u r n e d o f f , t h a t l a r g e
* pages a r e e n a b l e d w i t h H I D 4 : 6 1 a n d c l e a r H I D 5 : D C B Z _ s i z e a n d
* HID5 : DCBZ3 2 _ i l l
* /
li r0 ,0
mfspr r3 ,S P R N _ H I D 4
rldimi r3 ,r0 ,4 0 ,2 3 / * c l e a r b i t 2 3 ( r m _ c i ) * /
rldimi r3 ,r0 ,2 ,6 1 / * c l e a r b i t 6 1 ( l g _ p g _ e n ) * /
sync
mtspr S P R N _ H I D 4 ,r3
isync
sync
mfspr r3 ,S P R N _ H I D 5
rldimi r3 ,r0 ,6 ,5 6 / * c l e a r b i t s 5 6 & 5 7 ( D C B Z * ) * /
sync
mtspr S P R N _ H I D 5 ,r3
isync
sync
/* Setup some basic HID1 features */
mfspr r0 ,S P R N _ H I D 1
li r3 ,0 x12 0 0 / * e n a b l e i - f e t c h c a c h e a b i l i t y * /
sldi r3 ,r3 ,4 4 / * a n d p r e f e t c h * /
or r0 ,r0 ,r3
mtspr S P R N _ H I D 1 ,r0
mtspr S P R N _ H I D 1 ,r0
isync
/* Clear HIOR */
li r0 ,0
sync
mtspr S P R N _ H I O R ,0 / * C l e a r i n t e r r u p t p r e f i x * /
isync
blr
/* Definitions for the table use to save CPU states */
# define C S _ H I D 0 0
# define C S _ H I D 1 8
# define C S _ H I D 4 1 6
# define C S _ H I D 5 2 4
# define C S _ S I Z E 3 2
.data
.balign 1 _ C A C H E _ B Y T E S ,0
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cpu_state_storage :
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.space CS_SIZE
.balign 1 _ C A C H E _ B Y T E S ,0
.text
2005-11-09 05:38:01 +03:00
2005-04-17 02:20:36 +04:00
2006-08-11 09:07:08 +04:00
_ GLOBAL( _ _ s e t u p _ c p u _ p p c97 0 )
/* Do nothing if not running in HV mode */
2006-06-22 03:15:55 +04:00
mfmsr r0
rldicl. r0 ,r0 ,4 ,6 3
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:26:11 +04:00
beq n o _ h v _ m o d e
2006-08-11 09:07:08 +04:00
mfspr r0 ,S P R N _ H I D 0
li r11 ,5 / * c l e a r D O Z E a n d S L E E P * /
rldimi r0 ,r11 ,5 2 ,8 / * s e t N A P a n d D P M * /
2006-08-25 08:56:07 +04:00
li r11 ,0
rldimi r0 ,r11 ,3 2 ,3 1 / * c l e a r E N _ A T T N * /
2006-10-05 08:41:41 +04:00
b l o a d _ h i d s / * J u m p t o s h a r e d c o d e * /
_ GLOBAL( _ _ s e t u p _ c p u _ p p c97 0 M P )
/* Do nothing if not running in HV mode */
mfmsr r0
rldicl. r0 ,r0 ,4 ,6 3
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:26:11 +04:00
beq n o _ h v _ m o d e
2006-10-05 08:41:41 +04:00
mfspr r0 ,S P R N _ H I D 0
li r11 ,0 x15 / * c l e a r D O Z E a n d S L E E P * /
rldimi r0 ,r11 ,5 2 ,6 / * s e t D E E P N A P , N A P a n d D P M * /
li r11 ,0
rldimi r0 ,r11 ,3 2 ,3 1 / * c l e a r E N _ A T T N * /
load_hids :
2006-08-11 09:07:08 +04:00
mtspr S P R N _ H I D 0 ,r0
mfspr r0 ,S P R N _ H I D 0
mfspr r0 ,S P R N _ H I D 0
mfspr r0 ,S P R N _ H I D 0
mfspr r0 ,S P R N _ H I D 0
mfspr r0 ,S P R N _ H I D 0
mfspr r0 ,S P R N _ H I D 0
sync
isync
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:26:11 +04:00
/* Try to set LPES = 01 in HID4 */
mfspr r0 ,S P R N _ H I D 4
clrldi r0 ,r0 ,1 / * c l e a r L P E S 0 * /
ori r0 ,r0 ,H I D 4 _ L P E S 1 / * s e t L P E S 1 * /
sync
mtspr S P R N _ H I D 4 ,r0
isync
2006-08-11 09:07:08 +04:00
/* Save away cpu state */
2008-08-30 05:41:12 +04:00
LOAD_ R E G _ A D D R ( r5 ,c p u _ s t a t e _ s t o r a g e )
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/* Save HID0,1,4 and 5 */
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mfspr r3 ,S P R N _ H I D 0
std r3 ,C S _ H I D 0 ( r5 )
mfspr r3 ,S P R N _ H I D 1
std r3 ,C S _ H I D 1 ( r5 )
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:26:11 +04:00
mfspr r4 ,S P R N _ H I D 4
std r4 ,C S _ H I D 4 ( r5 )
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mfspr r3 ,S P R N _ H I D 5
std r3 ,C S _ H I D 5 ( r5 )
2005-11-09 05:38:01 +03:00
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 04:26:11 +04:00
/* See if we successfully set LPES1 to 1; if not we are in Apple mode */
andi. r4 ,r4 ,H I D 4 _ L P E S 1
bnelr
no_hv_mode :
/* Disable CPU_FTR_HVMODE and exit, since we don't have HV mode */
ld r5 ,C P U _ S P E C _ F E A T U R E S ( r4 )
LOAD_ R E G _ I M M E D I A T E ( r6 ,C P U _ F T R _ H V M O D E )
andc r5 ,r5 ,r6
std r5 ,C P U _ S P E C _ F E A T U R E S ( r4 )
2005-04-17 02:20:36 +04:00
blr
/ * Called w i t h n o M M U c o n t e x t ( t y p i c a l l y M S R : I R / D R o f f ) t o
* restore C P U s t a t e a s b a c k e d u p b y t h e p r e v i o u s
* function. T h i s d o e s n o t i n c l u d e c a c h e s e t t i n g
* /
2006-08-11 09:07:08 +04:00
_ GLOBAL( _ _ r e s t o r e _ c p u _ p p c97 0 )
/* Do nothing if not running in HV mode */
2006-06-22 03:15:55 +04:00
mfmsr r0
rldicl. r0 ,r0 ,4 ,6 3
beqlr
2008-08-30 05:41:12 +04:00
LOAD_ R E G _ A D D R ( r5 ,c p u _ s t a t e _ s t o r a g e )
2006-06-22 03:15:55 +04:00
/* Before accessing memory, we make sure rm_ci is clear */
2005-04-17 02:20:36 +04:00
li r0 ,0
mfspr r3 ,S P R N _ H I D 4
rldimi r3 ,r0 ,4 0 ,2 3 / * c l e a r b i t 2 3 ( r m _ c i ) * /
sync
mtspr S P R N _ H I D 4 ,r3
isync
sync
/* Clear interrupt prefix */
li r0 ,0
sync
mtspr S P R N _ H I O R ,0
isync
/* Restore HID0 */
ld r3 ,C S _ H I D 0 ( r5 )
sync
isync
mtspr S P R N _ H I D 0 ,r3
mfspr r3 ,S P R N _ H I D 0
mfspr r3 ,S P R N _ H I D 0
mfspr r3 ,S P R N _ H I D 0
mfspr r3 ,S P R N _ H I D 0
mfspr r3 ,S P R N _ H I D 0
mfspr r3 ,S P R N _ H I D 0
sync
isync
/* Restore HID1 */
ld r3 ,C S _ H I D 1 ( r5 )
sync
isync
mtspr S P R N _ H I D 1 ,r3
mtspr S P R N _ H I D 1 ,r3
sync
isync
2005-11-09 05:38:01 +03:00
2005-04-17 02:20:36 +04:00
/* Restore HID4 */
ld r3 ,C S _ H I D 4 ( r5 )
sync
isync
mtspr S P R N _ H I D 4 ,r3
sync
isync
/* Restore HID5 */
ld r3 ,C S _ H I D 5 ( r5 )
sync
isync
mtspr S P R N _ H I D 5 ,r3
sync
isync
blr
