2018-04-20 17:49:46 +03:00
/* SPDX-License-Identifier: GPL-2.0 */
# ifndef _ASM_S390_NOSPEC_ASM_H
# define _ASM_S390_NOSPEC_ASM_H
# include <asm/dwarf.h>
# ifdef __ASSEMBLY__
2018-06-15 11:22:18 +03:00
# ifdef CC_USING_EXPOLINE
2018-04-20 17:49:46 +03:00
/*
* The expoline macros are used to create thunks in the same format
* as gcc generates them . The ' comdat ' section flag makes sure that
* the various thunks are merged into a single copy .
*/
. macro __THUNK_PROLOG_NAME name
2022-03-06 22:56:07 +03:00
# ifdef CONFIG_EXPOLINE_EXTERN
. pushsection . text , " ax " , @ progbits
2022-03-07 00:30:42 +03:00
. align 16 , 0x07
2022-03-06 22:56:07 +03:00
# else
2018-04-20 17:49:46 +03:00
. pushsection . text . \ name , " axG " , @ progbits , \ name , comdat
2022-03-06 22:56:07 +03:00
# endif
2018-04-20 17:49:46 +03:00
. globl \ name
. hidden \ name
. type \ name , @ function
\ name :
CFI_STARTPROC
. endm
2022-03-07 00:30:42 +03:00
. macro __THUNK_EPILOG_NAME name
2018-04-20 17:49:46 +03:00
CFI_ENDPROC
2022-03-07 00:30:42 +03:00
# ifdef CONFIG_EXPOLINE_EXTERN
. size \ name , . - \ name
# endif
2018-04-20 17:49:46 +03:00
. popsection
. endm
2022-02-25 12:18:14 +03:00
. macro __THUNK_PROLOG_BR r1
2022-02-28 15:15:59 +03:00
__THUNK_PROLOG_NAME __s390_indirect_jump_r \ r1
. endm
2022-02-25 12:18:14 +03:00
. macro __THUNK_EPILOG_BR r1
2022-03-07 00:30:42 +03:00
__THUNK_EPILOG_NAME __s390_indirect_jump_r \ r1
. endm
2022-02-25 12:18:14 +03:00
. macro __THUNK_BR r1
2022-02-28 15:15:59 +03:00
jg __s390_indirect_jump_r \ r1
. endm
2022-02-25 12:18:14 +03:00
. macro __THUNK_BRASL r1 , r2
2022-02-28 15:15:59 +03:00
brasl \ r1 , __s390_indirect_jump_r \ r2
. endm
2018-04-20 17:49:46 +03:00
2022-02-25 12:18:14 +03:00
. macro __DECODE_R expand , reg
2022-05-01 21:55:05 +03:00
. set . L__decode_fail , 1
2018-04-20 17:49:46 +03:00
. irp r1 , 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15
. ifc \ reg , % r \ r1
2022-02-25 12:18:14 +03:00
\ expand \ r1
2022-05-01 21:55:05 +03:00
. set . L__decode_fail , 0
2018-04-20 17:49:46 +03:00
. endif
. endr
2022-05-01 21:55:05 +03:00
. if . L__decode_fail = = 1
2022-02-25 12:18:14 +03:00
. error " __DECODE_R failed "
2018-04-20 17:49:46 +03:00
. endif
. endm
2022-02-25 12:18:14 +03:00
. macro __DECODE_RR expand , rsave , rtarget
2022-05-01 21:55:05 +03:00
. set . L__decode_fail , 1
2018-04-20 17:49:46 +03:00
. irp r1 , 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15
. ifc \ rsave , % r \ r1
. irp r2 , 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15
. ifc \ rtarget , % r \ r2
2022-02-25 12:18:14 +03:00
\ expand \ r1 , \ r2
2022-05-01 21:55:05 +03:00
. set . L__decode_fail , 0
2018-04-20 17:49:46 +03:00
. endif
. endr
. endif
. endr
2022-05-01 21:55:05 +03:00
. if . L__decode_fail = = 1
2022-02-25 12:18:14 +03:00
. error " __DECODE_RR failed "
2018-04-20 17:49:46 +03:00
. endif
. endm
2022-02-25 12:18:14 +03:00
. macro __THUNK_EX_BR reg
2018-04-20 17:49:46 +03:00
exrl 0 , 555f
j .
555 : br \ reg
. endm
2022-03-06 22:56:07 +03:00
# ifdef CONFIG_EXPOLINE_EXTERN
2022-02-25 12:18:14 +03:00
. macro GEN_BR_THUNK reg
2022-03-06 22:56:07 +03:00
. endm
2022-02-25 12:18:14 +03:00
. macro GEN_BR_THUNK_EXTERN reg
2022-03-06 22:56:07 +03:00
# else
2022-02-25 12:18:14 +03:00
. macro GEN_BR_THUNK reg
2022-03-06 22:56:07 +03:00
# endif
2022-02-25 12:18:14 +03:00
__DECODE_R __THUNK_PROLOG_BR , \ reg
__THUNK_EX_BR \ reg
__DECODE_R __THUNK_EPILOG_BR , \ reg
2018-04-20 17:49:46 +03:00
. endm
2022-02-25 12:18:14 +03:00
. macro BR_EX reg
557 : __DECODE_R __THUNK_BR , \ reg
2018-04-20 17:49:46 +03:00
. pushsection . s390_indirect_branches , " a " , @ progbits
. long 557 b - .
. popsection
. endm
2022-02-25 12:18:14 +03:00
. macro BASR_EX rsave , rtarget
559 : __DECODE_RR __THUNK_BRASL , \ rsave , \ rtarget
2018-04-20 17:49:46 +03:00
. pushsection . s390_indirect_branches , " a " , @ progbits
. long 559 b - .
. popsection
. endm
# else
2022-02-25 12:18:14 +03:00
. macro GEN_BR_THUNK reg
2018-04-20 17:49:46 +03:00
. endm
2022-02-25 12:18:14 +03:00
. macro BR_EX reg
2018-04-20 17:49:46 +03:00
br \ reg
. endm
2022-02-25 12:18:14 +03:00
. macro BASR_EX rsave , rtarget
2018-04-20 17:49:46 +03:00
basr \ rsave , \ rtarget
. endm
2018-06-15 11:22:18 +03:00
# endif /* CC_USING_EXPOLINE */
2018-04-20 17:49:46 +03:00
# endif /* __ASSEMBLY__ */
# endif /* _ASM_S390_NOSPEC_ASM_H */