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linux/drivers/pinctrl/freescale/pinctrl-imx8dxl.c

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pinctrl: imx: Add imx8dxl driver i.MX8DXL contains a system controller that is responsible for controlling the pad setting of the IPs that are present. Communication between the host processor running an OS and the system controller happens through a SCU protocol, add support for the SCU based i.MX8DXL pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Link: https://lore.kernel.org/r/1585306559-13973-2-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27 18:55:58 +08:00
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019~2020 NXP
*/
#include <dt-bindings/pinctrl/pads-imx8dxl.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_PERST_B),
IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_CLKREQ_B),
IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_WAKE_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC0),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC1),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC2),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC3),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CLK),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CMD),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA0),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA1),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA2),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA3),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA4),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA5),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA6),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA7),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_STROBE),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_RESET_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_RESET_B),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_VSELECT),
IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_RE_P_N),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_WP),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_CD_B),
IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_DQS_P_N),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDIO),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDC),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_SCK),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDO),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDI),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS0),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS1),
IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN1),
IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN0),
IMX_PINCTRL_PIN(IMX8DXL_MCLK_OUT0),
IMX_PINCTRL_PIN(IMX8DXL_UART1_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART1_RX),
IMX_PINCTRL_PIN(IMX8DXL_UART1_RTS_B),
IMX_PINCTRL_PIN(IMX8DXL_UART1_CTS_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_SCK),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDI),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDO),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS1),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS0),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN1),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN0),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN3),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN2),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN5),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN4),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_RX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_TX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_RX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_TX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_RX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART0_RX),
IMX_PINCTRL_PIN(IMX8DXL_UART0_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART2_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART2_RX),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
IMX_PINCTRL_PIN(IMX8DXL_JTAG_TRST_B),
IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SCL),
IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SDA),
IMX_PINCTRL_PIN(IMX8DXL_PMIC_INT_B),
IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_00),
IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_01),
IMX_PINCTRL_PIN(IMX8DXL_SCU_PMIC_STANDBY),
IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE1),
IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE0),
IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE2),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT1),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT2),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT3),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT4),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN0),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN1),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN2),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN3),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_SCK),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDO),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDI),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_CS0),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA1),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA0),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA3),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA2),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SS0_B),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DQS),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SCLK),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SCLK),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DQS),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA1),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA0),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA3),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA2),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SS0_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B)
};
pinctrl: imx8dxl: Constify imx_pinctrl_soc_info The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Reported-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210716131341.3370620-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-16 10:13:41 -03:00
static const struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = {
pinctrl: imx: Add imx8dxl driver i.MX8DXL contains a system controller that is responsible for controlling the pad setting of the IPs that are present. Communication between the host processor running an OS and the system controller happens through a SCU protocol, add support for the SCU based i.MX8DXL pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Link: https://lore.kernel.org/r/1585306559-13973-2-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27 18:55:58 +08:00
.pins = imx8dxl_pinctrl_pads,
.npins = ARRAY_SIZE(imx8dxl_pinctrl_pads),
.flags = IMX_USE_SCU,
pinctrl: imx: Use function callbacks for SCU related functions Use function callbacks for SCU related functions in pinctrl-imx.c in order to support the scenario of PINCTRL_IMX is built in while PINCTRL_IMX_SCU is built as module, all drivers using SCU pinctrl driver need to initialize the SCU related function callback, and no need to check CONFIG_PINCTRL_IMX_SCU anymore, hence stub functions also can be removed. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/1599552721-24872-1-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-09-08 16:11:59 +08:00
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
pinctrl: imx: Add imx8dxl driver i.MX8DXL contains a system controller that is responsible for controlling the pad setting of the IPs that are present. Communication between the host processor running an OS and the system controller happens through a SCU protocol, add support for the SCU based i.MX8DXL pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Link: https://lore.kernel.org/r/1585306559-13973-2-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27 18:55:58 +08:00
};
static const struct of_device_id imx8dxl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8dxl-iomuxc", },
{ /* sentinel */ }
};
pinctrl: imx8dxl: Support building as module Change configuration to "tristate", add module device table, author, description and license to support building i.MX8DXL pinctrl driver as module. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/1592979844-18833-10-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-06-24 14:24:04 +08:00
MODULE_DEVICE_TABLE(of, imx8dxl_pinctrl_of_match);
pinctrl: imx: Add imx8dxl driver i.MX8DXL contains a system controller that is responsible for controlling the pad setting of the IPs that are present. Communication between the host processor running an OS and the system controller happens through a SCU protocol, add support for the SCU based i.MX8DXL pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Link: https://lore.kernel.org/r/1585306559-13973-2-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27 18:55:58 +08:00
static int imx8dxl_pinctrl_probe(struct platform_device *pdev)
{
int ret;
ret = imx_pinctrl_sc_ipc_init(pdev);
if (ret)
return ret;
return imx_pinctrl_probe(pdev, &imx8dxl_pinctrl_info);
}
static struct platform_driver imx8dxl_pinctrl_driver = {
.driver = {
.name = "fsl,imx8dxl-iomuxc",
pinctrl: imx: Remove unneeded of_match_ptr() i.MX is a DT-only platform, so of_match_ptr() can be safely removed. Remove the unneeded of_match_ptr(). Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210328183034.555702-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-28 15:30:33 -03:00
.of_match_table = imx8dxl_pinctrl_of_match,
pinctrl: imx: Add imx8dxl driver i.MX8DXL contains a system controller that is responsible for controlling the pad setting of the IPs that are present. Communication between the host processor running an OS and the system controller happens through a SCU protocol, add support for the SCU based i.MX8DXL pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Link: https://lore.kernel.org/r/1585306559-13973-2-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-27 18:55:58 +08:00
.suppress_bind_attrs = true,
},
.probe = imx8dxl_pinctrl_probe,
};
static int __init imx8dxl_pinctrl_init(void)
{
return platform_driver_register(&imx8dxl_pinctrl_driver);
}
arch_initcall(imx8dxl_pinctrl_init);
pinctrl: imx8dxl: Support building as module Change configuration to "tristate", add module device table, author, description and license to support building i.MX8DXL pinctrl driver as module. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/1592979844-18833-10-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-06-24 14:24:04 +08:00
MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX8DXL pinctrl driver");
MODULE_LICENSE("GPL v2");
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