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/* SPDX-License-Identifier: GPL-2.0-only */
# ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
# define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
# include "mtk-pm-domains.h"
# include <dt-bindings/power/mt8192-power.h>
/*
* MT8192 power domain support
*/
static const struct scpsys_domain_data scpsys_domain_data_mt8192 [ ] = {
[ MT8192_POWER_DOMAIN_AUDIO ] = {
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. name = " audio " ,
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. sta_mask = BIT ( 21 ) ,
. ctl_offs = 0x0354 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_2_AUDIO ,
MT8192_TOP_AXI_PROT_EN_2_SET ,
MT8192_TOP_AXI_PROT_EN_2_CLR ,
MT8192_TOP_AXI_PROT_EN_2_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_CONN ] = {
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. name = " conn " ,
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. sta_mask = PWR_STATUS_CONN ,
. ctl_offs = 0x0304 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = 0 ,
. sram_pdn_ack_bits = 0 ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_CONN ,
MT8192_TOP_AXI_PROT_EN_SET ,
MT8192_TOP_AXI_PROT_EN_CLR ,
MT8192_TOP_AXI_PROT_EN_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_CONN_2ND ,
MT8192_TOP_AXI_PROT_EN_SET ,
MT8192_TOP_AXI_PROT_EN_CLR ,
MT8192_TOP_AXI_PROT_EN_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_1_CONN ,
MT8192_TOP_AXI_PROT_EN_1_SET ,
MT8192_TOP_AXI_PROT_EN_1_CLR ,
MT8192_TOP_AXI_PROT_EN_1_STA1 ) ,
} ,
. caps = MTK_SCPD_KEEP_DEFAULT_OFF ,
} ,
[ MT8192_POWER_DOMAIN_MFG0 ] = {
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. name = " mfg0 " ,
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. sta_mask = BIT ( 2 ) ,
. ctl_offs = 0x0308 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
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. caps = MTK_SCPD_DOMAIN_SUPPLY ,
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} ,
[ MT8192_POWER_DOMAIN_MFG1 ] = {
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. name = " mfg1 " ,
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. sta_mask = BIT ( 3 ) ,
. ctl_offs = 0x030c ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_1_MFG1 ,
MT8192_TOP_AXI_PROT_EN_1_SET ,
MT8192_TOP_AXI_PROT_EN_1_CLR ,
MT8192_TOP_AXI_PROT_EN_1_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_2_MFG1 ,
MT8192_TOP_AXI_PROT_EN_2_SET ,
MT8192_TOP_AXI_PROT_EN_2_CLR ,
MT8192_TOP_AXI_PROT_EN_2_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MFG1 ,
MT8192_TOP_AXI_PROT_EN_SET ,
MT8192_TOP_AXI_PROT_EN_CLR ,
MT8192_TOP_AXI_PROT_EN_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND ,
MT8192_TOP_AXI_PROT_EN_2_SET ,
MT8192_TOP_AXI_PROT_EN_2_CLR ,
MT8192_TOP_AXI_PROT_EN_2_STA1 ) ,
} ,
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. caps = MTK_SCPD_DOMAIN_SUPPLY ,
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} ,
[ MT8192_POWER_DOMAIN_MFG2 ] = {
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. name = " mfg2 " ,
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. sta_mask = BIT ( 4 ) ,
. ctl_offs = 0x0310 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_MFG3 ] = {
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. name = " mfg3 " ,
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. sta_mask = BIT ( 5 ) ,
. ctl_offs = 0x0314 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_MFG4 ] = {
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. name = " mfg4 " ,
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. sta_mask = BIT ( 6 ) ,
. ctl_offs = 0x0318 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_MFG5 ] = {
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. name = " mfg5 " ,
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. sta_mask = BIT ( 7 ) ,
. ctl_offs = 0x031c ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_MFG6 ] = {
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. name = " mfg6 " ,
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. sta_mask = BIT ( 8 ) ,
. ctl_offs = 0x0320 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_DISP ] = {
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. name = " disp " ,
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. sta_mask = BIT ( 20 ) ,
. ctl_offs = 0x0350 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR_IGN ( MT8192_TOP_AXI_PROT_EN_MM_DISP ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR_IGN ( MT8192_TOP_AXI_PROT_EN_MM_2_DISP ,
MT8192_TOP_AXI_PROT_EN_MM_2_SET ,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_DISP ,
MT8192_TOP_AXI_PROT_EN_SET ,
MT8192_TOP_AXI_PROT_EN_CLR ,
MT8192_TOP_AXI_PROT_EN_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_2_SET ,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_IPE ] = {
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. name = " ipe " ,
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. sta_mask = BIT ( 14 ) ,
. ctl_offs = 0x0338 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_IPE ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_ISP ] = {
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. name = " isp " ,
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. sta_mask = BIT ( 12 ) ,
. ctl_offs = 0x0330 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_2_ISP ,
MT8192_TOP_AXI_PROT_EN_MM_2_SET ,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_2_SET ,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_ISP2 ] = {
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. name = " isp2 " ,
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. sta_mask = BIT ( 13 ) ,
. ctl_offs = 0x0334 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_ISP2 ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_MDP ] = {
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. name = " mdp " ,
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. sta_mask = BIT ( 19 ) ,
. ctl_offs = 0x034c ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_2_MDP ,
MT8192_TOP_AXI_PROT_EN_MM_2_SET ,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_2_SET ,
MT8192_TOP_AXI_PROT_EN_MM_2_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_2_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_VENC ] = {
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. name = " venc " ,
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. sta_mask = BIT ( 17 ) ,
. ctl_offs = 0x0344 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_VENC ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_VDEC ] = {
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. name = " vdec " ,
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. sta_mask = BIT ( 15 ) ,
. ctl_offs = 0x033c ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_VDEC ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_VDEC2 ] = {
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. name = " vdec2 " ,
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. sta_mask = BIT ( 16 ) ,
. ctl_offs = 0x0340 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_CAM ] = {
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. name = " cam " ,
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. sta_mask = BIT ( 23 ) ,
. ctl_offs = 0x035c ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
. bp_infracfg = {
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_2_CAM ,
MT8192_TOP_AXI_PROT_EN_2_SET ,
MT8192_TOP_AXI_PROT_EN_2_CLR ,
MT8192_TOP_AXI_PROT_EN_2_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_CAM ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_1_CAM ,
MT8192_TOP_AXI_PROT_EN_1_SET ,
MT8192_TOP_AXI_PROT_EN_1_CLR ,
MT8192_TOP_AXI_PROT_EN_1_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND ,
MT8192_TOP_AXI_PROT_EN_MM_SET ,
MT8192_TOP_AXI_PROT_EN_MM_CLR ,
MT8192_TOP_AXI_PROT_EN_MM_STA1 ) ,
BUS_PROT_WR ( MT8192_TOP_AXI_PROT_EN_VDNR_CAM ,
MT8192_TOP_AXI_PROT_EN_VDNR_SET ,
MT8192_TOP_AXI_PROT_EN_VDNR_CLR ,
MT8192_TOP_AXI_PROT_EN_VDNR_STA1 ) ,
} ,
} ,
[ MT8192_POWER_DOMAIN_CAM_RAWA ] = {
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. name = " cam_rawa " ,
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. sta_mask = BIT ( 24 ) ,
. ctl_offs = 0x0360 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_CAM_RAWB ] = {
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. name = " cam_rawb " ,
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. sta_mask = BIT ( 25 ) ,
. ctl_offs = 0x0364 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
[ MT8192_POWER_DOMAIN_CAM_RAWC ] = {
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. name = " cam_rawc " ,
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. sta_mask = BIT ( 26 ) ,
. ctl_offs = 0x0368 ,
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. pwr_sta_offs = 0x016c ,
. pwr_sta2nd_offs = 0x0170 ,
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. sram_pdn_bits = GENMASK ( 8 , 8 ) ,
. sram_pdn_ack_bits = GENMASK ( 12 , 12 ) ,
} ,
} ;
static const struct scpsys_soc_data mt8192_scpsys_data = {
. domains_data = scpsys_domain_data_mt8192 ,
. num_domains = ARRAY_SIZE ( scpsys_domain_data_mt8192 ) ,
} ;
# endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */