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/* SPDX-License-Identifier: GPL-2.0-only */
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/ *
*
* Copyright S U S E L i n u x P r o d u c t s G m b H 2 0 0 9
*
* Authors : Alexander G r a f < a g r a f @suse.de>
* /
/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* *
* Entry c o d e *
* *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /
.macro LOAD_GUEST_SEGMENTS
/ * Required s t a t e :
*
* MSR = ~ I R | D R
* R1 = h o s t R 1
* R2 = h o s t R 2
* R3 = s h a d o w v c p u
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* all o t h e r v o l a t i l e G P R S = f r e e e x c e p t R 4 , R 6
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* SVCPU[ C R ] = g u e s t C R
* SVCPU[ X E R ] = g u e s t X E R
* SVCPU[ C T R ] = g u e s t C T R
* SVCPU[ L R ] = g u e s t L R
* /
# define X C H G _ S R ( n ) l w z r9 , ( S V C P U _ S R + ( n * 4 ) ) ( r3 ) ; \
mtsr n , r9
XCHG_ S R ( 0 )
XCHG_ S R ( 1 )
XCHG_ S R ( 2 )
XCHG_ S R ( 3 )
XCHG_ S R ( 4 )
XCHG_ S R ( 5 )
XCHG_ S R ( 6 )
XCHG_ S R ( 7 )
XCHG_ S R ( 8 )
XCHG_ S R ( 9 )
XCHG_ S R ( 1 0 )
XCHG_ S R ( 1 1 )
XCHG_ S R ( 1 2 )
XCHG_ S R ( 1 3 )
XCHG_ S R ( 1 4 )
XCHG_ S R ( 1 5 )
/* Clear BATs. */
# define K V M _ K I L L _ B A T ( n , r e g ) \
mtspr S P R N _ I B A T ## n # # U , r e g ; \
mtspr S P R N _ I B A T ## n # # L , r e g ; \
mtspr S P R N _ D B A T ## n # # U , r e g ; \
mtspr S P R N _ D B A T ## n # # L , r e g ; \
li r9 , 0
KVM_ K I L L _ B A T ( 0 , r9 )
KVM_ K I L L _ B A T ( 1 , r9 )
KVM_ K I L L _ B A T ( 2 , r9 )
KVM_ K I L L _ B A T ( 3 , r9 )
.endm
/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* *
* Exit c o d e *
* *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /
.macro LOAD_HOST_SEGMENTS
/ * Register u s a g e a t t h i s p o i n t :
*
* R1 = h o s t R 1
* R2 = h o s t R 2
* R1 2 = e x i t h a n d l e r i d
* R1 3 = s h a d o w v c p u - S H A D O W _ V C P U _ O F F
* SVCPU. * = g u e s t *
* SVCPU[ C R ] = g u e s t C R
* SVCPU[ X E R ] = g u e s t X E R
* SVCPU[ C T R ] = g u e s t C T R
* SVCPU[ L R ] = g u e s t L R
*
* /
/* Restore BATs */
/ * We o n l y o v e r w r i t e t h e u p p e r p a r t , s o w e o n l y r e s t o r e e
the u p p e r p a r t . * /
# define K V M _ L O A D _ B A T ( n , r e g , R A , R B ) \
lwz R A ,( n * 1 6 ) + 0 ( r e g ) ; \
lwz R B ,( n * 1 6 ) + 4 ( r e g ) ; \
mtspr S P R N _ I B A T ## n # # U , R A ; \
mtspr S P R N _ I B A T ## n # # L , R B ; \
lwz R A ,( n * 1 6 ) + 8 ( r e g ) ; \
lwz R B ,( n * 1 6 ) + 1 2 ( r e g ) ; \
mtspr S P R N _ D B A T ## n # # U , R A ; \
mtspr S P R N _ D B A T ## n # # L , R B ; \
lis r9 , B A T S @ha
addi r9 , r9 , B A T S @l
tophys( r9 , r9 )
KVM_ L O A D _ B A T ( 0 , r9 , r10 , r11 )
KVM_ L O A D _ B A T ( 1 , r9 , r10 , r11 )
KVM_ L O A D _ B A T ( 2 , r9 , r10 , r11 )
KVM_ L O A D _ B A T ( 3 , r9 , r10 , r11 )
/* Restore Segment Registers */
/* 0xc - 0xf */
li r0 , 4
mtctr r0
LOAD_ R E G _ I M M E D I A T E ( r3 , 0 x20 0 0 0 0 0 0 | ( 0 x11 1 * 0 x c ) )
lis r4 , 0 x c00 0
3 : mtsrin r3 , r4
addi r3 , r3 , 0 x11 1 / * i n c r e m e n t V S I D * /
addis r4 , r4 , 0 x10 0 0 / * a d d r e s s o f n e x t s e g m e n t * /
bdnz 3 b
/* 0x0 - 0xb */
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/* switch_mmu_context() needs paging, let's enable it */
mfmsr r9
ori r11 , r9 , M S R _ D R
mtmsr r11
sync
/* switch_mmu_context() clobbers r12, rescue it */
SAVE_ G P R ( 1 2 , r1 )
/* Calling switch_mmu_context(<inv>, current->mm, <inv>); */
lwz r4 , M M ( r2 )
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bl s w i t c h _ m m u _ c o n t e x t
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/* restore r12 */
REST_ G P R ( 1 2 , r1 )
/* Disable paging again */
mfmsr r9
li r6 , M S R _ D R
andc r9 , r9 , r6
mtmsr r9
sync
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.endm