linux/drivers/net/dsa/mv88e6xxx/smi.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Marvell 88E6xxx System Management Interface (SMI) support
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
 */

#ifndef _MV88E6XXX_SMI_H
#define _MV88E6XXX_SMI_H

#include "chip.h"

/* Offset 0x00: SMI Command Register */
#define MV88E6XXX_SMI_CMD			0x00
#define MV88E6XXX_SMI_CMD_BUSY			0x8000
#define MV88E6XXX_SMI_CMD_MODE_MASK		0x1000
#define MV88E6XXX_SMI_CMD_MODE_45		0x0000
#define MV88E6XXX_SMI_CMD_MODE_22		0x1000
#define MV88E6XXX_SMI_CMD_OP_MASK		0x0c00
#define MV88E6XXX_SMI_CMD_OP_22_WRITE		0x0400
#define MV88E6XXX_SMI_CMD_OP_22_READ		0x0800
#define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR	0x0000
#define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA	0x0400
#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA	0x0800
#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC	0x0c00
#define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK		0x003e
#define MV88E6XXX_SMI_CMD_REG_ADDR_MASK		0x001f

/* Offset 0x01: SMI Data Register */
#define MV88E6XXX_SMI_DATA			0x01

int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
		       struct mii_bus *bus, int sw_addr);

static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
				     int dev, int reg, u16 *data)
{
	if (chip->smi_ops && chip->smi_ops->read)
		return chip->smi_ops->read(chip, dev, reg, data);

	return -EOPNOTSUPP;
}

static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
				      int dev, int reg, u16 data)
{
	if (chip->smi_ops && chip->smi_ops->write)
		return chip->smi_ops->write(chip, dev, reg, data);

	return -EOPNOTSUPP;
}

#endif /* _MV88E6XXX_SMI_H */
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-27 08:55:01 +02:00			`/* SPDX-License-Identifier: GPL-2.0-or-later */`
net: dsa: mv88e6xxx: refine SMI support The Marvell SOHO switches have several ways to access the internal registers. One of them being the System Management Interface (SMI), using the MDC and MDIO pins, with direct and indirect variants. In preparation for adding support for other register accesses, move the SMI code into its own files. At the same time, refine the code to make it clear that the indirect variant is implemented using the direct variant accessing only two registers for command and data. Signed-off-by: Vivien Didelot <vivien.didelot@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> 2019-05-03 19:28:22 -04:00			`/*`
			`* Marvell 88E6xxx System Management Interface (SMI) support`
			`*`
			`* Copyright (c) 2008 Marvell Semiconductor`
			`*`
			`* Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>`
			`*/`

			`#ifndef _MV88E6XXX_SMI_H`
			`#define _MV88E6XXX_SMI_H`

			`#include "chip.h"`

			`/* Offset 0x00: SMI Command Register */`
			`#define MV88E6XXX_SMI_CMD 0x00`
			`#define MV88E6XXX_SMI_CMD_BUSY 0x8000`
			`#define MV88E6XXX_SMI_CMD_MODE_MASK 0x1000`
			`#define MV88E6XXX_SMI_CMD_MODE_45 0x0000`
			`#define MV88E6XXX_SMI_CMD_MODE_22 0x1000`
			`#define MV88E6XXX_SMI_CMD_OP_MASK 0x0c00`
			`#define MV88E6XXX_SMI_CMD_OP_22_WRITE 0x0400`
			`#define MV88E6XXX_SMI_CMD_OP_22_READ 0x0800`
			`#define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR 0x0000`
			`#define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA 0x0400`
			`#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA 0x0800`
			`#define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC 0x0c00`
			`#define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK 0x003e`
			`#define MV88E6XXX_SMI_CMD_REG_ADDR_MASK 0x001f`

			`/* Offset 0x01: SMI Data Register */`
			`#define MV88E6XXX_SMI_DATA 0x01`

			`int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,`
			`struct mii_bus *bus, int sw_addr);`

			`static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,`
			`int dev, int reg, u16 *data)`
			`{`
			`if (chip->smi_ops && chip->smi_ops->read)`
			`return chip->smi_ops->read(chip, dev, reg, data);`

			`return -EOPNOTSUPP;`
			`}`

			`static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,`
			`int dev, int reg, u16 data)`
			`{`
			`if (chip->smi_ops && chip->smi_ops->write)`
			`return chip->smi_ops->write(chip, dev, reg, data);`

			`return -EOPNOTSUPP;`
			`}`

			`#endif /* _MV88E6XXX_SMI_H */`