2019-05-19 15:07:45 +03:00
# SPDX-License-Identifier: GPL-2.0-only
2018-09-05 09:25:06 +03:00
config CSKY
def_bool y
32-bit userspace ABI: introduce ARCH_32BIT_OFF_T config option
All new 32-bit architectures should have 64-bit userspace off_t type, but
existing architectures has 32-bit ones.
To enforce the rule, new config option is added to arch/Kconfig that defaults
ARCH_32BIT_OFF_T to be disabled for new 32-bit architectures. All existing
32-bit architectures enable it explicitly.
New option affects force_o_largefile() behaviour. Namely, if userspace
off_t is 64-bits long, we have no reason to reject user to open big files.
Note that even if architectures has only 64-bit off_t in the kernel
(arc, c6x, h8300, hexagon, nios2, openrisc, and unicore32),
a libc may use 32-bit off_t, and therefore want to limit the file size
to 4GB unless specified differently in the open flags.
Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Yury Norov <ynorov@marvell.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-05-16 11:18:49 +03:00
select ARCH_32BIT_OFF_T
2019-03-25 17:44:06 +03:00
select ARCH_HAS_DMA_PREP_COHERENT
2020-03-10 18:32:56 +03:00
select ARCH_HAS_GCOV_PROFILE_ALL
2018-09-05 09:25:06 +03:00
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_USE_BUILTIN_BSWAP
2020-12-20 11:12:45 +03:00
select ARCH_USE_QUEUED_RWLOCKS
2022-07-24 04:32:34 +03:00
select ARCH_USE_QUEUED_SPINLOCKS
2022-10-22 04:43:40 +03:00
select ARCH_HAS_CURRENT_STACK_POINTER
2022-07-24 05:52:17 +03:00
select ARCH_INLINE_READ_LOCK if !PREEMPTION
select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
2021-09-17 07:38:36 +03:00
select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
2020-07-30 15:44:12 +03:00
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
2018-09-05 09:25:06 +03:00
select COMMON_CLK
select CLKSRC_MMIO
2019-05-10 07:57:27 +03:00
select CSKY_MPINTC if CPU_CK860
select CSKY_MP_TIMER if CPU_CK860
select CSKY_APB_INTC
2018-11-04 19:47:44 +03:00
select DMA_DIRECT_REMAP
2018-09-05 09:25:06 +03:00
select IRQ_DOMAIN
select DW_APB_TIMER_OF
2019-08-13 12:41:57 +03:00
select GENERIC_IOREMAP
2018-09-05 09:25:06 +03:00
select GENERIC_LIB_ASHLDI3
select GENERIC_LIB_ASHRDI3
select GENERIC_LIB_LSHRDI3
select GENERIC_LIB_MULDI3
select GENERIC_LIB_CMPDI2
select GENERIC_LIB_UCMPDI2
select GENERIC_ALLOCATOR
select GENERIC_ATOMIC64
select GENERIC_CPU_DEVICES
select GENERIC_IRQ_CHIP
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_MULTI_HANDLER
select GENERIC_SCHED_CLOCK
select GENERIC_SMP_IDLE_THREAD
2021-01-17 18:38:18 +03:00
select GENERIC_TIME_VSYSCALL
select GENERIC_VDSO_32
select GENERIC_GETTIMEOFDAY
2019-05-10 07:57:27 +03:00
select GX6605S_TIMER if CPU_CK610
2018-09-05 09:25:06 +03:00
select HAVE_ARCH_TRACEHOOK
2019-03-20 13:27:27 +03:00
select HAVE_ARCH_AUDITSYSCALL
2022-04-18 16:01:54 +03:00
select HAVE_ARCH_JUMP_LABEL if !CPU_CK610
select HAVE_ARCH_JUMP_LABEL_RELATIVE
2020-07-30 15:44:12 +03:00
select HAVE_ARCH_MMAP_RND_BITS
2020-05-26 11:11:52 +03:00
select HAVE_ARCH_SECCOMP_FILTER
2022-06-08 17:40:24 +03:00
select HAVE_CONTEXT_TRACKING_USER
2020-07-31 12:13:51 +03:00
select HAVE_VIRT_CPU_ACCOUNTING_GEN
2020-05-13 10:15:25 +03:00
select HAVE_DEBUG_BUGVERBOSE
2020-12-24 06:34:43 +03:00
select HAVE_DEBUG_KMEMLEAK
2019-03-01 03:50:36 +03:00
select HAVE_DYNAMIC_FTRACE
2020-02-18 15:27:39 +03:00
select HAVE_DYNAMIC_FTRACE_WITH_REGS
2021-01-17 18:38:18 +03:00
select HAVE_GENERIC_VDSO
2018-12-09 09:29:59 +03:00
select HAVE_FUNCTION_TRACER
2018-12-15 16:04:27 +03:00
select HAVE_FUNCTION_GRAPH_TRACER
2020-07-28 19:30:46 +03:00
select HAVE_FUNCTION_ERROR_INJECTION
2019-03-01 03:50:36 +03:00
select HAVE_FTRACE_MCOUNT_RECORD
2018-09-05 09:25:06 +03:00
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZO
select HAVE_KERNEL_LZMA
2020-04-01 04:17:02 +03:00
select HAVE_KPROBES if !CPU_CK610
select HAVE_KPROBES_ON_FTRACE if !CPU_CK610
select HAVE_KRETPROBES if !CPU_CK610
2019-01-02 17:09:25 +03:00
select HAVE_PERF_EVENTS
2019-04-15 12:17:29 +03:00
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
2018-09-05 09:25:06 +03:00
select HAVE_DMA_CONTIGUOUS
2019-12-17 09:57:22 +03:00
select HAVE_REGS_AND_STACK_ACCESS_API
2019-10-11 05:56:55 +03:00
select HAVE_STACKPROTECTOR
2019-03-20 13:27:27 +03:00
select HAVE_SYSCALL_TRACEPOINTS
2023-05-13 00:07:35 +03:00
select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
mm/fault: convert remaining simple cases to lock_mm_and_find_vma()
This does the simple pattern conversion of alpha, arc, csky, hexagon,
loongarch, nios2, sh, sparc32, and xtensa to the lock_mm_and_find_vma()
helper. They all have the regular fault handling pattern without odd
special cases.
The remaining architectures all have something that keeps us from a
straightforward conversion: ia64 and parisc have stacks that can grow
both up as well as down (and ia64 has special address region checks).
And m68k, microblaze, openrisc, sparc64, and um end up having extra
rules about only expanding the stack down a limited amount below the
user space stack pointer. That is something that x86 used to do too
(long long ago), and it probably could just be skipped, but it still
makes the conversion less than trivial.
Note that this conversion was done manually and with the exception of
alpha without any build testing, because I have a fairly limited cross-
building environment. The cases are all simple, and I went through the
changes several times, but...
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2023-06-24 20:55:38 +03:00
select LOCK_MM_AND_FIND_VMA
2018-09-05 09:25:06 +03:00
select MAY_HAVE_SPARSE_IRQ
select MODULES_USE_ELF_RELA if MODULES
select OF
select OF_EARLY_FLATTREE
2019-01-02 17:09:25 +03:00
select PERF_USE_VMALLOC if CPU_CK610
2018-09-05 09:25:06 +03:00
select RTC_LIB
select TIMER_OF
2020-01-27 05:56:21 +03:00
select GENERIC_PCI_IOMAP
select HAVE_PCI
select PCI_DOMAINS_GENERIC if PCI
select PCI_SYSCALL if PCI
select PCI_MSI if PCI
2021-07-31 08:22:32 +03:00
select TRACE_IRQFLAGS_SUPPORT
2018-09-05 09:25:06 +03:00
2020-04-02 14:39:42 +03:00
config LOCKDEP_SUPPORT
def_bool y
2020-04-02 14:52:27 +03:00
config ARCH_SUPPORTS_UPROBES
def_bool y if !CPU_CK610
2018-09-05 09:25:06 +03:00
config CPU_HAS_CACHEV2
bool
config CPU_HAS_FPUV2
bool
config CPU_HAS_HILO
bool
config CPU_HAS_TLBI
bool
config CPU_HAS_LDSTEX
bool
help
2020-02-01 04:52:30 +03:00
For SMP, CPU needs "ldex&stex" instructions for atomic operations.
2018-09-05 09:25:06 +03:00
config CPU_NEED_TLBSYNC
bool
config CPU_NEED_SOFTALIGN
bool
config CPU_NO_USER_BKPT
bool
help
For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because
abiv2 is 16/32bit instruction set and "trap 1" is 32bit.
So we need a 16bit instruction as user space bkpt, and it will cause an illegal
instruction exception.
In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
config GENERIC_CALIBRATE_DELAY
def_bool y
config GENERIC_CSUM
def_bool y
config GENERIC_HWEIGHT
def_bool y
config MMU
def_bool y
2018-12-09 09:18:05 +03:00
config STACKTRACE_SUPPORT
def_bool y
2018-09-05 09:25:06 +03:00
config TIME_LOW_RES
def_bool y
config CPU_ASID_BITS
int
default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810)
default "12" if (CPU_CK860)
config L1_CACHE_SHIFT
int
default "4" if (CPU_CK610)
default "5" if (CPU_CK807 || CPU_CK810)
default "6" if (CPU_CK860)
2020-07-30 15:44:12 +03:00
config ARCH_MMAP_RND_BITS_MIN
default 8
# max bits determined by the following formula:
# VA_BITS - PAGE_SHIFT - 3
config ARCH_MMAP_RND_BITS_MAX
default 17
2018-09-05 09:25:06 +03:00
menu "Processor type and features"
choice
prompt "CPU MODEL"
default CPU_CK807
config CPU_CK610
bool "CSKY CPU ck610"
select CPU_NEED_TLBSYNC
select CPU_NEED_SOFTALIGN
select CPU_NO_USER_BKPT
config CPU_CK810
bool "CSKY CPU ck810"
select CPU_HAS_HILO
select CPU_NEED_TLBSYNC
config CPU_CK807
bool "CSKY CPU ck807"
select CPU_HAS_HILO
config CPU_CK860
bool "CSKY CPU ck860"
select CPU_HAS_TLBI
select CPU_HAS_CACHEV2
select CPU_HAS_LDSTEX
select CPU_HAS_FPUV2
endchoice
2019-01-02 17:09:25 +03:00
choice
2020-09-07 09:20:18 +03:00
prompt "PAGE OFFSET"
default PAGE_OFFSET_80000000
config PAGE_OFFSET_80000000
bool "PAGE OFFSET 2G (user:kernel = 2:2)"
config PAGE_OFFSET_A0000000
bool "PAGE OFFSET 2.5G (user:kernel = 2.5:1.5)"
endchoice
config PAGE_OFFSET
hex
default 0x80000000 if PAGE_OFFSET_80000000
default 0xa0000000 if PAGE_OFFSET_A0000000
choice
2019-01-02 17:09:25 +03:00
prompt "C-SKY PMU type"
depends on PERF_EVENTS
depends on CPU_CK807 || CPU_CK810 || CPU_CK860
config CPU_PMU_NONE
bool "None"
config CSKY_PMU_V1
bool "Performance Monitoring Unit Ver.1"
endchoice
2018-09-05 09:25:06 +03:00
choice
prompt "Power Manager Instruction (wait/doze/stop)"
default CPU_PM_NONE
config CPU_PM_NONE
bool "None"
config CPU_PM_WAIT
bool "wait"
config CPU_PM_DOZE
bool "doze"
config CPU_PM_STOP
bool "stop"
endchoice
csky: Tightly-Coupled Memory or Sram support
The implementation are not only used by TCM but also used by sram on
SOC bus. It follow existed linux tcm software interface, so that old
tcm application codes could be re-used directly.
Software interface list in asm/tcm.h:
- Variables/Const: __tcmdata, __tcmconst
- Functions: __tcmfunc, __tcmlocalfunc
- Malloc/Free: tcm_alloc, tcm_free
In linux menuconfig:
- Choose a TCM contain instrctions + data or separated in ITCM/DTCM.
- Determine TCM_BASE (DTCM_BASE) in phyiscal address.
- Determine size of TCM or ITCM(DTCM) in page counts.
Here is hello tcm example from Documentation/arm/tcm.rst which could
be directly used:
/* Uninitialized data */
static u32 __tcmdata tcmvar;
/* Initialized data */
static u32 __tcmdata tcmassigned = 0x2BADBABEU;
/* Constant */
static const u32 __tcmconst tcmconst = 0xCAFEBABEU;
static void __tcmlocalfunc tcm_to_tcm(void)
{
int i;
for (i = 0; i < 100; i++)
tcmvar ++;
}
static void __tcmfunc hello_tcm(void)
{
/* Some abstract code that runs in ITCM */
int i;
for (i = 0; i < 100; i++) {
tcmvar ++;
}
tcm_to_tcm();
}
static void __init test_tcm(void)
{
u32 *tcmem;
int i;
hello_tcm();
printk("Hello TCM executed from ITCM RAM\n");
printk("TCM variable from testrun: %u @ %p\n", tcmvar, &tcmvar);
tcmvar = 0xDEADBEEFU;
printk("TCM variable: 0x%x @ %p\n", tcmvar, &tcmvar);
printk("TCM assigned variable: 0x%x @ %p\n", tcmassigned, &tcmassigned);
printk("TCM constant: 0x%x @ %p\n", tcmconst, &tcmconst);
/* Allocate some TCM memory from the pool */
tcmem = tcm_alloc(20);
if (tcmem) {
printk("TCM Allocated 20 bytes of TCM @ %p\n", tcmem);
tcmem[0] = 0xDEADBEEFU;
tcmem[1] = 0x2BADBABEU;
tcmem[2] = 0xCAFEBABEU;
tcmem[3] = 0xDEADBEEFU;
tcmem[4] = 0x2BADBABEU;
for (i = 0; i < 5; i++)
printk("TCM tcmem[%d] = %08x\n", i, tcmem[i]);
tcm_free(tcmem, 20);
}
}
TODO:
- Separate fixup mapping from highmem
- Support abiv1
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2019-11-27 03:44:33 +03:00
menuconfig HAVE_TCM
bool "Tightly-Coupled/Sram Memory"
2021-09-17 07:38:38 +03:00
depends on !COMPILE_TEST
csky: Tightly-Coupled Memory or Sram support
The implementation are not only used by TCM but also used by sram on
SOC bus. It follow existed linux tcm software interface, so that old
tcm application codes could be re-used directly.
Software interface list in asm/tcm.h:
- Variables/Const: __tcmdata, __tcmconst
- Functions: __tcmfunc, __tcmlocalfunc
- Malloc/Free: tcm_alloc, tcm_free
In linux menuconfig:
- Choose a TCM contain instrctions + data or separated in ITCM/DTCM.
- Determine TCM_BASE (DTCM_BASE) in phyiscal address.
- Determine size of TCM or ITCM(DTCM) in page counts.
Here is hello tcm example from Documentation/arm/tcm.rst which could
be directly used:
/* Uninitialized data */
static u32 __tcmdata tcmvar;
/* Initialized data */
static u32 __tcmdata tcmassigned = 0x2BADBABEU;
/* Constant */
static const u32 __tcmconst tcmconst = 0xCAFEBABEU;
static void __tcmlocalfunc tcm_to_tcm(void)
{
int i;
for (i = 0; i < 100; i++)
tcmvar ++;
}
static void __tcmfunc hello_tcm(void)
{
/* Some abstract code that runs in ITCM */
int i;
for (i = 0; i < 100; i++) {
tcmvar ++;
}
tcm_to_tcm();
}
static void __init test_tcm(void)
{
u32 *tcmem;
int i;
hello_tcm();
printk("Hello TCM executed from ITCM RAM\n");
printk("TCM variable from testrun: %u @ %p\n", tcmvar, &tcmvar);
tcmvar = 0xDEADBEEFU;
printk("TCM variable: 0x%x @ %p\n", tcmvar, &tcmvar);
printk("TCM assigned variable: 0x%x @ %p\n", tcmassigned, &tcmassigned);
printk("TCM constant: 0x%x @ %p\n", tcmconst, &tcmconst);
/* Allocate some TCM memory from the pool */
tcmem = tcm_alloc(20);
if (tcmem) {
printk("TCM Allocated 20 bytes of TCM @ %p\n", tcmem);
tcmem[0] = 0xDEADBEEFU;
tcmem[1] = 0x2BADBABEU;
tcmem[2] = 0xCAFEBABEU;
tcmem[3] = 0xDEADBEEFU;
tcmem[4] = 0x2BADBABEU;
for (i = 0; i < 5; i++)
printk("TCM tcmem[%d] = %08x\n", i, tcmem[i]);
tcm_free(tcmem, 20);
}
}
TODO:
- Separate fixup mapping from highmem
- Support abiv1
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2019-11-27 03:44:33 +03:00
help
2022-10-07 23:16:48 +03:00
The implementation are not only used by TCM (Tightly-Coupled Memory)
csky: Tightly-Coupled Memory or Sram support
The implementation are not only used by TCM but also used by sram on
SOC bus. It follow existed linux tcm software interface, so that old
tcm application codes could be re-used directly.
Software interface list in asm/tcm.h:
- Variables/Const: __tcmdata, __tcmconst
- Functions: __tcmfunc, __tcmlocalfunc
- Malloc/Free: tcm_alloc, tcm_free
In linux menuconfig:
- Choose a TCM contain instrctions + data or separated in ITCM/DTCM.
- Determine TCM_BASE (DTCM_BASE) in phyiscal address.
- Determine size of TCM or ITCM(DTCM) in page counts.
Here is hello tcm example from Documentation/arm/tcm.rst which could
be directly used:
/* Uninitialized data */
static u32 __tcmdata tcmvar;
/* Initialized data */
static u32 __tcmdata tcmassigned = 0x2BADBABEU;
/* Constant */
static const u32 __tcmconst tcmconst = 0xCAFEBABEU;
static void __tcmlocalfunc tcm_to_tcm(void)
{
int i;
for (i = 0; i < 100; i++)
tcmvar ++;
}
static void __tcmfunc hello_tcm(void)
{
/* Some abstract code that runs in ITCM */
int i;
for (i = 0; i < 100; i++) {
tcmvar ++;
}
tcm_to_tcm();
}
static void __init test_tcm(void)
{
u32 *tcmem;
int i;
hello_tcm();
printk("Hello TCM executed from ITCM RAM\n");
printk("TCM variable from testrun: %u @ %p\n", tcmvar, &tcmvar);
tcmvar = 0xDEADBEEFU;
printk("TCM variable: 0x%x @ %p\n", tcmvar, &tcmvar);
printk("TCM assigned variable: 0x%x @ %p\n", tcmassigned, &tcmassigned);
printk("TCM constant: 0x%x @ %p\n", tcmconst, &tcmconst);
/* Allocate some TCM memory from the pool */
tcmem = tcm_alloc(20);
if (tcmem) {
printk("TCM Allocated 20 bytes of TCM @ %p\n", tcmem);
tcmem[0] = 0xDEADBEEFU;
tcmem[1] = 0x2BADBABEU;
tcmem[2] = 0xCAFEBABEU;
tcmem[3] = 0xDEADBEEFU;
tcmem[4] = 0x2BADBABEU;
for (i = 0; i < 5; i++)
printk("TCM tcmem[%d] = %08x\n", i, tcmem[i]);
tcm_free(tcmem, 20);
}
}
TODO:
- Separate fixup mapping from highmem
- Support abiv1
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2019-11-27 03:44:33 +03:00
but also used by sram on SOC bus. It follow existed linux tcm
software interface, so that old tcm application codes could be
re-used directly.
if HAVE_TCM
config ITCM_RAM_BASE
hex "ITCM ram base"
default 0xffffffff
config ITCM_NR_PAGES
int "Page count of ITCM size: NR*4KB"
range 1 256
default 32
config HAVE_DTCM
bool "DTCM Support"
config DTCM_RAM_BASE
hex "DTCM ram base"
depends on HAVE_DTCM
default 0xffffffff
config DTCM_NR_PAGES
int "Page count of DTCM size: NR*4KB"
depends on HAVE_DTCM
range 1 256
default 32
endif
2018-09-05 09:25:06 +03:00
config CPU_HAS_VDSP
bool "CPU has VDSP coprocessor"
depends on CPU_HAS_FPU && CPU_HAS_FPUV2
config CPU_HAS_FPU
bool "CPU has FPU coprocessor"
depends on CPU_CK807 || CPU_CK810 || CPU_CK860
2020-01-22 06:15:14 +03:00
config CPU_HAS_ICACHE_INS
bool "CPU has Icache invalidate instructions"
depends on CPU_HAS_CACHEV2
2018-09-05 09:25:06 +03:00
config CPU_HAS_TEE
bool "CPU has Trusted Execution Environment"
depends on CPU_CK810
config SMP
bool "Symmetric Multi-Processing (SMP) support for C-SKY"
depends on CPU_CK860
default n
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
depends on SMP
2020-07-30 16:12:00 +03:00
default "4"
2018-09-05 09:25:06 +03:00
config HIGHMEM
bool "High Memory Support"
depends on !CPU_CK610
2020-11-03 12:27:23 +03:00
select KMAP_LOCAL
2018-09-05 09:25:06 +03:00
default y
2021-04-17 01:46:03 +03:00
config DRAM_BASE
2018-09-05 09:25:06 +03:00
hex "DRAM start addr (the same with memory-section in dts)"
default 0x0
2018-12-19 14:56:14 +03:00
config HOTPLUG_CPU
bool "Support for hot-pluggable CPUs"
select GENERIC_IRQ_MIGRATION
depends on SMP
help
Say Y here to allow turning CPUs off and on. CPUs can be
controlled through /sys/devices/system/cpu/cpu1/hotplug/target.
Say N if you want to disable CPU hotplug.
2022-03-30 15:07:14 +03:00
config HAVE_EFFICIENT_UNALIGNED_STRING_OPS
bool "Enable EFFICIENT_UNALIGNED_STRING_OPS for abiv2"
depends on CPU_CK807 || CPU_CK810 || CPU_CK860
help
Say Y here to enable EFFICIENT_UNALIGNED_STRING_OPS. Some CPU models could
deal with unaligned access by hardware.
2018-09-05 09:25:06 +03:00
endmenu
2020-01-11 08:44:32 +03:00
source "arch/csky/Kconfig.platforms"
2018-09-05 09:25:06 +03:00
source "kernel/Kconfig.hz"