blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
/ *
2008-05-07 07:41:26 +04:00
* Copyright 2 0 0 4 - 2 0 0 8 A n a l o g D e v i c e s I n c .
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
*
2008-05-07 07:41:26 +04:00
* Licensed u n d e r t h e G P L - 2 o r l a t e r .
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
* /
# include < l i n u x / l i n k a g e . h >
# include < a s m / b l a c k f i n . h >
2008-08-27 06:51:02 +04:00
# include < m a c h / i r q . h >
2008-07-19 12:57:32 +04:00
# include < a s m / d p m c . h >
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
.section .l1 .text
ENTRY( _ s l e e p _ m o d e )
[ - - SP] = ( R 7 : 0 , P 5 : 0 ) ;
[ - - SP] = R E T S ;
call _ s e t _ s i c _ i w r ;
P0 . H = h i ( P L L _ C T L ) ;
P0 . L = l o ( P L L _ C T L ) ;
R1 = W [ P 0 ] ( z ) ;
BITSET ( R 1 , 3 ) ;
W[ P 0 ] = R 1 . L ;
CLI R 2 ;
SSYNC;
IDLE;
STI R 2 ;
call _ t e s t _ p l l _ l o c k e d ;
R0 = I W R _ E N A B L E ( 0 ) ;
2008-02-08 23:12:37 +03:00
R1 = I W R _ D I S A B L E _ A L L ;
R2 = I W R _ D I S A B L E _ A L L ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
call _ s e t _ s i c _ i w r ;
P0 . H = h i ( P L L _ C T L ) ;
P0 . L = l o ( P L L _ C T L ) ;
R7 = w [ p0 ] ( z ) ;
BITCLR ( R 7 , 3 ) ;
BITCLR ( R 7 , 5 ) ;
w[ p0 ] = R 7 . L ;
IDLE;
call _ t e s t _ p l l _ l o c k e d ;
RETS = [ S P + + ] ;
( R7 : 0 , P5 : 0 ) = [ SP+ + ] ;
RTS;
2008-07-16 13:07:26 +04:00
ENDPROC( _ s l e e p _ m o d e )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
ENTRY( _ h i b e r n a t e _ m o d e )
[ - - SP] = ( R 7 : 0 , P 5 : 0 ) ;
[ - - SP] = R E T S ;
2008-07-19 12:57:32 +04:00
R3 = R 0 ;
R0 = I W R _ D I S A B L E _ A L L ;
R1 = I W R _ D I S A B L E _ A L L ;
R2 = I W R _ D I S A B L E _ A L L ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
call _ s e t _ s i c _ i w r ;
2008-07-19 12:57:32 +04:00
call _ s e t _ d r a m _ s r f s ;
SSYNC;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( V R _ C T L ) ;
P0 . L = l o ( V R _ C T L ) ;
2008-07-19 12:57:32 +04:00
W[ P 0 ] = R 3 . L ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
CLI R 2 ;
IDLE;
2008-07-19 12:57:32 +04:00
.Lforever :
jump . L f o r e v e r ;
2008-07-16 13:07:26 +04:00
ENDPROC( _ h i b e r n a t e _ m o d e )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
ENTRY( _ s l e e p _ d e e p e r )
[ - - SP] = ( R 7 : 0 , P 5 : 0 ) ;
[ - - SP] = R E T S ;
CLI R 4 ;
P3 = R 0 ;
2008-02-08 23:12:37 +03:00
P4 = R 1 ;
P5 = R 2 ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
R0 = I W R _ E N A B L E ( 0 ) ;
2008-02-08 23:12:37 +03:00
R1 = I W R _ D I S A B L E _ A L L ;
R2 = I W R _ D I S A B L E _ A L L ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
call _ s e t _ s i c _ i w r ;
2008-01-11 12:21:41 +03:00
call _ s e t _ d r a m _ s r f s ; /* Set SDRAM Self Refresh */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( P L L _ D I V ) ;
P0 . L = l o ( P L L _ D I V ) ;
R6 = W [ P 0 ] ( z ) ;
R0 . L = 0 x F ;
2008-01-11 12:21:41 +03:00
W[ P 0 ] = R 0 . l ; /* Set Max VCO to SCLK divider */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( P L L _ C T L ) ;
P0 . L = l o ( P L L _ C T L ) ;
R5 = W [ P 0 ] ( z ) ;
2007-08-03 14:07:17 +04:00
R0 . L = ( C O N F I G _ M I N _ V C O _ H Z / C O N F I G _ C L K I N _ H Z ) < < 9 ;
2008-01-11 12:21:41 +03:00
W[ P 0 ] = R 0 . l ; /* Set Min CLKIN to VCO multiplier */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
SSYNC;
IDLE;
call _ t e s t _ p l l _ l o c k e d ;
P0 . H = h i ( V R _ C T L ) ;
P0 . L = l o ( V R _ C T L ) ;
R7 = W [ P 0 ] ( z ) ;
R1 = 0 x6 ;
R1 < < = 1 6 ;
R2 = 0 x04 0 4 ( Z ) ;
R1 = R 1 | R 2 ;
R2 = D E P O S I T ( R 7 , R 1 ) ;
2008-01-11 12:21:41 +03:00
W[ P 0 ] = R 2 ; /* Set Min Core Voltage */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
SSYNC;
IDLE;
call _ t e s t _ p l l _ l o c k e d ;
2008-01-11 12:21:41 +03:00
R0 = P 3 ;
2008-02-08 23:12:37 +03:00
R1 = P 4 ;
R3 = P 5 ;
2008-01-11 12:21:41 +03:00
call _ s e t _ s i c _ i w r ; /* Set Awake from IDLE */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( P L L _ C T L ) ;
P0 . L = l o ( P L L _ C T L ) ;
R0 = W [ P 0 ] ( z ) ;
BITSET ( R 0 , 3 ) ;
2008-01-11 12:21:41 +03:00
W[ P 0 ] = R 0 . L ; /* Turn CCLK OFF */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
SSYNC;
IDLE;
call _ t e s t _ p l l _ l o c k e d ;
R0 = I W R _ E N A B L E ( 0 ) ;
2008-02-08 23:12:37 +03:00
R1 = I W R _ D I S A B L E _ A L L ;
R2 = I W R _ D I S A B L E _ A L L ;
2008-01-11 12:21:41 +03:00
call _ s e t _ s i c _ i w r ; /* Set Awake from IDLE PLL */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( V R _ C T L ) ;
P0 . L = l o ( V R _ C T L ) ;
W[ P 0 ] = R 7 ;
SSYNC;
IDLE;
call _ t e s t _ p l l _ l o c k e d ;
P0 . H = h i ( P L L _ D I V ) ;
P0 . L = l o ( P L L _ D I V ) ;
2008-01-11 12:21:41 +03:00
W[ P 0 ] = R 6 ; /* Restore CCLK and SCLK divider */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( P L L _ C T L ) ;
P0 . L = l o ( P L L _ C T L ) ;
2008-01-11 12:21:41 +03:00
w[ p0 ] = R 5 ; /* Restore VCO multiplier */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
IDLE;
call _ t e s t _ p l l _ l o c k e d ;
2008-01-11 12:21:41 +03:00
call _ u n s e t _ d r a m _ s r f s ; /* SDRAM Self Refresh Off */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
STI R 4 ;
RETS = [ S P + + ] ;
( R7 : 0 , P5 : 0 ) = [ SP+ + ] ;
RTS;
2008-07-16 13:07:26 +04:00
ENDPROC( _ s l e e p _ d e e p e r )
2008-07-19 12:57:32 +04:00
2007-12-23 18:02:13 +03:00
ENTRY( _ s e t _ d r a m _ s r f s )
/* set the dram to self refresh mode */
2008-07-19 12:57:32 +04:00
SSYNC;
# if d e f i n e d ( E B I U _ R S T C T L ) / * D D R * /
2007-12-23 18:02:13 +03:00
P0 . H = h i ( E B I U _ R S T C T L ) ;
P0 . L = l o ( E B I U _ R S T C T L ) ;
R2 = [ P 0 ] ;
2008-07-19 12:57:32 +04:00
BITSET( R 2 , 3 ) ; /* SRREQ enter self-refresh mode */
[ P0 ] = R 2 ;
SSYNC;
1 :
R2 = [ P 0 ] ;
CC = B I T T S T ( R 2 , 4 ) ;
if ! C C J U M P 1 b ;
# else / * S D R A M * /
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . L = l o ( E B I U _ S D G C T L ) ;
2008-07-19 12:57:32 +04:00
P0 . H = h i ( E B I U _ S D G C T L ) ;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
R2 = [ P 0 ] ;
2008-07-19 12:57:32 +04:00
BITSET( R 2 , 2 4 ) ; /* SRFS enter self-refresh mode */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
[ P0 ] = R 2 ;
2008-07-19 12:57:32 +04:00
SSYNC;
P0 . L = l o ( E B I U _ S D S T A T ) ;
P0 . H = h i ( E B I U _ S D S T A T ) ;
1 :
R2 = w [ P 0 ] ;
SSYNC;
cc = B I T T S T ( R 2 , 1 ) ; /* SDSRA poll self-refresh status */
if ! c c j u m p 1 b ;
P0 . L = l o ( E B I U _ S D G C T L ) ;
P0 . H = h i ( E B I U _ S D G C T L ) ;
2007-12-23 18:02:13 +03:00
R2 = [ P 0 ] ;
2008-07-19 12:57:32 +04:00
BITCLR( R 2 , 0 ) ; /* SCTLE disable CLKOUT */
[ P0 ] = R 2 ;
2007-12-23 18:02:13 +03:00
# endif
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
RTS;
2008-07-16 13:07:26 +04:00
ENDPROC( _ s e t _ d r a m _ s r f s )
2008-07-19 12:57:32 +04:00
2007-12-23 18:02:13 +03:00
ENTRY( _ u n s e t _ d r a m _ s r f s )
/* set the dram out of self refresh mode */
2008-07-19 12:57:32 +04:00
# if d e f i n e d ( E B I U _ R S T C T L ) / * D D R * /
2007-12-23 18:02:13 +03:00
P0 . H = h i ( E B I U _ R S T C T L ) ;
P0 . L = l o ( E B I U _ R S T C T L ) ;
R2 = [ P 0 ] ;
2008-07-19 12:57:32 +04:00
BITCLR( R 2 , 3 ) ; /* clear SRREQ bit */
[ P0 ] = R 2 ;
# elif d e f i n e d ( E B I U _ S D G C T L ) / * S D R A M * /
P0 . L = l o ( E B I U _ S D G C T L ) ; /* release CLKOUT from self-refresh */
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( E B I U _ S D G C T L ) ;
R2 = [ P 0 ] ;
2008-07-19 12:57:32 +04:00
BITSET( R 2 , 0 ) ; /* SCTLE enable CLKOUT */
[ P0 ] = R 2
SSYNC;
P0 . L = l o ( E B I U _ S D G C T L ) ; /* release SDRAM from self-refresh */
P0 . H = h i ( E B I U _ S D G C T L ) ;
R2 = [ P 0 ] ;
BITCLR( R 2 , 2 4 ) ; /* clear SRFS bit */
[ P0 ] = R 2
2007-12-23 18:02:13 +03:00
# endif
2008-07-19 12:57:32 +04:00
SSYNC;
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
RTS;
2008-07-16 13:07:26 +04:00
ENDPROC( _ u n s e t _ d r a m _ s r f s )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
ENTRY( _ s e t _ s i c _ i w r )
2008-11-18 12:48:22 +03:00
# if d e f i n e d ( C O N F I G _ B F 5 4 x ) | | d e f i n e d ( C O N F I G _ B F 5 2 x ) | | d e f i n e d ( C O N F I G _ B F 5 6 1 ) | | \
2008-11-18 12:48:21 +03:00
defined( C O N F I G _ B F 5 3 8 ) | | d e f i n e d ( C O N F I G _ B F 5 3 9 ) | | d e f i n e d ( C O N F I G _ B F 5 1 x )
2007-12-23 18:02:13 +03:00
P0 . H = h i ( S I C _ I W R 0 ) ;
P0 . L = l o ( S I C _ I W R 0 ) ;
2008-02-08 23:12:37 +03:00
P1 . H = h i ( S I C _ I W R 1 ) ;
P1 . L = l o ( S I C _ I W R 1 ) ;
[ P1 ] = R 1 ;
# if d e f i n e d ( C O N F I G _ B F 5 4 x )
P1 . H = h i ( S I C _ I W R 2 ) ;
P1 . L = l o ( S I C _ I W R 2 ) ;
[ P1 ] = R 2 ;
# endif
2007-12-23 18:02:13 +03:00
# else
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
P0 . H = h i ( S I C _ I W R ) ;
P0 . L = l o ( S I C _ I W R ) ;
2007-12-23 18:02:13 +03:00
# endif
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
[ P0 ] = R 0 ;
2008-02-08 23:12:37 +03:00
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
SSYNC;
RTS;
2008-07-16 13:07:26 +04:00
ENDPROC( _ s e t _ s i c _ i w r )
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 01:50:22 +04:00
ENTRY( _ t e s t _ p l l _ l o c k e d )
P0 . H = h i ( P L L _ S T A T ) ;
P0 . L = l o ( P L L _ S T A T ) ;
1 :
R0 = W [ P 0 ] ( Z ) ;
CC = B I T T S T ( R 0 ,5 ) ;
IF ! C C J U M P 1 b ;
RTS;
2008-07-16 13:07:26 +04:00
ENDPROC( _ t e s t _ p l l _ l o c k e d )
2008-07-19 12:57:32 +04:00
.section .text
ENTRY( _ d o _ h i b e r n a t e )
[ - - SP] = ( R 7 : 0 , P 5 : 0 ) ;
[ - - SP] = R E T S ;
/* Save System MMRs */
R2 = R 0 ;
P0 . H = h i ( P L L _ C T L ) ;
P0 . L = l o ( P L L _ C T L ) ;
# ifdef S I C _ I M A S K 0
PM_ S Y S _ P U S H ( S I C _ I M A S K 0 )
# endif
# ifdef S I C _ I M A S K 1
PM_ S Y S _ P U S H ( S I C _ I M A S K 1 )
# endif
# ifdef S I C _ I M A S K 2
PM_ S Y S _ P U S H ( S I C _ I M A S K 2 )
# endif
# ifdef S I C _ I M A S K
PM_ S Y S _ P U S H ( S I C _ I M A S K )
# endif
2010-10-19 22:44:23 +04:00
# ifdef S I C _ I A R 0
2008-07-19 12:57:32 +04:00
PM_ S Y S _ P U S H ( S I C _ I A R 0 )
PM_ S Y S _ P U S H ( S I C _ I A R 1 )
PM_ S Y S _ P U S H ( S I C _ I A R 2 )
# endif
# ifdef S I C _ I A R 3
PM_ S Y S _ P U S H ( S I C _ I A R 3 )
# endif
# ifdef S I C _ I A R 4
PM_ S Y S _ P U S H ( S I C _ I A R 4 )
PM_ S Y S _ P U S H ( S I C _ I A R 5 )
PM_ S Y S _ P U S H ( S I C _ I A R 6 )
# endif
# ifdef S I C _ I A R 7
PM_ S Y S _ P U S H ( S I C _ I A R 7 )
# endif
# ifdef S I C _ I A R 8
PM_ S Y S _ P U S H ( S I C _ I A R 8 )
PM_ S Y S _ P U S H ( S I C _ I A R 9 )
PM_ S Y S _ P U S H ( S I C _ I A R 1 0 )
PM_ S Y S _ P U S H ( S I C _ I A R 1 1 )
# endif
# ifdef S I C _ I W R
PM_ S Y S _ P U S H ( S I C _ I W R )
# endif
# ifdef S I C _ I W R 0
PM_ S Y S _ P U S H ( S I C _ I W R 0 )
# endif
# ifdef S I C _ I W R 1
PM_ S Y S _ P U S H ( S I C _ I W R 1 )
# endif
# ifdef S I C _ I W R 2
PM_ S Y S _ P U S H ( S I C _ I W R 2 )
# endif
# ifdef P I N T 0 _ A S S I G N
2009-03-05 13:41:24 +03:00
PM_ S Y S _ P U S H ( P I N T 0 _ M A S K _ S E T )
PM_ S Y S _ P U S H ( P I N T 1 _ M A S K _ S E T )
PM_ S Y S _ P U S H ( P I N T 2 _ M A S K _ S E T )
PM_ S Y S _ P U S H ( P I N T 3 _ M A S K _ S E T )
2008-07-19 12:57:32 +04:00
PM_ S Y S _ P U S H ( P I N T 0 _ A S S I G N )
PM_ S Y S _ P U S H ( P I N T 1 _ A S S I G N )
PM_ S Y S _ P U S H ( P I N T 2 _ A S S I G N )
PM_ S Y S _ P U S H ( P I N T 3 _ A S S I G N )
2009-03-05 13:41:24 +03:00
PM_ S Y S _ P U S H ( P I N T 0 _ I N V E R T _ S E T )
PM_ S Y S _ P U S H ( P I N T 1 _ I N V E R T _ S E T )
PM_ S Y S _ P U S H ( P I N T 2 _ I N V E R T _ S E T )
PM_ S Y S _ P U S H ( P I N T 3 _ I N V E R T _ S E T )
PM_ S Y S _ P U S H ( P I N T 0 _ E D G E _ S E T )
PM_ S Y S _ P U S H ( P I N T 1 _ E D G E _ S E T )
PM_ S Y S _ P U S H ( P I N T 2 _ E D G E _ S E T )
PM_ S Y S _ P U S H ( P I N T 3 _ E D G E _ S E T )
2008-07-19 12:57:32 +04:00
# endif
PM_ S Y S _ P U S H ( E B I U _ A M B C T L 0 )
PM_ S Y S _ P U S H ( E B I U _ A M B C T L 1 )
PM_ S Y S _ P U S H 1 6 ( E B I U _ A M G C T L )
# ifdef E B I U _ F C T L
PM_ S Y S _ P U S H ( E B I U _ M B S C T L )
PM_ S Y S _ P U S H ( E B I U _ M O D E )
PM_ S Y S _ P U S H ( E B I U _ F C T L )
# endif
2009-09-28 16:23:41 +04:00
# ifdef P O R T C I O _ F E R
PM_ S Y S _ P U S H 1 6 ( P O R T C I O _ D I R )
PM_ S Y S _ P U S H 1 6 ( P O R T C I O _ I N E N )
PM_ S Y S _ P U S H 1 6 ( P O R T C I O )
PM_ S Y S _ P U S H 1 6 ( P O R T C I O _ F E R )
PM_ S Y S _ P U S H 1 6 ( P O R T D I O _ D I R )
PM_ S Y S _ P U S H 1 6 ( P O R T D I O _ I N E N )
PM_ S Y S _ P U S H 1 6 ( P O R T D I O )
PM_ S Y S _ P U S H 1 6 ( P O R T D I O _ F E R )
PM_ S Y S _ P U S H 1 6 ( P O R T E I O _ D I R )
PM_ S Y S _ P U S H 1 6 ( P O R T E I O _ I N E N )
PM_ S Y S _ P U S H 1 6 ( P O R T E I O )
PM_ S Y S _ P U S H 1 6 ( P O R T E I O _ F E R )
# endif
2008-07-19 12:57:32 +04:00
PM_ S Y S _ P U S H 1 6 ( S Y S C R )
/* Save Core MMRs */
P0 . H = h i ( S R A M _ B A S E _ A D D R E S S ) ;
P0 . L = l o ( S R A M _ B A S E _ A D D R E S S ) ;
PM_ P U S H ( D M E M _ C O N T R O L )
PM_ P U S H ( D C P L B _ A D D R 0 )
PM_ P U S H ( D C P L B _ A D D R 1 )
PM_ P U S H ( D C P L B _ A D D R 2 )
PM_ P U S H ( D C P L B _ A D D R 3 )
PM_ P U S H ( D C P L B _ A D D R 4 )
PM_ P U S H ( D C P L B _ A D D R 5 )
PM_ P U S H ( D C P L B _ A D D R 6 )
PM_ P U S H ( D C P L B _ A D D R 7 )
PM_ P U S H ( D C P L B _ A D D R 8 )
PM_ P U S H ( D C P L B _ A D D R 9 )
PM_ P U S H ( D C P L B _ A D D R 1 0 )
PM_ P U S H ( D C P L B _ A D D R 1 1 )
PM_ P U S H ( D C P L B _ A D D R 1 2 )
PM_ P U S H ( D C P L B _ A D D R 1 3 )
PM_ P U S H ( D C P L B _ A D D R 1 4 )
PM_ P U S H ( D C P L B _ A D D R 1 5 )
PM_ P U S H ( D C P L B _ D A T A 0 )
PM_ P U S H ( D C P L B _ D A T A 1 )
PM_ P U S H ( D C P L B _ D A T A 2 )
PM_ P U S H ( D C P L B _ D A T A 3 )
PM_ P U S H ( D C P L B _ D A T A 4 )
PM_ P U S H ( D C P L B _ D A T A 5 )
PM_ P U S H ( D C P L B _ D A T A 6 )
PM_ P U S H ( D C P L B _ D A T A 7 )
PM_ P U S H ( D C P L B _ D A T A 8 )
PM_ P U S H ( D C P L B _ D A T A 9 )
PM_ P U S H ( D C P L B _ D A T A 1 0 )
PM_ P U S H ( D C P L B _ D A T A 1 1 )
PM_ P U S H ( D C P L B _ D A T A 1 2 )
PM_ P U S H ( D C P L B _ D A T A 1 3 )
PM_ P U S H ( D C P L B _ D A T A 1 4 )
PM_ P U S H ( D C P L B _ D A T A 1 5 )
PM_ P U S H ( I M E M _ C O N T R O L )
PM_ P U S H ( I C P L B _ A D D R 0 )
PM_ P U S H ( I C P L B _ A D D R 1 )
PM_ P U S H ( I C P L B _ A D D R 2 )
PM_ P U S H ( I C P L B _ A D D R 3 )
PM_ P U S H ( I C P L B _ A D D R 4 )
PM_ P U S H ( I C P L B _ A D D R 5 )
PM_ P U S H ( I C P L B _ A D D R 6 )
PM_ P U S H ( I C P L B _ A D D R 7 )
PM_ P U S H ( I C P L B _ A D D R 8 )
PM_ P U S H ( I C P L B _ A D D R 9 )
PM_ P U S H ( I C P L B _ A D D R 1 0 )
PM_ P U S H ( I C P L B _ A D D R 1 1 )
PM_ P U S H ( I C P L B _ A D D R 1 2 )
PM_ P U S H ( I C P L B _ A D D R 1 3 )
PM_ P U S H ( I C P L B _ A D D R 1 4 )
PM_ P U S H ( I C P L B _ A D D R 1 5 )
PM_ P U S H ( I C P L B _ D A T A 0 )
PM_ P U S H ( I C P L B _ D A T A 1 )
PM_ P U S H ( I C P L B _ D A T A 2 )
PM_ P U S H ( I C P L B _ D A T A 3 )
PM_ P U S H ( I C P L B _ D A T A 4 )
PM_ P U S H ( I C P L B _ D A T A 5 )
PM_ P U S H ( I C P L B _ D A T A 6 )
PM_ P U S H ( I C P L B _ D A T A 7 )
PM_ P U S H ( I C P L B _ D A T A 8 )
PM_ P U S H ( I C P L B _ D A T A 9 )
PM_ P U S H ( I C P L B _ D A T A 1 0 )
PM_ P U S H ( I C P L B _ D A T A 1 1 )
PM_ P U S H ( I C P L B _ D A T A 1 2 )
PM_ P U S H ( I C P L B _ D A T A 1 3 )
PM_ P U S H ( I C P L B _ D A T A 1 4 )
PM_ P U S H ( I C P L B _ D A T A 1 5 )
PM_ P U S H ( E V T 0 )
PM_ P U S H ( E V T 1 )
PM_ P U S H ( E V T 2 )
PM_ P U S H ( E V T 3 )
PM_ P U S H ( E V T 4 )
PM_ P U S H ( E V T 5 )
PM_ P U S H ( E V T 6 )
PM_ P U S H ( E V T 7 )
PM_ P U S H ( E V T 8 )
PM_ P U S H ( E V T 9 )
PM_ P U S H ( E V T 1 0 )
PM_ P U S H ( E V T 1 1 )
PM_ P U S H ( E V T 1 2 )
PM_ P U S H ( E V T 1 3 )
PM_ P U S H ( E V T 1 4 )
PM_ P U S H ( E V T 1 5 )
PM_ P U S H ( I M A S K )
PM_ P U S H ( I L A T )
PM_ P U S H ( I P R I O )
PM_ P U S H ( T C N T L )
PM_ P U S H ( T P E R I O D )
PM_ P U S H ( T S C A L E )
PM_ P U S H ( T C O U N T )
PM_ P U S H ( T B U F C T L )
/* Save Core Registers */
[ - - sp] = S Y S C F G ;
[ - - sp] = ( R 7 : 0 , P 5 : 0 ) ;
[ - - sp] = f p ;
[ - - sp] = u s p ;
[ - - sp] = i 0 ;
[ - - sp] = i 1 ;
[ - - sp] = i 2 ;
[ - - sp] = i 3 ;
[ - - sp] = m 0 ;
[ - - sp] = m 1 ;
[ - - sp] = m 2 ;
[ - - sp] = m 3 ;
[ - - sp] = l 0 ;
[ - - sp] = l 1 ;
[ - - sp] = l 2 ;
[ - - sp] = l 3 ;
[ - - sp] = b0 ;
[ - - sp] = b1 ;
[ - - sp] = b2 ;
[ - - sp] = b3 ;
[ - - sp] = a0 . x ;
[ - - sp] = a0 . w ;
[ - - sp] = a1 . x ;
[ - - sp] = a1 . w ;
[ - - sp] = L C 0 ;
[ - - sp] = L C 1 ;
[ - - sp] = L T 0 ;
[ - - sp] = L T 1 ;
[ - - sp] = L B 0 ;
[ - - sp] = L B 1 ;
[ - - sp] = A S T A T ;
[ - - sp] = C Y C L E S ;
[ - - sp] = C Y C L E S 2 ;
[ - - sp] = R E T S ;
r0 = R E T I ;
[ - - sp] = r0 ;
[ - - sp] = R E T X ;
[ - - sp] = R E T N ;
[ - - sp] = R E T E ;
[ - - sp] = S E Q S T A T ;
/* Save Magic, return address and Stack Pointer */
P0 . H = 0 ;
P0 . L = 0 ;
R0 . H = 0 x D E A D ; /* Hibernate Magic */
R0 . L = 0 x B E E F ;
[ P0 + + ] = R 0 ; /* Store Hibernate Magic */
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R0 . H = . L p m _ r e s u m e _ h e r e ;
R0 . L = . L p m _ r e s u m e _ h e r e ;
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[ P0 + + ] = R 0 ; /* Save Return Address */
[ P0 + + ] = S P ; /* Save Stack Pointer */
P0 . H = _ h i b e r n a t e _ m o d e ;
P0 . L = _ h i b e r n a t e _ m o d e ;
R0 = R 2 ;
call ( P 0 ) ; /* Goodbye */
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.Lpm_resume_here :
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/* Restore Core Registers */
SEQSTAT = [ s p + + ] ;
RETE = [ s p + + ] ;
RETN = [ s p + + ] ;
RETX = [ s p + + ] ;
r0 = [ s p + + ] ;
RETI = r0 ;
RETS = [ s p + + ] ;
CYCLES2 = [ s p + + ] ;
CYCLES = [ s p + + ] ;
ASTAT = [ s p + + ] ;
LB1 = [ s p + + ] ;
LB0 = [ s p + + ] ;
LT1 = [ s p + + ] ;
LT0 = [ s p + + ] ;
LC1 = [ s p + + ] ;
LC0 = [ s p + + ] ;
a1 . w = [ s p + + ] ;
a1 . x = [ s p + + ] ;
a0 . w = [ s p + + ] ;
a0 . x = [ s p + + ] ;
b3 = [ s p + + ] ;
b2 = [ s p + + ] ;
b1 = [ s p + + ] ;
b0 = [ s p + + ] ;
l3 = [ s p + + ] ;
l2 = [ s p + + ] ;
l1 = [ s p + + ] ;
l0 = [ s p + + ] ;
m3 = [ s p + + ] ;
m2 = [ s p + + ] ;
m1 = [ s p + + ] ;
m0 = [ s p + + ] ;
i3 = [ s p + + ] ;
i2 = [ s p + + ] ;
i1 = [ s p + + ] ;
i0 = [ s p + + ] ;
usp = [ s p + + ] ;
fp = [ s p + + ] ;
( R7 : 0 , P 5 : 0 ) = [ S P + + ] ;
SYSCFG = [ s p + + ] ;
/* Restore Core MMRs */
PM_ P O P ( T B U F C T L )
PM_ P O P ( T C O U N T )
PM_ P O P ( T S C A L E )
PM_ P O P ( T P E R I O D )
PM_ P O P ( T C N T L )
PM_ P O P ( I P R I O )
PM_ P O P ( I L A T )
PM_ P O P ( I M A S K )
PM_ P O P ( E V T 1 5 )
PM_ P O P ( E V T 1 4 )
PM_ P O P ( E V T 1 3 )
PM_ P O P ( E V T 1 2 )
PM_ P O P ( E V T 1 1 )
PM_ P O P ( E V T 1 0 )
PM_ P O P ( E V T 9 )
PM_ P O P ( E V T 8 )
PM_ P O P ( E V T 7 )
PM_ P O P ( E V T 6 )
PM_ P O P ( E V T 5 )
PM_ P O P ( E V T 4 )
PM_ P O P ( E V T 3 )
PM_ P O P ( E V T 2 )
PM_ P O P ( E V T 1 )
PM_ P O P ( E V T 0 )
PM_ P O P ( I C P L B _ D A T A 1 5 )
PM_ P O P ( I C P L B _ D A T A 1 4 )
PM_ P O P ( I C P L B _ D A T A 1 3 )
PM_ P O P ( I C P L B _ D A T A 1 2 )
PM_ P O P ( I C P L B _ D A T A 1 1 )
PM_ P O P ( I C P L B _ D A T A 1 0 )
PM_ P O P ( I C P L B _ D A T A 9 )
PM_ P O P ( I C P L B _ D A T A 8 )
PM_ P O P ( I C P L B _ D A T A 7 )
PM_ P O P ( I C P L B _ D A T A 6 )
PM_ P O P ( I C P L B _ D A T A 5 )
PM_ P O P ( I C P L B _ D A T A 4 )
PM_ P O P ( I C P L B _ D A T A 3 )
PM_ P O P ( I C P L B _ D A T A 2 )
PM_ P O P ( I C P L B _ D A T A 1 )
PM_ P O P ( I C P L B _ D A T A 0 )
PM_ P O P ( I C P L B _ A D D R 1 5 )
PM_ P O P ( I C P L B _ A D D R 1 4 )
PM_ P O P ( I C P L B _ A D D R 1 3 )
PM_ P O P ( I C P L B _ A D D R 1 2 )
PM_ P O P ( I C P L B _ A D D R 1 1 )
PM_ P O P ( I C P L B _ A D D R 1 0 )
PM_ P O P ( I C P L B _ A D D R 9 )
PM_ P O P ( I C P L B _ A D D R 8 )
PM_ P O P ( I C P L B _ A D D R 7 )
PM_ P O P ( I C P L B _ A D D R 6 )
PM_ P O P ( I C P L B _ A D D R 5 )
PM_ P O P ( I C P L B _ A D D R 4 )
PM_ P O P ( I C P L B _ A D D R 3 )
PM_ P O P ( I C P L B _ A D D R 2 )
PM_ P O P ( I C P L B _ A D D R 1 )
PM_ P O P ( I C P L B _ A D D R 0 )
PM_ P O P ( I M E M _ C O N T R O L )
PM_ P O P ( D C P L B _ D A T A 1 5 )
PM_ P O P ( D C P L B _ D A T A 1 4 )
PM_ P O P ( D C P L B _ D A T A 1 3 )
PM_ P O P ( D C P L B _ D A T A 1 2 )
PM_ P O P ( D C P L B _ D A T A 1 1 )
PM_ P O P ( D C P L B _ D A T A 1 0 )
PM_ P O P ( D C P L B _ D A T A 9 )
PM_ P O P ( D C P L B _ D A T A 8 )
PM_ P O P ( D C P L B _ D A T A 7 )
PM_ P O P ( D C P L B _ D A T A 6 )
PM_ P O P ( D C P L B _ D A T A 5 )
PM_ P O P ( D C P L B _ D A T A 4 )
PM_ P O P ( D C P L B _ D A T A 3 )
PM_ P O P ( D C P L B _ D A T A 2 )
PM_ P O P ( D C P L B _ D A T A 1 )
PM_ P O P ( D C P L B _ D A T A 0 )
PM_ P O P ( D C P L B _ A D D R 1 5 )
PM_ P O P ( D C P L B _ A D D R 1 4 )
PM_ P O P ( D C P L B _ A D D R 1 3 )
PM_ P O P ( D C P L B _ A D D R 1 2 )
PM_ P O P ( D C P L B _ A D D R 1 1 )
PM_ P O P ( D C P L B _ A D D R 1 0 )
PM_ P O P ( D C P L B _ A D D R 9 )
PM_ P O P ( D C P L B _ A D D R 8 )
PM_ P O P ( D C P L B _ A D D R 7 )
PM_ P O P ( D C P L B _ A D D R 6 )
PM_ P O P ( D C P L B _ A D D R 5 )
PM_ P O P ( D C P L B _ A D D R 4 )
PM_ P O P ( D C P L B _ A D D R 3 )
PM_ P O P ( D C P L B _ A D D R 2 )
PM_ P O P ( D C P L B _ A D D R 1 )
PM_ P O P ( D C P L B _ A D D R 0 )
PM_ P O P ( D M E M _ C O N T R O L )
/* Restore System MMRs */
P0 . H = h i ( P L L _ C T L ) ;
P0 . L = l o ( P L L _ C T L ) ;
PM_ S Y S _ P O P 1 6 ( S Y S C R )
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# ifdef P O R T C I O _ F E R
PM_ S Y S _ P O P 1 6 ( P O R T E I O _ F E R )
PM_ S Y S _ P O P 1 6 ( P O R T E I O )
PM_ S Y S _ P O P 1 6 ( P O R T E I O _ I N E N )
PM_ S Y S _ P O P 1 6 ( P O R T E I O _ D I R )
PM_ S Y S _ P O P 1 6 ( P O R T D I O _ F E R )
PM_ S Y S _ P O P 1 6 ( P O R T D I O )
PM_ S Y S _ P O P 1 6 ( P O R T D I O _ I N E N )
PM_ S Y S _ P O P 1 6 ( P O R T D I O _ D I R )
PM_ S Y S _ P O P 1 6 ( P O R T C I O _ F E R )
PM_ S Y S _ P O P 1 6 ( P O R T C I O )
PM_ S Y S _ P O P 1 6 ( P O R T C I O _ I N E N )
PM_ S Y S _ P O P 1 6 ( P O R T C I O _ D I R )
# endif
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# ifdef E B I U _ F C T L
PM_ S Y S _ P O P ( E B I U _ F C T L )
PM_ S Y S _ P O P ( E B I U _ M O D E )
PM_ S Y S _ P O P ( E B I U _ M B S C T L )
# endif
PM_ S Y S _ P O P 1 6 ( E B I U _ A M G C T L )
PM_ S Y S _ P O P ( E B I U _ A M B C T L 1 )
PM_ S Y S _ P O P ( E B I U _ A M B C T L 0 )
# ifdef P I N T 0 _ A S S I G N
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PM_ S Y S _ P O P ( P I N T 3 _ E D G E _ S E T )
PM_ S Y S _ P O P ( P I N T 2 _ E D G E _ S E T )
PM_ S Y S _ P O P ( P I N T 1 _ E D G E _ S E T )
PM_ S Y S _ P O P ( P I N T 0 _ E D G E _ S E T )
PM_ S Y S _ P O P ( P I N T 3 _ I N V E R T _ S E T )
PM_ S Y S _ P O P ( P I N T 2 _ I N V E R T _ S E T )
PM_ S Y S _ P O P ( P I N T 1 _ I N V E R T _ S E T )
PM_ S Y S _ P O P ( P I N T 0 _ I N V E R T _ S E T )
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PM_ S Y S _ P O P ( P I N T 3 _ A S S I G N )
PM_ S Y S _ P O P ( P I N T 2 _ A S S I G N )
PM_ S Y S _ P O P ( P I N T 1 _ A S S I G N )
PM_ S Y S _ P O P ( P I N T 0 _ A S S I G N )
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PM_ S Y S _ P O P ( P I N T 3 _ M A S K _ S E T )
PM_ S Y S _ P O P ( P I N T 2 _ M A S K _ S E T )
PM_ S Y S _ P O P ( P I N T 1 _ M A S K _ S E T )
PM_ S Y S _ P O P ( P I N T 0 _ M A S K _ S E T )
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# endif
# ifdef S I C _ I W R 2
PM_ S Y S _ P O P ( S I C _ I W R 2 )
# endif
# ifdef S I C _ I W R 1
PM_ S Y S _ P O P ( S I C _ I W R 1 )
# endif
# ifdef S I C _ I W R 0
PM_ S Y S _ P O P ( S I C _ I W R 0 )
# endif
# ifdef S I C _ I W R
PM_ S Y S _ P O P ( S I C _ I W R )
# endif
# ifdef S I C _ I A R 8
PM_ S Y S _ P O P ( S I C _ I A R 1 1 )
PM_ S Y S _ P O P ( S I C _ I A R 1 0 )
PM_ S Y S _ P O P ( S I C _ I A R 9 )
PM_ S Y S _ P O P ( S I C _ I A R 8 )
# endif
# ifdef S I C _ I A R 7
PM_ S Y S _ P O P ( S I C _ I A R 7 )
# endif
# ifdef S I C _ I A R 6
PM_ S Y S _ P O P ( S I C _ I A R 6 )
PM_ S Y S _ P O P ( S I C _ I A R 5 )
PM_ S Y S _ P O P ( S I C _ I A R 4 )
# endif
# ifdef S I C _ I A R 3
PM_ S Y S _ P O P ( S I C _ I A R 3 )
# endif
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# ifdef S I C _ I A R 0
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PM_ S Y S _ P O P ( S I C _ I A R 2 )
PM_ S Y S _ P O P ( S I C _ I A R 1 )
PM_ S Y S _ P O P ( S I C _ I A R 0 )
# endif
# ifdef S I C _ I M A S K
PM_ S Y S _ P O P ( S I C _ I M A S K )
# endif
# ifdef S I C _ I M A S K 2
PM_ S Y S _ P O P ( S I C _ I M A S K 2 )
# endif
# ifdef S I C _ I M A S K 1
PM_ S Y S _ P O P ( S I C _ I M A S K 1 )
# endif
# ifdef S I C _ I M A S K 0
PM_ S Y S _ P O P ( S I C _ I M A S K 0 )
# endif
[ - - sp] = R E T I ; /* Clear Global Interrupt Disable */
SP + = 4 ;
RETS = [ S P + + ] ;
( R7 : 0 , P5 : 0 ) = [ SP+ + ] ;
RTS;
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ENDPROC( _ d o _ h i b e r n a t e )
