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linux/drivers/irqchip/irq-ixp4xx.c

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irqchip: Add driver for IXP4xx The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale platform that has very wide deployment and use. As part of modernizing the platform, we need to implement a proper irqchip in the irqchip subsystem. The IXP4xx irqchip is tightly jotted together with the GPIO controller, and whereas in the past we would deal with this complex logic by adding necessarily different code, we can nowadays modernize it using a hierarchical irqchip. The actual IXP4 irqchip is a simple active low level IRQ controller, whereas the GPIO functionality resides in a different memory area and adds edge trigger support for the interrupts. The interrupts from GPIO lines 0..12 are 1:1 mapped to a fixed set of hardware IRQs on this IRQchip, so we expect the child GPIO interrupt controller to go in and allocate descriptors for these interrupts. For the other interrupts, as we do not yet have DT support for this platform, we create a linear irqdomain and then go in and allocate the IRQs that the legacy boards use. This code will be removed on the DT probe path when we add DT support to the platform. We add some translation code for supporting DT translations for the fwnodes, but we leave most of that for later. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-25 18:41:25 +03:00
// SPDX-License-Identifier: GPL-2.0
/*
* irqchip for the IXP4xx interrupt controller
* Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
*
* Based on arch/arm/mach-ixp4xx/common.c
* Copyright 2002 (C) Intel Corporation
* Copyright 2003-2004 (C) MontaVista, Software, Inc.
* Copyright (C) Deepak Saxena <dsaxena@plexity.net>
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
irqchip: ixp4xx: Add OF initialization support This adds support for probing and settin up the IXP4xx irqchip from device tree. Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-27 16:05:53 +03:00
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
irqchip: Add driver for IXP4xx The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale platform that has very wide deployment and use. As part of modernizing the platform, we need to implement a proper irqchip in the irqchip subsystem. The IXP4xx irqchip is tightly jotted together with the GPIO controller, and whereas in the past we would deal with this complex logic by adding necessarily different code, we can nowadays modernize it using a hierarchical irqchip. The actual IXP4 irqchip is a simple active low level IRQ controller, whereas the GPIO functionality resides in a different memory area and adds edge trigger support for the interrupts. The interrupts from GPIO lines 0..12 are 1:1 mapped to a fixed set of hardware IRQs on this IRQchip, so we expect the child GPIO interrupt controller to go in and allocate descriptors for these interrupts. For the other interrupts, as we do not yet have DT support for this platform, we create a linear irqdomain and then go in and allocate the IRQs that the legacy boards use. This code will be removed on the DT probe path when we add DT support to the platform. We add some translation code for supporting DT translations for the fwnodes, but we leave most of that for later. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-25 18:41:25 +03:00
#include <linux/platform_device.h>
#include <linux/cpu.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#define IXP4XX_ICPR 0x00 /* Interrupt Status */
#define IXP4XX_ICMR 0x04 /* Interrupt Enable */
#define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
#define IXP4XX_ICIP 0x0C /* IRQ Status */
#define IXP4XX_ICFP 0x10 /* FIQ Status */
#define IXP4XX_ICHR 0x14 /* Interrupt Priority */
#define IXP4XX_ICIH 0x18 /* IRQ Highest Pri Int */
#define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
/* IXP43x and IXP46x-only */
#define IXP4XX_ICPR2 0x20 /* Interrupt Status 2 */
#define IXP4XX_ICMR2 0x24 /* Interrupt Enable 2 */
#define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
#define IXP4XX_ICIP2 0x2C /* IRQ Status */
#define IXP4XX_ICFP2 0x30 /* FIQ Status */
#define IXP4XX_ICEEN 0x34 /* Error High Pri Enable */
/**
* struct ixp4xx_irq - state container for the Faraday IRQ controller
* @irqbase: IRQ controller memory base in virtual memory
* @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
* @irqchip: irqchip for this instance
* @domain: IRQ domain for this instance
*/
struct ixp4xx_irq {
void __iomem *irqbase;
bool is_356;
struct irq_chip irqchip;
struct irq_domain *domain;
};
/* Local static state container */
static struct ixp4xx_irq ixirq;
/* GPIO Clocks */
#define IXP4XX_GPIO_CLK_0 14
#define IXP4XX_GPIO_CLK_1 15
static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
{
/* All are level active high (asserted) here */
if (type != IRQ_TYPE_LEVEL_HIGH)
return -EINVAL;
return 0;
}
static void ixp4xx_irq_mask(struct irq_data *d)
{
struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
u32 val;
if (ixi->is_356 && d->hwirq >= 32) {
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
val &= ~BIT(d->hwirq - 32);
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
} else {
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
val &= ~BIT(d->hwirq);
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
}
}
/*
* Level triggered interrupts on GPIO lines can only be cleared when the
* interrupt condition disappears.
*/
static void ixp4xx_irq_unmask(struct irq_data *d)
{
struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
u32 val;
if (ixi->is_356 && d->hwirq >= 32) {
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
val |= BIT(d->hwirq - 32);
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
} else {
val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
val |= BIT(d->hwirq);
__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
}
}
irq/gpio: ixp4xx: Drop boardfile probe path The boardfiles for IXP4xx have been deleted. Delete all the quirks and code dealing with that boot path and rely solely on device tree boot. Fix some missing static keywords that the kernel test robot was complaining about while we're at it. Cc: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2022-04-21 23:06:54 +03:00
static asmlinkage void __exception_irq_entry
ixp4xx_handle_irq(struct pt_regs *regs)
irqchip: Add driver for IXP4xx The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale platform that has very wide deployment and use. As part of modernizing the platform, we need to implement a proper irqchip in the irqchip subsystem. The IXP4xx irqchip is tightly jotted together with the GPIO controller, and whereas in the past we would deal with this complex logic by adding necessarily different code, we can nowadays modernize it using a hierarchical irqchip. The actual IXP4 irqchip is a simple active low level IRQ controller, whereas the GPIO functionality resides in a different memory area and adds edge trigger support for the interrupts. The interrupts from GPIO lines 0..12 are 1:1 mapped to a fixed set of hardware IRQs on this IRQchip, so we expect the child GPIO interrupt controller to go in and allocate descriptors for these interrupts. For the other interrupts, as we do not yet have DT support for this platform, we create a linear irqdomain and then go in and allocate the IRQs that the legacy boards use. This code will be removed on the DT probe path when we add DT support to the platform. We add some translation code for supporting DT translations for the fwnodes, but we leave most of that for later. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-25 18:41:25 +03:00
{
struct ixp4xx_irq *ixi = &ixirq;
unsigned long status;
int i;
status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
for_each_set_bit(i, &status, 32)
irq: remove handle_domain_{irq,nmi}() Now that entry code handles IRQ entry (including setting the IRQ regs) before calling irqchip code, irqchip code can safely call generic_handle_domain_irq(), and there's no functional reason for it to call handle_domain_irq(). Let's cement this split of responsibility and remove handle_domain_irq() entirely, updating irqchip drivers to call generic_handle_domain_irq(). For consistency, handle_domain_nmi() is similarly removed and replaced with a generic_handle_domain_nmi() function which also does not perform any entry logic. Previously handle_domain_{irq,nmi}() had a WARN_ON() which would fire when they were called in an inappropriate context. So that we can identify similar issues going forward, similar WARN_ON_ONCE() logic is added to the generic_handle_*() functions, and comments are updated for clarity and consistency. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de>
2021-10-20 22:23:09 +03:00
generic_handle_domain_irq(ixi->domain, i);
irqchip: Add driver for IXP4xx The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale platform that has very wide deployment and use. As part of modernizing the platform, we need to implement a proper irqchip in the irqchip subsystem. The IXP4xx irqchip is tightly jotted together with the GPIO controller, and whereas in the past we would deal with this complex logic by adding necessarily different code, we can nowadays modernize it using a hierarchical irqchip. The actual IXP4 irqchip is a simple active low level IRQ controller, whereas the GPIO functionality resides in a different memory area and adds edge trigger support for the interrupts. The interrupts from GPIO lines 0..12 are 1:1 mapped to a fixed set of hardware IRQs on this IRQchip, so we expect the child GPIO interrupt controller to go in and allocate descriptors for these interrupts. For the other interrupts, as we do not yet have DT support for this platform, we create a linear irqdomain and then go in and allocate the IRQs that the legacy boards use. This code will be removed on the DT probe path when we add DT support to the platform. We add some translation code for supporting DT translations for the fwnodes, but we leave most of that for later. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-25 18:41:25 +03:00
/*
* IXP465/IXP435 has an upper IRQ status register
*/
if (ixi->is_356) {
status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
for_each_set_bit(i, &status, 32)
irq: remove handle_domain_{irq,nmi}() Now that entry code handles IRQ entry (including setting the IRQ regs) before calling irqchip code, irqchip code can safely call generic_handle_domain_irq(), and there's no functional reason for it to call handle_domain_irq(). Let's cement this split of responsibility and remove handle_domain_irq() entirely, updating irqchip drivers to call generic_handle_domain_irq(). For consistency, handle_domain_nmi() is similarly removed and replaced with a generic_handle_domain_nmi() function which also does not perform any entry logic. Previously handle_domain_{irq,nmi}() had a WARN_ON() which would fire when they were called in an inappropriate context. So that we can identify similar issues going forward, similar WARN_ON_ONCE() logic is added to the generic_handle_*() functions, and comments are updated for clarity and consistency. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de>
2021-10-20 22:23:09 +03:00
generic_handle_domain_irq(ixi->domain, i + 32);
irqchip: Add driver for IXP4xx The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale platform that has very wide deployment and use. As part of modernizing the platform, we need to implement a proper irqchip in the irqchip subsystem. The IXP4xx irqchip is tightly jotted together with the GPIO controller, and whereas in the past we would deal with this complex logic by adding necessarily different code, we can nowadays modernize it using a hierarchical irqchip. The actual IXP4 irqchip is a simple active low level IRQ controller, whereas the GPIO functionality resides in a different memory area and adds edge trigger support for the interrupts. The interrupts from GPIO lines 0..12 are 1:1 mapped to a fixed set of hardware IRQs on this IRQchip, so we expect the child GPIO interrupt controller to go in and allocate descriptors for these interrupts. For the other interrupts, as we do not yet have DT support for this platform, we create a linear irqdomain and then go in and allocate the IRQs that the legacy boards use. This code will be removed on the DT probe path when we add DT support to the platform. We add some translation code for supporting DT translations for the fwnodes, but we leave most of that for later. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-25 18:41:25 +03:00
}
}
static int ixp4xx_irq_domain_translate(struct irq_domain *domain,
struct irq_fwspec *fwspec,
unsigned long *hwirq,
unsigned int *type)
{
/* We support standard DT translation */
if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
*hwirq = fwspec->param[0];
*type = fwspec->param[1];
return 0;
}
if (is_fwnode_irqchip(fwspec->fwnode)) {
if (fwspec->param_count != 2)
return -EINVAL;
*hwirq = fwspec->param[0];
*type = fwspec->param[1];
WARN_ON(*type == IRQ_TYPE_NONE);
return 0;
}
return -EINVAL;
}
static int ixp4xx_irq_domain_alloc(struct irq_domain *d,
unsigned int irq, unsigned int nr_irqs,
void *data)
{
struct ixp4xx_irq *ixi = d->host_data;
irq_hw_number_t hwirq;
unsigned int type = IRQ_TYPE_NONE;
struct irq_fwspec *fwspec = data;
int ret;
int i;
ret = ixp4xx_irq_domain_translate(d, fwspec, &hwirq, &type);
if (ret)
return ret;
for (i = 0; i < nr_irqs; i++) {
/*
* TODO: after converting IXP4xx to only device tree, set
* handle_bad_irq as default handler and assume all consumers
* call .set_type() as this is provided in the second cell in
* the device tree phandle.
*/
irq_domain_set_info(d,
irq + i,
hwirq + i,
&ixi->irqchip,
ixi,
handle_level_irq,
NULL, NULL);
irq_set_probe(irq + i);
}
return 0;
}
/*
* This needs to be a hierarchical irqdomain to work well with the
* GPIO irqchip (which is lower in the hierarchy)
*/
static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
.translate = ixp4xx_irq_domain_translate,
.alloc = ixp4xx_irq_domain_alloc,
.free = irq_domain_free_irqs_common,
};
/**
* ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
* @ixi: State container
* @irqbase: Virtual memory base for the interrupt controller
* @fwnode: Corresponding fwnode abstraction for this controller
* @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
*/
ARM: ixp4xx: mark ixp4xx_irq_setup as __init Kbuild complains about ixp4xx_irq_setup not being __init itself in some configurations: WARNING: vmlinux.o(.text+0x85bae4): Section mismatch in reference from the function ixp4xx_irq_setup() to the function .init.text:set_handle_irq() The function ixp4xx_irq_setup() references the function __init set_handle_irq(). This is often because ixp4xx_irq_setup lacks a __init annotation or the annotation of set_handle_irq is wrong. I suspect it normally gets inlined, so we get no such warning, but clang makes this obvious when the function is left out of line. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-17 15:24:31 +03:00
static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
void __iomem *irqbase,
struct fwnode_handle *fwnode,
bool is_356)
irqchip: Add driver for IXP4xx The IXP4xx (arch/arm/mach-ixp4xx) is an old Intel XScale platform that has very wide deployment and use. As part of modernizing the platform, we need to implement a proper irqchip in the irqchip subsystem. The IXP4xx irqchip is tightly jotted together with the GPIO controller, and whereas in the past we would deal with this complex logic by adding necessarily different code, we can nowadays modernize it using a hierarchical irqchip. The actual IXP4 irqchip is a simple active low level IRQ controller, whereas the GPIO functionality resides in a different memory area and adds edge trigger support for the interrupts. The interrupts from GPIO lines 0..12 are 1:1 mapped to a fixed set of hardware IRQs on this IRQchip, so we expect the child GPIO interrupt controller to go in and allocate descriptors for these interrupts. For the other interrupts, as we do not yet have DT support for this platform, we create a linear irqdomain and then go in and allocate the IRQs that the legacy boards use. This code will be removed on the DT probe path when we add DT support to the platform. We add some translation code for supporting DT translations for the fwnodes, but we leave most of that for later. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-25 18:41:25 +03:00
{
int nr_irqs;
ixi->irqbase = irqbase;
ixi->is_356 = is_356;
/* Route all sources to IRQ instead of FIQ */
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);
/* Disable all interrupts */
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);
if (is_356) {
/* Route upper 32 sources to IRQ instead of FIQ */
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);
/* Disable upper 32 interrupts */
__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);
nr_irqs = 64;
} else {
nr_irqs = 32;
}
ixi->irqchip.name = "IXP4xx";
ixi->irqchip.irq_mask = ixp4xx_irq_mask;
ixi->irqchip.irq_unmask = ixp4xx_irq_unmask;
ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;
ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,
&ixp4xx_irqdomain_ops,
ixi);
if (!ixi->domain) {
pr_crit("IXP4XX: can not add primary irqdomain\n");
return -ENODEV;
}
set_handle_irq(ixp4xx_handle_irq);
return 0;
}
irq/gpio: ixp4xx: Drop boardfile probe path The boardfiles for IXP4xx have been deleted. Delete all the quirks and code dealing with that boot path and rely solely on device tree boot. Fix some missing static keywords that the kernel test robot was complaining about while we're at it. Cc: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2022-04-21 23:06:54 +03:00
static int __init ixp4xx_of_init_irq(struct device_node *np,
struct device_node *parent)
irqchip: ixp4xx: Add OF initialization support This adds support for probing and settin up the IXP4xx irqchip from device tree. Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-27 16:05:53 +03:00
{
struct ixp4xx_irq *ixi = &ixirq;
void __iomem *base;
struct fwnode_handle *fwnode;
bool is_356;
int ret;
base = of_iomap(np, 0);
if (!base) {
pr_crit("IXP4XX: could not ioremap interrupt controller\n");
return -ENODEV;
}
fwnode = of_node_to_fwnode(np);
/* These chip variants have 64 interrupts */
is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||
of_device_is_compatible(np, "intel,ixp45x-interrupt") ||
of_device_is_compatible(np, "intel,ixp46x-interrupt");
ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
if (ret)
pr_crit("IXP4XX: failed to set up irqchip\n");
return ret;
}
IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
ixp4xx_of_init_irq);
IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
ixp4xx_of_init_irq);
IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
ixp4xx_of_init_irq);
IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",
ixp4xx_of_init_irq);
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