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/*
* Copyright ( C ) 2002 Momentum Computer , Inc .
* Author : Matthew Dharm , mdharm @ momenco . com
*
* Based on work by :
* Copyright ( C ) 2000 RidgeRun , Inc .
* Author : RidgeRun , Inc .
* glonnon @ ridgerun . com , skranz @ ridgerun . com , stevej @ ridgerun . com
*
* Copyright 2001 MontaVista Software Inc .
* Author : Jun Sun , jsun @ mvista . com or jsun @ junsun . net
*
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* Copyright ( C ) 2000 , 01 , 06 Ralf Baechle ( ralf @ linux - mips . org )
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*
* This program is free software ; you can redistribute it and / or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation ; either version 2 of the License , or ( at your
* option ) any later version .
*
* THIS SOFTWARE IS PROVIDED ` ` AS IS ' ' AND ANY EXPRESS OR IMPLIED
* WARRANTIES , INCLUDING , BUT NOT LIMITED TO , THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED . IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT , INDIRECT ,
* INCIDENTAL , SPECIAL , EXEMPLARY , OR CONSEQUENTIAL DAMAGES ( INCLUDING , BUT
* NOT LIMITED TO , PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES ; LOSS OF
* USE , DATA , OR PROFITS ; OR BUSINESS INTERRUPTION ) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY , WHETHER IN CONTRACT , STRICT LIABILITY , OR TORT
* ( INCLUDING NEGLIGENCE OR OTHERWISE ) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE , EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE .
*
* You should have received a copy of the GNU General Public License along
* with this program ; if not , write to the Free Software Foundation , Inc . ,
* 675 Mass Ave , Cambridge , MA 0213 9 , USA .
*/
# include <linux/init.h>
# include <linux/interrupt.h>
# include <linux/signal.h>
# include <linux/types.h>
# include <asm/irq_cpu.h>
# include <asm/mipsregs.h>
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# include <asm/time.h>
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asmlinkage void plat_irq_dispatch ( void )
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{
unsigned int pending = read_c0_cause ( ) & read_c0_status ( ) ;
if ( pending & STATUSF_IP0 )
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do_IRQ ( 0 ) ;
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else if ( pending & STATUSF_IP1 )
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do_IRQ ( 1 ) ;
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else if ( pending & STATUSF_IP2 )
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do_IRQ ( 2 ) ;
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else if ( pending & STATUSF_IP3 )
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do_IRQ ( 3 ) ;
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else if ( pending & STATUSF_IP4 )
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do_IRQ ( 4 ) ;
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else if ( pending & STATUSF_IP5 )
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do_IRQ ( 5 ) ;
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else if ( pending & STATUSF_IP6 )
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do_IRQ ( 6 ) ;
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else if ( pending & STATUSF_IP7 )
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ll_timer_interrupt ( 7 ) ;
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else {
/*
* Now look at the extended interrupts
*/
pending = ( read_c0_cause ( ) & ( read_c0_intcontrol ( ) < < 8 ) ) > > 16 ;
if ( pending & STATUSF_IP8 )
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ll_mv64340_irq ( ) ;
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}
}
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static struct irqaction cascade_mv64340 = {
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no_action , IRQF_DISABLED , CPU_MASK_NONE , " MV64340-Cascade " , NULL , NULL
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} ;
void __init arch_init_irq ( void )
{
/*
* Clear all of the interrupts while we change the able around a bit .
* int - handler is not on bootstrap
*/
clear_c0_status ( ST0_IM ) ;
mips_cpu_irq_init ( 0 ) ;
rm7k_cpu_irq_init ( 8 ) ;
/* set up the cascading interrupts */
setup_irq ( 8 , & cascade_mv64340 ) ;
mv64340_irq_init ( 16 ) ;
set_c0_status ( ST0_IM ) ;
}