iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
linux/arch/powerpc/boot/dts/fsl/p1020rdb.dts

63 lines
1.4 KiB
Plaintext
Raw Normal View History

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-27 08:55:01 +02:00
// SPDX-License-Identifier: GPL-2.0-or-later
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
/*
* P1020 RDB Device Tree Source
*
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 10:17:45 +05:30
* Copyright 2009-2011 Freescale Semiconductor Inc.
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
*/
powerpc/fsl: Move Freescale device tree files into fsl folder It makes no sense that some Freescale device tree files are in fsl directory while some others not. This patch move Freescale device tree files into fsl folder. To do that the following two steps are made: - Move Freescale device tree files into fsl folder. - Update the include path in these files from "fsl/*.dtsi" to "*.dtsi". Please add "fsl/" prefix when you make dtb using Makefile. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> [scottwood: fixed cuImage rule] Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-09-18 12:00:24 +08:00
/include/ "p1020si-pre.dtsi"
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
/ {
powerpc/85xx: P1020 DTS : re-organize dts files Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts files for P1020 based systems to use dtsi file Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Grant Likely <grant.likelY@secretlab.ca> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-07 14:40:55 +05:30
model = "fsl,P1020RDB";
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
compatible = "fsl,P1020RDB";
memory {
device_type = "memory";
};
powerpc/85xx: Rework P1020RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 02:21:09 -05:00
board_lbc: lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xffa00000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000>;
};
powerpc/85xx: Rework P1020RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 02:21:09 -05:00
board_soc: soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 10:17:45 +05:30
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
powerpc/85xx: Rework PCI nodes on P1020RDB * Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-19 10:58:05 -05:00
reg = <0 0xffe09000 0 0x1000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
powerpc/85xx: Rework PCI nodes on P1020RDB * Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-19 10:58:05 -05:00
reg = <0 0xffe0a000 0 0x1000>;
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 10:17:45 +05:30
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
pcie@0 {
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 10:17:45 +05:30
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 09:50:28 +05:30
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
powerpc/85xx: Rework P1020RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 02:21:09 -05:00
/include/ "p1020rdb.dtsi"
powerpc/fsl: Move Freescale device tree files into fsl folder It makes no sense that some Freescale device tree files are in fsl directory while some others not. This patch move Freescale device tree files into fsl folder. To do that the following two steps are made: - Move Freescale device tree files into fsl folder. - Update the include path in these files from "fsl/*.dtsi" to "*.dtsi". Please add "fsl/" prefix when you make dtb using Makefile. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> [scottwood: fixed cuImage rule] Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-09-18 12:00:24 +08:00
/include/ "p1020si-post.dtsi"
Reference in New Issue Copy Permalink