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#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 1994, 95, 96, 2003 by Ralf Baechle
# DECStation modifications by Paul M. Antoine, 1996
# Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
#
# This file is included by the global makefile so that you can add your own
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# architecture-specific flags and dependencies.
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#
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archscripts : scripts_basic
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$( Q) $( MAKE) $( build) = arch/mips/tools elf-entry
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i f e q ( $( CONFIG_CPU_LOONGSON 3_WORKAROUNDS ) , y )
$( Q) $( MAKE) $( build) = arch/mips/tools loongson3-llsc-check
e n d i f
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$( Q) $( MAKE) $( build) = arch/mips/boot/tools relocs
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KBUILD_DEFCONFIG := 32r2el_defconfig
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KBUILD_DTBS := dtbs
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#
# Select the object file format to substitute into the linker script.
#
i f d e f C O N F I G _ C P U _ L I T T L E _ E N D I A N
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32bit-tool-archpref = mipsel
64bit-tool-archpref = mips64el
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32bit-bfd = elf32-tradlittlemips
64bit-bfd = elf64-tradlittlemips
32bit-emul = elf32ltsmip
64bit-emul = elf64ltsmip
e l s e
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32bit-tool-archpref = mips
64bit-tool-archpref = mips64
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32bit-bfd = elf32-tradbigmips
64bit-bfd = elf64-tradbigmips
32bit-emul = elf32btsmip
64bit-emul = elf64btsmip
e n d i f
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i f d e f C O N F I G _ 3 2 B I T
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tool-archpref = $( 32bit-tool-archpref)
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UTS_MACHINE := mips
e n d i f
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i f d e f C O N F I G _ 6 4 B I T
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tool-archpref = $( 64bit-tool-archpref)
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UTS_MACHINE := mips64
e n d i f
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i f d e f c r o s s _ c o m p i l i n g
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ifeq ( $( CROSS_COMPILE) ,)
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CROSS_COMPILE := $( call cc-cross-prefix, $( tool-archpref) -linux- $( tool-archpref) -linux-gnu- $( tool-archpref) -unknown-linux-gnu-)
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endif
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e n d i f
MIPS: Tracing: Make function graph tracer work with -mmcount-ra-address
That thread "MIPS: Add option to pass return address location to
_mcount" from "David Daney <ddaney@caviumnetworks.com>" have added a new
option -mmcount-ra-address to gcc(4.5) for MIPS to transfer the location
of the return address to _mcount.
Benefit from this new feature, function graph tracer on MIPS will be
easier and safer to hijack the return address of the kernel function,
which will save some overhead and make the whole thing more reliable.
In this patch, at first, try to enable the option -mmcount-ra-address in
arch/mips/Makefile with cc-option, if gcc support it, it will be
enabled, otherwise, no side effect.
and then, we need to support this new option of gcc 4.5 and also support
the old gcc versions.
with _mcount in the old gcc versions, it's not easy to get the location
of return address(tracing: add function graph tracer support for MIPS),
so, we do it in a C function: ftrace_get_parent_addr(ftrace.c), but
with -mmcount-ra-address, only several instructions need to get what
we want, so, I put into asm(mcount.S). and also, as the $12(t0) is
used by -mmcount-ra-address for transferring the localtion of return
address to _mcount, we need to save it into the stack and restore it
when enabled dynamic function tracer, 'Cause we have called
"ftrace_call" before "ftrace_graph_caller", which may destroy
$12(t0).
(Thanks to David for providing that -mcount-ra-address and giving the
idea of KBUILD_MCOUNT_RA_ADDRESS, both of them have made the whole
thing more beautiful!)
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Nicholas Mc Guire <der.herr@hofr.at>
Cc: zhangfx@lemote.com
Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/681/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-20 15:34:38 +03:00
i f d e f C O N F I G _ F U N C T I O N _ G R A P H _ T R A C E R
ifndef KBUILD_MCOUNT_RA_ADDRESS
ifeq ( $( call cc-option-yn,-mmcount-ra-address) , y)
cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
endif
endif
e n d i f
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cflags-y += $( call cc-option, -mno-check-zero-division)
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i f d e f C O N F I G _ 3 2 B I T
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ld-emul = $( 32bit-emul)
vmlinux-32 = vmlinux
vmlinux-64 = vmlinux.64
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cflags-y += -mabi= 32
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e n d i f
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i f d e f C O N F I G _ 6 4 B I T
ld-emul = $( 64bit-emul)
vmlinux-32 = vmlinux.32
vmlinux-64 = vmlinux
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cflags-y += -mabi= 64
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e n d i f
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all-$(CONFIG_BOOT_ELF32) := $( vmlinux-32)
all-$(CONFIG_BOOT_ELF64) := $( vmlinux-64)
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all-$(CONFIG_SYS_SUPPORTS_ZBOOT) += vmlinuz
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#
# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
# code since it only slows down the whole thing. At some point we might make
# use of global pointer optimizations but their use of $28 conflicts with
# the current pointer optimization.
#
# The DECStation requires an ECOFF kernel for remote booting, other MIPS
# machines may also. Since BFD is incredibly buggy with respect to
# crossformat linking we rely on the elf2ecoff tool for format conversion.
#
cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
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cflags-y += -msoft-float -Wa,-msoft-float
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LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
kbuild: allow assignment to {A,C,LD}FLAGS_MODULE on the command line
It is now possible to assign options to AS, CC and LD
on the command line - which is only used when building modules.
{A,C,LD}FLAGS_MODULE was all used both in the top-level Makefile
in the arch makefiles, thus users had no way to specify
additional options to AS, CC, LD when building modules
without overriding the original value.
Introduce a new set of variables KBUILD_{A,C,LD}FLAGS_MODULE
that is used by arch specific files and free up
{A,C,LD}FLAGS_MODULE so they can be assigned on
the command line.
All arch Makefiles that used the old variables has been updated.
Note: Previously we had a MODFLAGS variable for both
AS and CC. But in favour of consistency this was dropped.
So in some cases arch Makefile has one assignmnet replaced by
two assignmnets.
Note2: MODFLAGS was not documented and is dropped
without any notice. I do not expect much/any breakage
from this.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Cc: Denys Vlasenko <vda.linux@googlemail.com>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Chen Liqin <liqin.chen@sunplusct.com>
Acked-by: Mike Frysinger <vapier@gentoo.org> [blackfin]
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> [avr32]
Signed-off-by: Michal Marek <mmarek@suse.cz>
2010-07-28 19:33:09 +04:00
KBUILD_AFLAGS_MODULE += -mlong-calls
KBUILD_CFLAGS_MODULE += -mlong-calls
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i f e q ( $( CONFIG_RELOCATABLE ) , y )
LDFLAGS_vmlinux += --emit-relocs
e n d i f
2006-06-07 16:25:37 +04:00
cflags-y += -ffreestanding
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cflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -EL
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cflags-$(CONFIG_SB1XXX_CORELIS) += $( call cc-option,-mno-sched-prolog) \
-fno-omit-frame-pointer
2017-01-29 06:24:16 +03:00
# Some distribution-specific toolchains might pass the -fstack-check
# option during the build, which adds a simple stack-probe at the beginning
# of every function. This stack probe is to ensure that there is enough
# stack space, else a SEGV is generated. This is not desirable for MIPS
# as kernel stacks are small, placed in unmapped virtual memory, and do not
# grow when overflowed. Especially on SGI IP27 platforms, this check will
# lead to a NULL pointer dereference in _raw_spin_lock_irq.
#
# In disassembly, this stack probe appears at the top of a function as:
# sd zero,<offset>(sp)
# Where <offset> is a negative value.
#
cflags-y += -fno-stack-check
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# binutils from v2.35 when built with --enable-mips-fix-loongson3-llsc=yes,
# supports an -mfix-loongson3-llsc flag which emits a sync prior to each ll
# instruction to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h
# for a description).
#
# We disable this in order to prevent the assembler meddling with the
# instruction that labels refer to, ie. if we label an ll instruction:
#
# 1: ll v0, 0(a0)
#
# ...then with the assembler fix applied the label may actually point at a sync
# instruction inserted by the assembler, and if we were using the label in an
# exception table the table would no longer contain the address of the ll
# instruction.
#
# Avoid this by explicitly disabling that assembler behaviour.
#
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cflags-y += $( call cc-option,-Wa$( comma) -mno-fix-loongson3-llsc,)
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#
# CPU-dependent compiler/assembler options for optimization.
#
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cflags-$(CONFIG_CPU_R3000) += -march= r3000
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cflags-$(CONFIG_CPU_R4300) += -march= r4300 -Wa,--trap
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cflags-$(CONFIG_CPU_R4X00) += -march= r4600 -Wa,--trap
cflags-$(CONFIG_CPU_TX49XX) += -march= r4600 -Wa,--trap
2018-06-19 03:37:59 +03:00
cflags-$(CONFIG_CPU_MIPS32_R1) += -march= mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march= mips32r2 -Wa,--trap
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 17:07:14 +03:00
cflags-$(CONFIG_CPU_MIPS32_R5) += -march= mips32r5 -Wa,--trap -modd-spreg
MIPS: build: Fix "-modd-spreg" switch usage when compiling for mips32r6
Add "-modd-spreg" when compiling the kernel for mips32r6 target.
This makes sure the kernel builds properly even with toolchains that
use "-mno-odd-spreg" by default. This is the case with Android gcc.
Prior to this patch, kernel builds using gcc for Android failed with
following error messages, if target architecture is set to mips32r6:
arch/mips/kernel/r4k_switch.S: Assembler messages:
.../r4k_switch.S:210: Error: float register should be even, was 1
.../r4k_switch.S:212: Error: float register should be even, was 3
.../r4k_switch.S:214: Error: float register should be even, was 5
.../r4k_switch.S:216: Error: float register should be even, was 7
.../r4k_switch.S:218: Error: float register should be even, was 9
.../r4k_switch.S:220: Error: float register should be even, was 11
.../r4k_switch.S:222: Error: float register should be even, was 13
.../r4k_switch.S:224: Error: float register should be even, was 15
.../r4k_switch.S:226: Error: float register should be even, was 17
.../r4k_switch.S:228: Error: float register should be even, was 19
.../r4k_switch.S:230: Error: float register should be even, was 21
.../r4k_switch.S:232: Error: float register should be even, was 23
.../r4k_switch.S:234: Error: float register should be even, was 25
.../r4k_switch.S:236: Error: float register should be even, was 27
.../r4k_switch.S:238: Error: float register should be even, was 29
.../r4k_switch.S:240: Error: float register should be even, was 31
make[2]: *** [arch/mips/kernel/r4k_switch.o] Error 1
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Cc: James.Hogan@imgtec.com
Cc: Paul.Burton@imgtec.com
Cc: Raghu.Gandham@imgtec.com
Cc: Leonid.Yegoshin@imgtec.com
Cc: Douglas.Leung@imgtec.com
Cc: Petar.Jovanovic@imgtec.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-06-19 18:50:09 +03:00
cflags-$(CONFIG_CPU_MIPS32_R6) += -march= mips32r6 -Wa,--trap -modd-spreg
2018-06-19 03:37:59 +03:00
cflags-$(CONFIG_CPU_MIPS64_R1) += -march= mips64 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R2) += -march= mips64r2 -Wa,--trap
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 17:07:14 +03:00
cflags-$(CONFIG_CPU_MIPS64_R5) += -march= mips64r5 -Wa,--trap
2014-10-27 13:34:11 +03:00
cflags-$(CONFIG_CPU_MIPS64_R6) += -march= mips64r6 -Wa,--trap
mips: Add MIPS Warrior P5600 support
This is a MIPS32 Release 5 based IP core with XPA, EVA, dual/quad issue
exec pipes, MMU with two-levels TLB, UCA, MSA, MDU core level features
and system level features like up to six P5600 calculation cores, CM2
with L2 cache, IOCU/IOMMU (though might be unused depending on the
system-specific IP core configuration), GIC, CPC, virtualisation module,
eJTAG and PDtrace.
As being MIPS32 Release 5 based core it provides all the features
available by the CPU_MIPS32_R5 config, while adding a few more like
UCA attribute support, availability of CPU-freq (by means of L2/CM
clock ratio setting), EI/VI GIC modes detection at runtime.
In addition to this if P5600 architecture is enabled modern GNU GCC
provides a specific tuning for P5600 processors with respect to the
classic MIPS32 Release 5. First of all branch-likely avoidance is
activated only when the code is compiled with the speed optimization
(avoidance is always enabled for the pure MIPS32 Release 5
architecture). Secondly the madd/msub avoidance is enabled since
madd/msub utilization isn't profitable due to overhead of getting the
result out of the HI/LO registers. Multiply-accumulate instructions are
activated and utilized together with the necessary code reorder when
multiply-add/multiply-subtract statements are met. Finally load/store
bonding is activated by default. All of these optimizations may make
the code relatively faster than if just MIP32 release 5 architecture
was requested.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 17:07:15 +03:00
cflags-$(CONFIG_CPU_P5600) += -march= p5600 -Wa,--trap -modd-spreg
2006-03-08 14:35:00 +03:00
cflags-$(CONFIG_CPU_R5000) += -march= r5000 -Wa,--trap
2008-10-23 20:27:57 +04:00
cflags-$(CONFIG_CPU_R5500) += $( call cc-option,-march= r5500,-march= r5000) \
-Wa,--trap
2006-04-01 23:43:58 +04:00
cflags-$(CONFIG_CPU_NEVADA) += $( call cc-option,-march= rm5200,-march= r5000) \
2005-04-17 02:20:36 +04:00
-Wa,--trap
2006-03-08 14:35:00 +03:00
cflags-$(CONFIG_CPU_RM7000) += $( call cc-option,-march= rm7000,-march= r5000) \
2005-04-17 02:20:36 +04:00
-Wa,--trap
2014-06-29 03:59:35 +04:00
cflags-$(CONFIG_CPU_SB1) += $( call cc-option,-march= sb1,-march= r5000) \
2005-04-17 02:20:36 +04:00
-Wa,--trap
2014-06-29 03:59:35 +04:00
cflags-$(CONFIG_CPU_SB1) += $( call cc-option,-mno-mdmx)
cflags-$(CONFIG_CPU_SB1) += $( call cc-option,-mno-mips3d)
2006-03-08 14:35:00 +03:00
cflags-$(CONFIG_CPU_R10000) += $( call cc-option,-march= r10000,-march= r8000) \
2005-04-17 02:20:36 +04:00
-Wa,--trap
2008-12-12 02:33:28 +03:00
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $( call cc-option,-march= octeon) -Wa,--trap
i f e q ( , $( findstring march =octeon , $ ( cflags -$ ( CONFIG_CPU_CAVIUM_OCTEON ) ) ) )
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march= octeon
e n d i f
2010-10-08 03:03:53 +04:00
cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
2011-11-16 05:25:40 +04:00
cflags-$(CONFIG_CPU_BMIPS) += -march= mips32 -Wa,-mips32 -Wa,--trap
2005-04-17 02:20:36 +04:00
MIPS: Loongson: Fix build error when make modules_install
After commit 0e96ea5c3eb5904e5dc2f ("MIPS: Loongson64: Clean up use of
cc-ifversion") we get a build error when make modules_install:
cc1: error: '-mloongson-mmi' must be used with '-mhard-float'
The reason is when make modules_install, 'call cc-option' doesn't work
in $(KBUILD_CFLAGS) of 'CHECKFLAGS'. Then there is no -mno-loongson-mmi
applied and -march=loongson3a enable MMI instructions.
To be detail, the error message comes from the CHECKFLAGS invocation of
$(CC) but it has no impact on the final result of make modules_install,
it is purely a cosmetic issue. The error occurs because cc-option is
defined in scripts/Makefile.compiler, which is not included in Makefile
when running 'make modules_install', as install targets are not supposed
to require the compiler; see commit 805b2e1d427aab4b ("kbuild: include
Makefile.compiler only when compiler is needed"). As a result, the call
to check for '-mno-loongson-mmi' just never happens.
Fix this by partially reverting to the old logic, use 'call cc-option'
to conditionally apply -march=loongson3a and -march=mips64r2.
By the way, Loongson-2E/2F is also broken in commit 13ceb48bc19c563e05f4
("MIPS: Loongson2ef: Remove unnecessary {as,cc}-option calls") so fix it
together.
Fixes: 13ceb48bc19c563e05f4 ("MIPS: Loongson2ef: Remove unnecessary {as,cc}-option calls")
Fixes: 0e96ea5c3eb5904e5dc2 ("MIPS: Loongson64: Clean up use of cc-ifversion")
Cc: stable@vger.kernel.org
Cc: Feiyang Chen <chenfeiyang@loongson.cn>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-28 14:08:47 +03:00
cflags-$(CONFIG_CPU_LOONGSON2E) += $( call cc-option,-march= loongson2e) -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2F) += $( call cc-option,-march= loongson2f) -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON64) += $( call cc-option,-march= loongson3a,-march= mips64r2) -Wa,--trap
2023-04-04 12:33:47 +03:00
# Some -march= flags enable MMI instructions, and GCC complains about that
# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
cflags-$(CONFIG_CPU_LOONGSON2EF) += $( call cc-option,-mno-loongson-mmi)
cflags-$(CONFIG_CPU_LOONGSON64) += $( call cc-option,-mno-loongson-mmi)
2007-10-23 15:43:11 +04:00
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $( call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $( call cc-option,-mfix-r4400,)
cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $( call cc-option,-mno-daddi,)
2023-04-04 12:33:47 +03:00
i f d e f C O N F I G _ C P U _ L O O N G S O N 2 F _ W O R K A R O U N D S
cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
e n d i f
#
# Some versions of binutils, not currently mainline as of 2019/02/04, support
# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
# description).
#
# We disable this in order to prevent the assembler meddling with the
# instruction that labels refer to, ie. if we label an ll instruction:
#
# 1: ll v0, 0(a0)
#
# ...then with the assembler fix applied the label may actually point at a sync
# instruction inserted by the assembler, and if we were using the label in an
# exception table the table would no longer contain the address of the ll
# instruction.
#
# Avoid this by explicitly disabling that assembler behaviour. If upstream
# binutils does not merge support for the flag then we can revisit & remove
# this later - for now it ensures vendor toolchains don't cause problems.
#
cflags-$(CONFIG_CPU_LOONGSON64) += $( call as-option,-Wa$( comma) -mno-fix-loongson3-llsc,)
2007-10-23 15:43:11 +04:00
2015-02-02 18:41:01 +03:00
# For smartmips configurations, there are hundreds of warnings due to ISA overrides
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards
# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
# similar directives in the kernel will spam the build logs with the following warnings:
# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
# or
# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
# been fixed properly.
2015-04-02 16:42:52 +03:00
mips-cflags := $( cflags-y)
i f e q ( $( CONFIG_CPU_HAS_SMARTMIPS ) , y )
smartmips-ase := $( call cc-option-yn,$( mips-cflags) -msmartmips)
cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn
e n d i f
i f e q ( $( CONFIG_CPU_MICROMIPS ) , y )
micromips-ase := $( call cc-option-yn,$( mips-cflags) -mmicromips)
cflags-$(micromips-ase) += -mmicromips
e n d i f
2015-02-02 18:41:01 +03:00
i f e q ( $( CONFIG_CPU_HAS_MSA ) , y )
2015-04-02 16:42:52 +03:00
toolchain-msa := $( call cc-option-yn,$( mips-cflags) -mhard-float -mfp64 -Wa$( comma) -mmsa)
2015-02-02 18:41:01 +03:00
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
e n d i f
2016-05-16 14:50:04 +03:00
toolchain-virt := $( call cc-option-yn,$( mips-cflags) -mvirt)
cflags-$(toolchain-virt) += -DTOOLCHAIN_SUPPORTS_VIRT
2017-11-22 14:30:30 +03:00
# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which
# only warns
xpa-cflags-y := $( mips-cflags)
xpa-cflags-$(micromips-ase) += -mmicromips -Wa$( comma) -fatal-warnings
toolchain-xpa := $( call cc-option-yn,$( xpa-cflags-y) -mxpa)
cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA
2018-02-10 01:11:06 +03:00
toolchain-crc := $( call cc-option-yn,$( mips-cflags) -Wa$( comma) -mcrc)
cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC
2018-10-15 21:26:12 +03:00
toolchain-dsp := $( call cc-option-yn,$( mips-cflags) -Wa$( comma) -mdsp)
cflags-$(toolchain-dsp) += -DTOOLCHAIN_SUPPORTS_DSP
2019-02-02 04:43:27 +03:00
toolchain-ginv := $( call cc-option-yn,$( mips-cflags) -Wa$( comma) -mginv)
cflags-$(toolchain-ginv) += -DTOOLCHAIN_SUPPORTS_GINV
2015-02-02 18:41:01 +03:00
2005-04-17 02:20:36 +04:00
#
# Firmware support
#
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libs-$(CONFIG_FW_ARC) += arch/mips/fw/arc/
libs-$(CONFIG_FW_CFE) += arch/mips/fw/cfe/
libs-$(CONFIG_FW_SNIPROM) += arch/mips/fw/sni/
2008-01-05 01:31:07 +03:00
libs-y += arch/mips/fw/lib/
2005-04-17 02:20:36 +04:00
2010-02-26 15:57:12 +03:00
#
# Kernel compression
#
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i f d e f C O N F I G _ S Y S _ S U P P O R T S _ Z B O O T
2010-02-26 15:57:12 +03:00
COMPRESSION_FNAME = vmlinuz
e l s e
COMPRESSION_FNAME = vmlinux
e n d i f
2005-04-17 02:20:36 +04:00
#
# Board-dependent options and extra files
#
2021-07-24 21:35:56 +03:00
i n c l u d e $( srctree ) / a r c h / m i p s / K b u i l d . p l a t f o r m s
2009-06-24 13:12:57 +04:00
2012-10-25 18:23:31 +04:00
i f d e f C O N F I G _ P H Y S I C A L _ S T A R T
2013-01-22 15:59:30 +04:00
load-y = $( CONFIG_PHYSICAL_START)
2012-10-25 18:23:31 +04:00
e n d i f
2017-08-08 02:16:47 +03:00
2018-08-29 21:01:30 +03:00
entry-y = $( shell $( objtree) /arch/mips/tools/elf-entry vmlinux)
2008-09-16 21:48:51 +04:00
cflags-y += -I$( srctree) /arch/mips/include/asm/mach-generic
2005-04-17 02:20:36 +04:00
drivers-$(CONFIG_PCI) += arch/mips/pci/
2007-02-15 14:06:48 +03:00
#
# Automatically detect the build format. By default we choose
# the elf format according to the load address.
# We can always force a build with a 64-bits symbol format by
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# passing 'KBUILD_SYM32=no' option to the make's command line.
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#
i f d e f C O N F I G _ 6 4 B I T
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ifndef KBUILD_SYM32
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ifeq ( $( shell expr $( load-y) \< 0xffffffff80000000) , 0)
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KBUILD_SYM32 = y
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endif
endif
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ifeq ( $( KBUILD_SYM32) $( call cc-option-yn,-msym32) , yy)
cflags-y += -msym32 -DKBUILD_64BIT_SYM32
else
ifeq ( $( CONFIG_CPU_DADDI_WORKAROUNDS) , y)
$( error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32)
2007-09-27 18:26:40 +04:00
endif
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endif
e n d i f
2020-05-06 08:52:45 +03:00
# When linking a 32-bit executable the LLVM linker cannot cope with a
# 32-bit load address that has been sign-extended to 64 bits. Simply
# remove the upper 32 bits then, as it is safe to do so with other
# linkers.
i f d e f C O N F I G _ 6 4 B I T
load-ld = $( load-y)
e l s e
load-ld = $( subst 0xffffffff,0x,$( load-y) )
e n d i f
2007-10-15 23:59:31 +04:00
KBUILD_AFLAGS += $( cflags-y)
2009-09-20 14:28:22 +04:00
KBUILD_CFLAGS += $( cflags-y)
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KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS= $( load-y) -DLINKER_LOAD_ADDRESS= $( load-ld)
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KBUILD_CPPFLAGS += -DDATAOFFSET= $( if $( dataoffset-y) ,$( dataoffset-y) ,0)
2005-04-17 02:20:36 +04:00
2013-08-30 19:42:41 +04:00
bootvars-y = VMLINUX_LOAD_ADDRESS = $( load-y) \
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LINKER_LOAD_ADDRESS = $( load-ld) \
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VMLINUX_ENTRY_ADDRESS = $( entry-y) \
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PLATFORM = " $( platform-y) " \
ITS_INPUTS = " $( its-y) "
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i f d e f C O N F I G _ 3 2 B I T
bootvars-y += ADDR_BITS = 32
e n d i f
i f d e f C O N F I G _ 6 4 B I T
bootvars-y += ADDR_BITS = 64
e n d i f
2013-08-30 19:42:41 +04:00
2017-08-10 21:27:39 +03:00
# This is required to get dwarf unwinding tables into .debug_frame
# instead of .eh_frame so we don't discard them.
KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
2018-08-24 02:20:39 +03:00
KBUILD_LDFLAGS += -m $( ld-emul)
2005-04-17 02:20:36 +04:00
2006-03-08 14:35:00 +03:00
i f d e f C O N F I G _ M I P S
2023-06-01 21:38:24 +03:00
CHECKFLAGS += $( shell $( CC) $( KBUILD_CPPFLAGS) $( KBUILD_CFLAGS) -dM -E -x c /dev/null | \
2022-11-18 11:28:11 +03:00
grep -E -vw '__GNUC_(MINOR_|PATCHLEVEL_)?_' | \
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sed -e "s/^\#define /-D'/" -e "s/ /'='/" -e " s/ $$ /'/ " -e 's/\$$/&&/g' )
2006-03-08 14:35:00 +03:00
e n d i f
2005-04-17 02:20:36 +04:00
OBJCOPYFLAGS += --remove-section= .reginfo
libs-y += arch/mips/lib/
2018-11-08 02:14:10 +03:00
libs-$(CONFIG_MIPS_FP_SUPPORT) += arch/mips/math-emu/
2005-04-17 02:20:36 +04:00
2019-11-08 15:22:17 +03:00
drivers-y += arch/mips/crypto/
2005-04-17 02:20:36 +04:00
2009-06-04 16:27:10 +04:00
# suspend and hibernation support
drivers-$(CONFIG_PM) += arch/mips/power/
2013-08-30 19:42:40 +04:00
# boot image targets (arch/mips/boot/)
boot-y := vmlinux.bin
boot-y += vmlinux.ecoff
boot-y += vmlinux.srec
2013-08-30 19:42:42 +04:00
boot-y += uImage
2015-02-16 18:13:11 +03:00
boot-y += uImage.bin
boot-y += uImage.bz2
2013-08-30 19:42:42 +04:00
boot-y += uImage.gz
2015-02-16 18:13:11 +03:00
boot-y += uImage.lzma
boot-y += uImage.lzo
2016-10-05 20:18:19 +03:00
boot-y += vmlinux.itb
boot-y += vmlinux.gz.itb
boot-y += vmlinux.bz2.itb
boot-y += vmlinux.lzma.itb
boot-y += vmlinux.lzo.itb
2013-08-30 19:42:40 +04:00
# compressed boot image targets (arch/mips/boot/compressed/)
bootz-y := vmlinuz
bootz-y += vmlinuz.bin
bootz-y += vmlinuz.ecoff
bootz-y += vmlinuz.srec
2016-10-31 17:19:55 +03:00
bootz-y += uzImage.bin
2020-11-01 18:13:01 +03:00
bootz-y += vmlinuz.itb
2013-08-30 19:42:40 +04:00
2005-04-17 02:20:36 +04:00
#
# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
# convert to ECOFF using elf2ecoff.
#
2010-11-09 19:26:34 +03:00
quiet_cmd_32 = OBJCOPY $@
cmd_32 = $( OBJCOPY) -O $( 32bit-bfd) $( OBJCOPYFLAGS) $< $@
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vmlinux.32 : vmlinux
2010-11-09 19:26:34 +03:00
$( call cmd,32)
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#
# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
# ELF files from 32-bit files by conversion.
#
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quiet_cmd_64 = OBJCOPY $@
cmd_64 = $( OBJCOPY) -O $( 64bit-bfd) $( OBJCOPYFLAGS) $< $@
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vmlinux.64 : vmlinux
2010-11-09 19:26:34 +03:00
$( call cmd,64)
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2019-06-13 11:52:50 +03:00
all : $( all -y ) $( KBUILD_DTBS )
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2010-05-30 18:28:03 +04:00
# boot
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$(boot-y) : $( vmlinux -32) FORCE
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$( Q) $( MAKE) $( build) = arch/mips/boot VMLINUX = $( vmlinux-32) \
$( bootvars-y) arch/mips/boot/$@
2005-04-17 02:20:36 +04:00
2013-09-11 14:34:48 +04:00
i f d e f C O N F I G _ S Y S _ S U P P O R T S _ Z B O O T
2010-05-30 18:28:03 +04:00
# boot/compressed
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$(bootz-y) : $( vmlinux -32) FORCE
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$( Q) $( MAKE) $( build) = arch/mips/boot/compressed \
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$( bootvars-y) 32bit-bfd= $( 32bit-bfd) arch/mips/boot/$@
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e l s e
vmlinuz : FORCE
@echo ' CONFIG_SYS_SUPPORTS_ZBOOT is not enabled'
/bin/false
e n d i f
2010-05-30 18:28:03 +04:00
2010-05-30 18:28:31 +04:00
CLEAN_FILES += vmlinux.32 vmlinux.64
2005-04-17 02:20:36 +04:00
2014-08-22 00:04:20 +04:00
# device-trees
2018-01-11 00:19:37 +03:00
core-y += arch/mips/boot/dts/
2014-08-22 00:04:21 +04:00
2007-05-29 19:38:07 +04:00
archprepare :
i f d e f C O N F I G _ M I P S 3 2 _ N 3 2
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@$( kecho) ' Checking missing-syscalls for N32'
2011-11-08 22:20:10 +04:00
$( Q) $( MAKE) $( build) = . missing-syscalls missing_syscalls_flags = "-mabi=n32"
2007-05-29 19:38:07 +04:00
e n d i f
i f d e f C O N F I G _ M I P S 3 2 _ O 3 2
2017-01-17 18:18:37 +03:00
@$( kecho) ' Checking missing-syscalls for O32'
2011-11-08 22:20:10 +04:00
$( Q) $( MAKE) $( build) = . missing-syscalls missing_syscalls_flags = "-mabi=32"
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e n d i f
2009-03-30 16:49:40 +04:00
install :
$( Q) install -D -m 755 vmlinux $( INSTALL_PATH) /vmlinux-$( KERNELRELEASE)
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i f d e f C O N F I G _ S Y S _ S U P P O R T S _ Z B O O T
2009-10-14 14:12:16 +04:00
$( Q) install -D -m 755 vmlinuz $( INSTALL_PATH) /vmlinuz-$( KERNELRELEASE)
2011-06-21 20:58:55 +04:00
e n d i f
2009-03-30 16:49:40 +04:00
$( Q) install -D -m 644 .config $( INSTALL_PATH) /config-$( KERNELRELEASE)
$( Q) install -D -m 644 System.map $( INSTALL_PATH) /System.map-$( KERNELRELEASE)
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archheaders :
$( Q) $( MAKE) $( build) = arch/mips/kernel/syscalls all
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d e f i n e a r c h h e l p
2009-03-30 16:49:40 +04:00
echo ' install - install kernel into $(INSTALL_PATH)'
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echo ' vmlinux.ecoff - ECOFF boot image'
echo ' vmlinux.bin - Raw binary boot image'
echo ' vmlinux.srec - SREC boot image'
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echo ' vmlinux.32 - 64-bit boot image wrapped in 32bits (IP22/IP32)'
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echo ' vmlinuz - Compressed boot(zboot) image'
echo ' vmlinuz.ecoff - ECOFF zboot image'
echo ' vmlinuz.bin - Raw binary zboot image'
echo ' vmlinuz.srec - SREC zboot image'
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echo ' uImage - U-Boot image'
2015-02-16 18:13:11 +03:00
echo ' uImage.bin - U-Boot image (uncompressed)'
echo ' uImage.bz2 - U-Boot image (bz2)'
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echo ' uImage.gz - U-Boot image (gzip)'
2015-02-16 18:13:11 +03:00
echo ' uImage.lzma - U-Boot image (lzma)'
echo ' uImage.lzo - U-Boot image (lzo)'
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echo ' uzImage.bin - U-Boot image (self-extracting)'
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echo
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echo ' These will be default as appropriate for a configured platform.'
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echo
echo ' If you are targeting a system supported by generic kernels you may'
echo ' configure the kernel for a given architecture target like so:'
echo
echo ' {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">'
echo
2018-02-09 19:11:58 +03:00
echo ' Where BOARDS is some subset of the following:'
for board in $( sort $( BOARDS) ) ; do echo " $$ {board} " ; done
echo
echo ' Specifically the following generic default configurations are'
echo ' supported:'
echo
$( foreach cfg,$( generic_defconfigs) ,
printf " %-24s - Build generic kernel for $( call describe_generic_defconfig,$( cfg) ) \n " $( cfg) ; )
echo
echo ' The following legacy default configurations have been converted to'
echo ' generic and can still be used:'
echo
$( foreach cfg,$( sort $( legacy_defconfigs) ) ,
printf " %-24s - Build $( $( cfg) -y) \n " $( cfg) ; )
echo
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echo ' Otherwise, the following default configurations are available:'
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e n d e f
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generic_config_dir = $( srctree) /arch/$( ARCH) /configs/generic
generic_defconfigs :=
#
# If the user generates a generic kernel configuration without specifying a
# list of boards to include the config fragments for, default to including all
# available board config fragments.
#
i f e q ( $( BOARDS ) , )
BOARDS = $( patsubst board-%.config,%,$( notdir $( wildcard $( generic_config_dir) /board-*.config) ) )
e n d i f
#
# Generic kernel configurations which merge generic_defconfig with the
# appropriate config fragments from arch/mips/configs/generic/, resulting in
# the ability to easily configure the kernel for a given architecture,
# endianness & set of boards without duplicating the needed configuration in
# hundreds of defconfig files.
#
d e f i n e g e n _ g e n e r i c _ d e f c o n f i g s
$( foreach bits ,$ ( 1) ,$ ( foreach rev ,$ ( 2) ,$ ( foreach endian ,$ ( 3) ,
target := $( bits) $( rev) $( filter el,$( endian) ) _defconfig
generic_defconfigs += $$ ( target)
$$ (target) : $( generic_config_dir ) /$( bits ) $( rev ) .config
$$ (target) : $( generic_config_dir ) /$( endian ) .config
) ) )
e n d e f
$( eval $ ( call gen_generic_defconfigs ,32 64,r 1 r 2 r 6,eb el ) )
$( eval $ ( call gen_generic_defconfigs ,micro 32,r 2,eb el ) )
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d e f i n e d e s c r i b e _ g e n e r i c _ d e f c o n f i g
$( subst 32r ,MIPS 32 r ,$ ( subst 64r ,MIPS 64 r ,$ ( subst el , little endian ,$ ( patsubst %_defconfig ,%,$ ( 1) ) ) ) )
e n d e f
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.PHONY : $( generic_defconfigs )
$(generic_defconfigs) :
$( Q) $( CONFIG_SHELL) $( srctree) /scripts/kconfig/merge_config.sh \
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-m -O $( objtree) $( srctree) /arch/$( ARCH) /configs/generic_defconfig $^ | \
grep -Ev '^#'
$( Q) cp $( KCONFIG_CONFIG) $( objtree) /.config.$@
$( Q) $( MAKE) -f $( srctree) /Makefile olddefconfig \
KCONFIG_CONFIG = $( objtree) /.config.$@ >/dev/null
$( Q) $( CONFIG_SHELL) $( srctree) /arch/$( ARCH) /tools/generic-board-config.sh \
$( srctree) $( objtree) $( objtree) /.config.$@ $( KCONFIG_CONFIG) \
" $( origin BOARDS) " $( BOARDS)
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$( Q) $( MAKE) -f $( srctree) /Makefile olddefconfig
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#
# Prevent generic merge_config rules attempting to merge single fragments
#
$(generic_config_dir)/%.config : ;
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#
# Prevent direct use of generic_defconfig, which is intended to be used as the
# basis of the various ISA-specific targets generated above.
#
.PHONY : generic_defconfig
generic_defconfig :
$( Q) echo "generic_defconfig is not intended for direct use, but should instead be"
$( Q) echo "used via an ISA-specific target from the following list:"
$( Q) echo
$( Q) for cfg in $( generic_defconfigs) ; do echo " $$ {cfg} " ; done
$( Q) echo
$( Q) false
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#
# Legacy defconfig compatibility - these targets used to be real defconfigs but
# now that the boards have been converted to use the generic kernel they are
# wrappers around the generic rules above.
#
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legacy_defconfigs += ocelot_defconfig
ocelot_defconfig-y := 32r2el_defconfig BOARDS = ocelot
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legacy_defconfigs += sead3_defconfig
sead3_defconfig-y := 32r2el_defconfig BOARDS = sead-3
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legacy_defconfigs += sead3micro_defconfig
sead3micro_defconfig-y := micro32r2el_defconfig BOARDS = sead-3
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legacy_defconfigs += xilfpga_defconfig
xilfpga_defconfig-y := 32r2el_defconfig BOARDS = xilfpga
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legacy_defconfigs += pistachio_defconfig
pistachio_defconfig-y := 32r2el_defconfig BOARDS = marduk
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.PHONY : $( legacy_defconfigs )
$(legacy_defconfigs) :
$( Q) $( MAKE) -f $( srctree) /Makefile $( $@ -y)
