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/ *
* sh7 3 7 2 l o w l e v e l s l e e p c o d e f o r " C o r e S t a n d b y M o d e "
*
* Copyright ( C ) 2 0 1 1 M a g n u s D a m m
*
* In " C o r e S t a n d b y M o d e " t h e A R M c o r e i s o f f , b u t L 2 c a c h e i s s t i l l o n
*
* Based o n m a c h - o m a p2 / s l e e p34 x x . S
*
* ( C) C o p y r i g h t 2 0 0 7 T e x a s I n s t r u m e n t s
* Karthik D a s u < k a r t h i k - d p @ti.com>
*
* ( C) C o p y r i g h t 2 0 0 4 T e x a s I n s t r u m e n t s , < w w w . t i . c o m >
* Richard W o o d r u f f < r - w o o d r u f f2 @ti.com>
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version 2 of
* the L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* This p r o g r a m i s d i s t r i b u t e d i n t h e h o p e t h a t i t w i l l b e u s e f u l ,
* but W I T H O U T A N Y W A R R A N T Y ; without even the implied warranty of
* MERCHANTABILITY o r F I T N E S S F O R A P A R T I C U L A R / P U R P O S E . S e e t h e
* GNU G e n e r a l P u b l i c L i c e n s e f o r m o r e d e t a i l s .
*
* You s h o u l d h a v e r e c e i v e d a c o p y o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* along w i t h t h i s p r o g r a m ; if not, write to the Free Software
* Foundation, I n c . , 5 9 T e m p l e P l a c e , S u i t e 3 3 0 , B o s t o n ,
* MA 0 2 1 1 1 - 1 3 0 7 U S A
* /
# include < l i n u x / l i n k a g e . h >
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# include < l i n u x / i n i t . h >
# include < a s m / m e m o r y . h >
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# include < a s m / a s s e m b l e r . h >
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# if d e f i n e d ( C O N F I G _ S U S P E N D ) | | d e f i n e d ( C O N F I G _ C P U _ I D L E )
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.align 12
.text
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.global sh7372_resume_core_standby_sysc
sh7372_resume_core_standby_sysc :
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ldr p c , 1 f
1 : .long c p u _ r e s u m e - P A G E _ O F F S E T + P L A T _ P H Y S _ O F F S E T
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# define S P D C R 0 x e 6 1 8 0 0 0 8
/* A3SM & A4S power down */
.global sh7372_do_idle_sysc
sh7372_do_idle_sysc :
mov r8 , r0 / * s l e e p m o d e p a s s e d i n r0 * /
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/ *
* Clear t h e S C T L R . C b i t t o p r e v e n t f u r t h e r d a t a c a c h e
* allocation. C l e a r i n g S C T L R . C w o u l d m a k e a l l t h e d a t a a c c e s s e s
* strongly o r d e r e d a n d w o u l d n o t h i t t h e c a c h e .
* /
mrc p15 , 0 , r0 , c1 , c0 , 0
bic r0 , r0 , #( 1 < < 2 ) @ Disable the C bit
mcr p15 , 0 , r0 , c1 , c0 , 0
isb
/* disable L2 cache in the aux control register */
mrc p15 , 0 , r10 , c1 , c0 , 1
bic r10 , r10 , #2
mcr p15 , 0 , r10 , c1 , c0 , 1
/ *
* Invalidate d a t a c a c h e a g a i n .
* /
ldr r1 , k e r n e l _ f l u s h
blx r1
/ *
* The k e r n e l d o e s n ' t i n t e r w o r k : v7 _ f l u s h _ d c a c h e _ a l l i n p a r t i c l u a r w i l l
* always r e t u r n i n T h u m b s t a t e w h e n C O N F I G _ T H U M B 2 _ K E R N E L i s e n a b l e d .
* This s e q u e n c e s w i t c h e s b a c k t o A R M . N o t e t h a t . a l i g n m a y i n s e r t a
* nop : bx p c n e e d s t o b e w o r d - a l i g n e d i n o r d e r t o w o r k .
* /
THUMB( . t h u m b )
THUMB( . a l i g n )
THUMB( b x p c )
THUMB( n o p )
.arm
/* Data memory barrier and Data sync barrier */
dsb
dmb
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/* SYSC power down */
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ldr r0 , =SPDCR
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str r8 , [ r0 ]
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1 :
b 1 b
kernel_flush :
.word v7_flush_dcache_all
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# endif
