2005-09-26 16:04:21 +10:00
/ *
* FPU s u p p o r t c o d e , m o v e d h e r e f r o m h e a d . S s o t h a t i t c a n b e u s e d
* by c h i p s w h i c h u s e o t h e r h e a d - w h a t e v e r . S f i l e s .
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* as p u b l i s h e d b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version
* 2 of t h e L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* /
# include < l i n u x / c o n f i g . h >
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# include < a s m / r e g . h >
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# include < a s m / p a g e . h >
# include < a s m / m m u . h >
# include < a s m / p g t a b l e . h >
# include < a s m / c p u t a b l e . h >
# include < a s m / c a c h e . h >
# include < a s m / t h r e a d _ i n f o . h >
# include < a s m / p p c _ a s m . h >
# include < a s m / a s m - o f f s e t s . h >
/ *
* This t a s k w a n t s t o u s e t h e F P U n o w .
* On U P , d i s a b l e F P f o r t h e t a s k w h i c h h a d t h e F P U p r e v i o u s l y ,
* and s a v e i t s f l o a t i n g - p o i n t r e g i s t e r s i n i t s t h r e a d _ s t r u c t .
* Load u p t h i s t a s k ' s F P r e g i s t e r s f r o m i t s t h r e a d _ s t r u c t ,
* enable t h e F P U f o r t h e c u r r e n t t a s k a n d r e t u r n t o t h e t a s k .
* /
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_ GLOBAL( l o a d _ u p _ f p u )
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mfmsr r5
ori r5 ,r5 ,M S R _ F P
SYNC
MTMSRD( r5 ) / * e n a b l e u s e o f f p u n o w * /
isync
/ *
* For S M P , w e d o n ' t d o l a z y F P U s w i t c h i n g b e c a u s e i t j u s t g e t s t o o
* horrendously c o m p l e x , e s p e c i a l l y w h e n a t a s k s w i t c h e s f r o m o n e C P U
* to a n o t h e r . I n s t e a d w e c a l l g i v e u p _ f p u i n s w i t c h _ t o .
* /
# ifndef C O N F I G _ S M P
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LOADBASE( r3 , l a s t _ t a s k _ u s e d _ m a t h )
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toreal( r3 )
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LDL r4 ,O F F ( l a s t _ t a s k _ u s e d _ m a t h ) ( r3 )
CMPI 0 ,r4 ,0
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beq 1 f
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toreal( r4 )
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addi r4 ,r4 ,T H R E A D / * w a n t l a s t _ t a s k _ u s e d _ m a t h - > t h r e a d * /
SAVE_ 3 2 F P R S ( 0 , r4 )
mffs f r0
[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 16:27:25 +10:00
stfd f r0 ,T H R E A D _ F P S C R ( r4 )
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LDL r5 ,P T _ R E G S ( r4 )
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toreal( r5 )
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LDL r4 ,_ M S R - S T A C K _ F R A M E _ O V E R H E A D ( r5 )
2005-09-26 16:04:21 +10:00
li r10 ,M S R _ F P | M S R _ F E 0 | M S R _ F E 1
andc r4 ,r4 ,r10 / * d i s a b l e F P f o r p r e v i o u s t a s k * /
2005-10-06 10:59:19 +10:00
STL r4 ,_ M S R - S T A C K _ F R A M E _ O V E R H E A D ( r5 )
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1 :
# endif / * C O N F I G _ S M P * /
/* enable use of FP after return */
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# ifdef C O N F I G _ P P C 3 2
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mfspr r5 ,S P R N _ S P R G 3 / * c u r r e n t t a s k ' s T H R E A D ( p h y s ) * /
lwz r4 ,T H R E A D _ F P E X C _ M O D E ( r5 )
ori r9 ,r9 ,M S R _ F P / * e n a b l e F P f o r c u r r e n t * /
or r9 ,r9 ,r4
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# else
ld r4 ,P A C A C U R R E N T ( r13 )
addi r5 ,r4 ,T H R E A D / * G e t T H R E A D * /
ld r4 ,T H R E A D _ F P E X C _ M O D E ( r5 )
ori r12 ,r12 ,M S R _ F P
or r12 ,r12 ,r4
std r12 ,_ M S R ( r1 )
# endif
[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 16:27:25 +10:00
lfd f r0 ,T H R E A D _ F P S C R ( r5 )
2005-09-26 16:04:21 +10:00
mtfsf 0 x f f ,f r0
REST_ 3 2 F P R S ( 0 , r5 )
# ifndef C O N F I G _ S M P
subi r4 ,r5 ,T H R E A D
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fromreal( r4 )
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STL r4 ,O F F ( l a s t _ t a s k _ u s e d _ m a t h ) ( r3 )
2005-09-26 16:04:21 +10:00
# endif / * C O N F I G _ S M P * /
/* restore registers and return */
/* we haven't used ctr or xer or lr */
b f a s t _ e x c e p t i o n _ r e t u r n
/ *
* giveup_ f p u ( t s k )
* Disable F P f o r t h e t a s k g i v e n a s t h e a r g u m e n t ,
* and s a v e t h e f l o a t i n g - p o i n t r e g i s t e r s i n i t s t h r e a d _ s t r u c t .
* Enables t h e F P U f o r u s e i n t h e k e r n e l o n r e t u r n .
* /
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_ GLOBAL( g i v e u p _ f p u )
2005-09-26 16:04:21 +10:00
mfmsr r5
ori r5 ,r5 ,M S R _ F P
SYNC_ 6 0 1
ISYNC_ 6 0 1
MTMSRD( r5 ) / * e n a b l e u s e o f f p u n o w * /
SYNC_ 6 0 1
isync
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CMPI 0 ,r3 ,0
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beqlr- / * i f n o p r e v i o u s o w n e r , d o n e * /
addi r3 ,r3 ,T H R E A D / * w a n t T H R E A D o f t a s k * /
2005-10-06 10:59:19 +10:00
LDL r5 ,P T _ R E G S ( r3 )
CMPI 0 ,r5 ,0
2005-09-26 16:04:21 +10:00
SAVE_ 3 2 F P R S ( 0 , r3 )
mffs f r0
[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 16:27:25 +10:00
stfd f r0 ,T H R E A D _ F P S C R ( r3 )
2005-09-26 16:04:21 +10:00
beq 1 f
2005-10-06 10:59:19 +10:00
LDL r4 ,_ M S R - S T A C K _ F R A M E _ O V E R H E A D ( r5 )
2005-09-26 16:04:21 +10:00
li r3 ,M S R _ F P | M S R _ F E 0 | M S R _ F E 1
andc r4 ,r4 ,r3 / * d i s a b l e F P f o r p r e v i o u s t a s k * /
2005-10-06 10:59:19 +10:00
STL r4 ,_ M S R - S T A C K _ F R A M E _ O V E R H E A D ( r5 )
2005-09-26 16:04:21 +10:00
1 :
# ifndef C O N F I G _ S M P
li r5 ,0
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LOADBASE( r4 ,l a s t _ t a s k _ u s e d _ m a t h )
STL r5 ,O F F ( l a s t _ t a s k _ u s e d _ m a t h ) ( r4 )
2005-09-26 16:04:21 +10:00
# endif / * C O N F I G _ S M P * /
blr
[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 16:27:25 +10:00
/ *
* These a r e u s e d i n t h e a l i g n m e n t t r a p h a n d l e r w h e n e m u l a t i n g
* single- p r e c i s i o n l o a d s a n d s t o r e s .
* We r e s t o r e a n d s a v e t h e f p s c r s o t h e t a s k g e t s t h e s a m e r e s u l t
* and e x c e p t i o n s a s i f t h e c p u h a d p e r f o r m e d t h e l o a d o r s t o r e .
* /
_ GLOBAL( c v t _ f d )
lfd 0 ,T H R E A D _ F P S C R ( r5 ) / * l o a d u p f p s c r v a l u e * /
mtfsf 0 x f f ,0
lfs 0 ,0 ( r3 )
stfd 0 ,0 ( r4 )
mffs 0
stfd 0 ,T H R E A D _ F P S C R ( r5 ) / * s a v e n e w f p s c r v a l u e * /
blr
_ GLOBAL( c v t _ d f )
lfd 0 ,T H R E A D _ F P S C R ( r5 ) / * l o a d u p f p s c r v a l u e * /
mtfsf 0 x f f ,0
lfd 0 ,0 ( r3 )
stfs 0 ,0 ( r4 )
mffs 0
stfd 0 ,T H R E A D _ F P S C R ( r5 ) / * s a v e n e w f p s c r v a l u e * /
blr
