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/*
* IEEE754 floating point arithmetic
* double precision : MADDF . f ( Fused Multiply Add )
* MADDF . fmt : FPR [ fd ] = FPR [ fd ] + ( FPR [ fs ] x FPR [ ft ] )
*
* MIPS floating point support
* Copyright ( C ) 2015 Imagination Technologies , Ltd .
* Author : Markos Chandras < markos . chandras @ imgtec . com >
*
* This program is free software ; you can distribute it and / or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation ; version 2 of the License .
*/
# include "ieee754dp.h"
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enum maddf_flags {
maddf_negate_product = 1 < < 0 ,
} ;
static union ieee754dp _dp_maddf ( union ieee754dp z , union ieee754dp x ,
union ieee754dp y , enum maddf_flags flags )
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{
int re ;
int rs ;
u64 rm ;
unsigned lxm ;
unsigned hxm ;
unsigned lym ;
unsigned hym ;
u64 lrm ;
u64 hrm ;
u64 t ;
u64 at ;
int s ;
COMPXDP ;
COMPYDP ;
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COMPZDP ;
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EXPLODEXDP ;
EXPLODEYDP ;
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EXPLODEZDP ;
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FLUSHXDP ;
FLUSHYDP ;
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FLUSHZDP ;
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ieee754_clearcx ( ) ;
switch ( zc ) {
case IEEE754_CLASS_SNAN :
ieee754_setcx ( IEEE754_INVALID_OPERATION ) ;
return ieee754dp_nanxcpt ( z ) ;
case IEEE754_CLASS_DNORM :
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DPDNORMZ ;
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/* QNAN is handled separately below */
}
switch ( CLPAIR ( xc , yc ) ) {
case CLPAIR ( IEEE754_CLASS_QNAN , IEEE754_CLASS_SNAN ) :
case CLPAIR ( IEEE754_CLASS_ZERO , IEEE754_CLASS_SNAN ) :
case CLPAIR ( IEEE754_CLASS_NORM , IEEE754_CLASS_SNAN ) :
case CLPAIR ( IEEE754_CLASS_DNORM , IEEE754_CLASS_SNAN ) :
case CLPAIR ( IEEE754_CLASS_INF , IEEE754_CLASS_SNAN ) :
return ieee754dp_nanxcpt ( y ) ;
case CLPAIR ( IEEE754_CLASS_SNAN , IEEE754_CLASS_SNAN ) :
case CLPAIR ( IEEE754_CLASS_SNAN , IEEE754_CLASS_QNAN ) :
case CLPAIR ( IEEE754_CLASS_SNAN , IEEE754_CLASS_ZERO ) :
case CLPAIR ( IEEE754_CLASS_SNAN , IEEE754_CLASS_NORM ) :
case CLPAIR ( IEEE754_CLASS_SNAN , IEEE754_CLASS_DNORM ) :
case CLPAIR ( IEEE754_CLASS_SNAN , IEEE754_CLASS_INF ) :
return ieee754dp_nanxcpt ( x ) ;
case CLPAIR ( IEEE754_CLASS_ZERO , IEEE754_CLASS_QNAN ) :
case CLPAIR ( IEEE754_CLASS_NORM , IEEE754_CLASS_QNAN ) :
case CLPAIR ( IEEE754_CLASS_DNORM , IEEE754_CLASS_QNAN ) :
case CLPAIR ( IEEE754_CLASS_INF , IEEE754_CLASS_QNAN ) :
return y ;
case CLPAIR ( IEEE754_CLASS_QNAN , IEEE754_CLASS_QNAN ) :
case CLPAIR ( IEEE754_CLASS_QNAN , IEEE754_CLASS_ZERO ) :
case CLPAIR ( IEEE754_CLASS_QNAN , IEEE754_CLASS_NORM ) :
case CLPAIR ( IEEE754_CLASS_QNAN , IEEE754_CLASS_DNORM ) :
case CLPAIR ( IEEE754_CLASS_QNAN , IEEE754_CLASS_INF ) :
return x ;
/*
* Infinity handling
*/
case CLPAIR ( IEEE754_CLASS_INF , IEEE754_CLASS_ZERO ) :
case CLPAIR ( IEEE754_CLASS_ZERO , IEEE754_CLASS_INF ) :
if ( zc = = IEEE754_CLASS_QNAN )
return z ;
ieee754_setcx ( IEEE754_INVALID_OPERATION ) ;
return ieee754dp_indef ( ) ;
case CLPAIR ( IEEE754_CLASS_NORM , IEEE754_CLASS_INF ) :
case CLPAIR ( IEEE754_CLASS_DNORM , IEEE754_CLASS_INF ) :
case CLPAIR ( IEEE754_CLASS_INF , IEEE754_CLASS_NORM ) :
case CLPAIR ( IEEE754_CLASS_INF , IEEE754_CLASS_DNORM ) :
case CLPAIR ( IEEE754_CLASS_INF , IEEE754_CLASS_INF ) :
if ( zc = = IEEE754_CLASS_QNAN )
return z ;
return ieee754dp_inf ( xs ^ ys ) ;
case CLPAIR ( IEEE754_CLASS_ZERO , IEEE754_CLASS_ZERO ) :
case CLPAIR ( IEEE754_CLASS_ZERO , IEEE754_CLASS_NORM ) :
case CLPAIR ( IEEE754_CLASS_ZERO , IEEE754_CLASS_DNORM ) :
case CLPAIR ( IEEE754_CLASS_NORM , IEEE754_CLASS_ZERO ) :
case CLPAIR ( IEEE754_CLASS_DNORM , IEEE754_CLASS_ZERO ) :
if ( zc = = IEEE754_CLASS_INF )
return ieee754dp_inf ( zs ) ;
/* Multiplication is 0 so just return z */
return z ;
case CLPAIR ( IEEE754_CLASS_DNORM , IEEE754_CLASS_DNORM ) :
DPDNORMX ;
case CLPAIR ( IEEE754_CLASS_NORM , IEEE754_CLASS_DNORM ) :
if ( zc = = IEEE754_CLASS_QNAN )
return z ;
else if ( zc = = IEEE754_CLASS_INF )
return ieee754dp_inf ( zs ) ;
DPDNORMY ;
break ;
case CLPAIR ( IEEE754_CLASS_DNORM , IEEE754_CLASS_NORM ) :
if ( zc = = IEEE754_CLASS_QNAN )
return z ;
else if ( zc = = IEEE754_CLASS_INF )
return ieee754dp_inf ( zs ) ;
DPDNORMX ;
break ;
case CLPAIR ( IEEE754_CLASS_NORM , IEEE754_CLASS_NORM ) :
if ( zc = = IEEE754_CLASS_QNAN )
return z ;
else if ( zc = = IEEE754_CLASS_INF )
return ieee754dp_inf ( zs ) ;
/* fall through to real computations */
}
/* Finally get to do some computation */
/*
* Do the multiplication bit first
*
* rm = xm * ym , re = xe + ye basically
*
* At this point xm and ym should have been normalized .
*/
assert ( xm & DP_HIDDEN_BIT ) ;
assert ( ym & DP_HIDDEN_BIT ) ;
re = xe + ye ;
rs = xs ^ ys ;
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if ( flags & maddf_negate_product )
rs ^ = 1 ;
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/* shunt to top of word */
xm < < = 64 - ( DP_FBITS + 1 ) ;
ym < < = 64 - ( DP_FBITS + 1 ) ;
/*
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* Multiply 64 bits xm , ym to give high 64 bits rm with stickness .
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*/
/* 32 * 32 => 64 */
# define DPXMULT(x, y) ((u64)(x) * (u64)y)
lxm = xm ;
hxm = xm > > 32 ;
lym = ym ;
hym = ym > > 32 ;
lrm = DPXMULT ( lxm , lym ) ;
hrm = DPXMULT ( hxm , hym ) ;
t = DPXMULT ( lxm , hym ) ;
at = lrm + ( t < < 32 ) ;
hrm + = at < lrm ;
lrm = at ;
hrm = hrm + ( t > > 32 ) ;
t = DPXMULT ( hxm , lym ) ;
at = lrm + ( t < < 32 ) ;
hrm + = at < lrm ;
lrm = at ;
hrm = hrm + ( t > > 32 ) ;
rm = hrm | ( lrm ! = 0 ) ;
/*
* Sticky shift down to normal rounding precision .
*/
if ( ( s64 ) rm < 0 ) {
rm = ( rm > > ( 64 - ( DP_FBITS + 1 + 3 ) ) ) |
( ( rm < < ( DP_FBITS + 1 + 3 ) ) ! = 0 ) ;
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re + + ;
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} else {
rm = ( rm > > ( 64 - ( DP_FBITS + 1 + 3 + 1 ) ) ) |
( ( rm < < ( DP_FBITS + 1 + 3 + 1 ) ) ! = 0 ) ;
}
assert ( rm & ( DP_HIDDEN_BIT < < 3 ) ) ;
/* And now the addition */
assert ( zm & DP_HIDDEN_BIT ) ;
/*
* Provide guard , round and stick bit space .
*/
zm < < = 3 ;
if ( ze > re ) {
/*
* Have to shift y fraction right to align .
*/
s = ze - re ;
rm = XDPSRS ( rm , s ) ;
re + = s ;
} else if ( re > ze ) {
/*
* Have to shift x fraction right to align .
*/
s = re - ze ;
zm = XDPSRS ( zm , s ) ;
ze + = s ;
}
assert ( ze = = re ) ;
assert ( ze < = DP_EMAX ) ;
if ( zs = = rs ) {
/*
* Generate 28 bit result of adding two 27 bit numbers
* leaving result in xm , xs and xe .
*/
zm = zm + rm ;
if ( zm > > ( DP_FBITS + 1 + 3 ) ) { /* carry out */
zm = XDPSRS1 ( zm ) ;
ze + + ;
}
} else {
if ( zm > = rm ) {
zm = zm - rm ;
} else {
zm = rm - zm ;
zs = rs ;
}
if ( zm = = 0 )
return ieee754dp_zero ( ieee754_csr . rm = = FPU_CSR_RD ) ;
/*
* Normalize to rounding precision .
*/
while ( ( zm > > ( DP_FBITS + 3 ) ) = = 0 ) {
zm < < = 1 ;
ze - - ;
}
}
return ieee754dp_format ( zs , ze , zm ) ;
}
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union ieee754dp ieee754dp_maddf ( union ieee754dp z , union ieee754dp x ,
union ieee754dp y )
{
return _dp_maddf ( z , x , y , 0 ) ;
}
union ieee754dp ieee754dp_msubf ( union ieee754dp z , union ieee754dp x ,
union ieee754dp y )
{
return _dp_maddf ( z , x , y , maddf_negate_product ) ;
}