ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
/ *
* ARCv2 I S A b a s e d c o r e L o w L e v e l I n t r / T r a p s / E x c e p t i o n s ( n o n - T L B ) H a n d l i n g
*
* Copyright ( C ) 2 0 1 3 S y n o p s y s , I n c . ( w w w . s y n o p s y s . c o m )
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
* /
# include < l i n u x / l i n k a g e . h > / * A R C _ { E X T R Y ,E X I T } * /
# include < a s m / e n t r y . h > / * S A V E _ A L L _ { I N T 1 ,I N T 2 ,T R A P . . . } * /
# include < a s m / e r r n o . h >
# include < a s m / a r c r e g s . h >
# include < a s m / i r q f l a g s . h >
2017-01-31 14:45:22 +03:00
; A maximum number of supported interrupts in the core interrupt controller.
; This number is not equal to the maximum interrupt number (256) because
; first 16 lines are reserved for exceptions and are not configurable.
# define N R _ C P U _ I R Q S 2 4 0
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
.cpu HS
# define V E C T O R . w o r d
;############################ Vector Table #################################
.section .vector , " a" ,@progbits
.align 4
# Initial 1 6 s l o t s a r e E x c e p t i o n V e c t o r s
2015-10-09 08:56:12 +03:00
VECTOR r e s _ s e r v i c e ; Reset Vector
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
VECTOR m e m _ s e r v i c e ; Mem exception
VECTOR i n s t r _ s e r v i c e ; Instrn Error
VECTOR E V _ M a c h i n e C h e c k ; Fatal Machine check
VECTOR E V _ T L B M i s s I ; Intruction TLB miss
VECTOR E V _ T L B M i s s D ; Data TLB miss
VECTOR E V _ T L B P r o t V ; Protection Violation
VECTOR E V _ P r i v i l e g e V ; Privilege Violation
VECTOR E V _ S W I ; Software Breakpoint
VECTOR E V _ T r a p ; Trap exception
VECTOR E V _ E x t e n s i o n ; Extn Instruction Exception
VECTOR E V _ D i v Z e r o ; Divide by Zero
VECTOR E V _ D C E r r o r ; Data Cache Error
VECTOR E V _ M i s a l i g n e d ; Misaligned Data Access
VECTOR r e s e r v e d ; Reserved slots
VECTOR r e s e r v e d ; Reserved slots
# Begin I n t e r r u p t V e c t o r s
VECTOR h a n d l e _ i n t e r r u p t ; (16) Timer0
VECTOR h a n d l e _ i n t e r r u p t ; unused (Timer1)
VECTOR h a n d l e _ i n t e r r u p t ; unused (WDT)
2016-02-23 09:25:16 +03:00
VECTOR h a n d l e _ i n t e r r u p t ; (19) Inter core Interrupt (IPI)
VECTOR h a n d l e _ i n t e r r u p t ; (20) perf Interrupt
VECTOR h a n d l e _ i n t e r r u p t ; (21) Software Triggered Intr (Self IPI)
VECTOR h a n d l e _ i n t e r r u p t ; unused
VECTOR h a n d l e _ i n t e r r u p t ; (23) unused
# End o f f i x e d I R Q s
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
2017-01-31 14:45:22 +03:00
.rept NR_CPU_IRQS - 8
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
VECTOR h a n d l e _ i n t e r r u p t
.endr
.section .text , " ax" ,@progbits
2015-08-27 13:55:07 +03:00
reserved :
flag 1 ; Unexpected event, halt
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
;##################### Interrupt Handling ##############################
ENTRY( h a n d l e _ i n t e r r u p t )
INTERRUPT_ P R O L O G U E i r q
2016-09-24 00:09:30 +03:00
# irq c o n t r o l A P I s l o c a l _ i r q _ s a v e / r e s t o r e / d i s a b l e / e n a b l e f i d d l e w i t h
# global i n t e r r u p t e n a b l e b i t s i n S T A T U S 3 2 ( . I E f o r 1 p r i o , . E [ ] f o r 2 p r i o )
# However a t a k e n i n t e r r u p t d o e s n ' t c l e a r t h e s e b i t s . T h u s i r q s _ d i s a b l e d ( )
# query i n h a r d I S R p a t h w o u l d r e t u r n f a l s e ( s i n c e . I E i s s e t ) w h i c h w o u l d
# trips g e n i r q i n t e r r u p t h a n d l i n g a s s e r t s .
#
# So d o a " s o f t " d i s a b l e o f i n t e r r u t p s h e r e .
#
# Note t h i s d i s a b l e i s o n l y f o r c o n s i s t e n t b o o k - k e e p i n g a s f u r t h e r i n t e r r u p t s
# will b e d i s a b l e d a n y w a y s e v e n w / o t h i s . H a r d w a r e t r a c k s a c t i v e i n t e r r u p t s
# seperately i n A U X _ I R Q _ A C T I V E . a c t i v e a n d w i l l n o t t a k e n e w i n t e r r u p t s
# unless t h i s o n e r e t u r n s ( o r h i g h e r p r i o b e c o m e s p e n d i n g i n 2 - p r i o s c h e m e )
IRQ_ D I S A B L E
; icause is banked: one per priority level
; so a higher prio interrupt taken here won't clobber prev prio icause
2016-03-23 12:26:52 +03:00
lr r0 , [ I C A U S E ]
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
mov b l i n k , r e t _ f r o m _ e x c e p t i o n
b. d a r c h _ d o _ I R Q
mov r1 , s p
END( h a n d l e _ i n t e r r u p t )
;################### Non TLB Exception Handling #############################
ENTRY( E V _ S W I )
2017-03-21 04:46:15 +03:00
; TODO: implement this
EXCEPTION_ P R O L O G U E
b r e t _ f r o m _ e x c e p t i o n
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
END( E V _ S W I )
ENTRY( E V _ D i v Z e r o )
2017-03-21 04:46:15 +03:00
; TODO: implement this
EXCEPTION_ P R O L O G U E
b r e t _ f r o m _ e x c e p t i o n
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
END( E V _ D i v Z e r o )
ENTRY( E V _ D C E r r o r )
2017-03-21 04:46:15 +03:00
; TODO: implement this
EXCEPTION_ P R O L O G U E
b r e t _ f r o m _ e x c e p t i o n
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
END( E V _ D C E r r o r )
2015-10-30 22:52:51 +03:00
; ---------------------------------------------
; Memory Error Exception Handler
; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
; Instruction fetch or Data access, under a single Exception Vector
; ---------------------------------------------
ENTRY( m e m _ s e r v i c e )
EXCEPTION_ P R O L O G U E
lr r0 , [ e f a ]
mov r1 , s p
FAKE_ R E T _ F R O M _ E X C P N
bl d o _ m e m o r y _ e r r o r
b r e t _ f r o m _ e x c e p t i o n
END( m e m _ s e r v i c e )
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
ENTRY( E V _ M i s a l i g n e d )
EXCEPTION_ P R O L O G U E
lr r0 , [ e f a ] ; Faulting Data address
mov r1 , s p
FAKE_ R E T _ F R O M _ E X C P N
SAVE_ C A L L E E _ S A V E D _ U S E R
mov r2 , s p ; callee_regs
bl d o _ m i s a l i g n e d _ a c c e s s
; TBD: optimize - do this only if a callee reg was involved
; either a dst of emulated LD/ST or src with address-writeback
RESTORE_ C A L L E E _ S A V E D _ U S E R
b r e t _ f r o m _ e x c e p t i o n
END( E V _ M i s a l i g n e d )
; ---------------------------------------------
; Protection Violation Exception Handler
; ---------------------------------------------
ENTRY( E V _ T L B P r o t V )
EXCEPTION_ P R O L O G U E
lr r0 , [ e f a ] ; Faulting Data address
mov r1 , s p ; pt_regs
FAKE_ R E T _ F R O M _ E X C P N
mov b l i n k , r e t _ f r o m _ e x c e p t i o n
b d o _ p a g e _ f a u l t
END( E V _ T L B P r o t V )
; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
; need to call do_page_fault().
; ECR in pt_regs provides whether access was R/W/X
.global call_do_page_fault
.set _ d o _ p a g e _ f a u l t , E V _ T L B P r o t V
;############# Common Handlers for ARCompact and ARCv2 ##############
# include " e n t r y . S "
;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
;
; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
; IRQ shd definitely not happen between now and rtie
; All 2 entry points to here already disable interrupts
.Lrestore_regs :
2016-09-24 00:09:30 +03:00
restore_regs :
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
2016-03-23 12:26:52 +03:00
# Interrpts a r e a c t u a l l y d i s a b l e d f r o m t h i s p o i n t o n , b u t w i l l g e t
# reenabled a f t e r w e r e t u r n f r o m i n t e r r u p t / e x c e p t i o n .
# But i r q t r a c e r n e e d s t o b e t o l d n o w . . .
TRACE_ A S M _ I R Q _ E N A B L E
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
ld r0 , [ s p , P T _ s t a t u s32 ] ; U/K mode at time of entry
lr r10 , [ A U X _ I R Q _ A C T ]
bmsk r11 , r10 , 1 5 ; AUX_IRQ_ACT.ACTIVE
breq r11 , 0 , . L e x c e p t _ r e t ; No intr active, ret from Exception
;####### Return from Intr #######
debug_marker_l1 :
2014-09-22 15:21:47 +04:00
bbit1 . n t r0 , S T A T U S _ D E _ B I T , . L i n t r _ r e t _ t o _ d e l a y _ s l o t
.Lisr_ret_fast_path :
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
; Handle special case #1: (Entry via Exception, Return via IRQ)
;
; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
; task now returning to U mode (riding the Intr)
; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
; won't be switched to correct U mode value (from AUX_SP)
; So force AUX_IRQ_ACT.U for such a case
btst r0 , S T A T U S _ U _ B I T ; Z flag set if K (Z clear for U)
bset. n z r11 , r11 , A U X _ I R Q _ A C T _ B I T _ U ; NZ means U
sr r11 , [ A U X _ I R Q _ A C T ]
INTERRUPT_ E P I L O G U E i r q
rtie
;####### Return from Exception / pure kernel mode #######
.Lexcept_ret : ; Expects r0 has PT_status32
debug_marker_syscall :
EXCEPTION_ E P I L O G U E
rtie
2014-09-22 15:21:47 +04:00
;####### Return from Intr to insn in delay slot #######
; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
;
; Intr returning to a Delay Slot (DS) insn
; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
; entry was via Exception in DS which got preempted in kernel).
;
2016-01-08 09:59:10 +03:00
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
;
; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
2014-09-22 15:21:47 +04:00
.Lintr_ret_to_delay_slot :
debug_marker_ds :
ld r2 , [ @intr_to_DE_cnt]
add r2 , r2 , 1
st r2 , [ @intr_to_DE_cnt]
ld r2 , [ s p , P T _ r e t ]
ld r3 , [ s p , P T _ s t a t u s32 ]
2016-01-08 09:59:10 +03:00
; STAT32 for Int return created from scratch
; (No delay dlot, disable Further intr in trampoline)
2014-09-22 15:21:47 +04:00
bic r0 , r3 , S T A T U S _ U _ M A S K | S T A T U S _ D E _ M A S K | S T A T U S _ I E _ M A S K | S T A T U S _ L _ M A S K
st r0 , [ s p , P T _ s t a t u s32 ]
mov r1 , . L i n t r _ r e t _ t o _ d e l a y _ s l o t _ 2
st r1 , [ s p , P T _ r e t ]
2016-01-08 09:59:10 +03:00
; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
2014-09-22 15:21:47 +04:00
st r2 , [ s p , 0 ]
st r3 , [ s p , 4 ]
b . L i s r _ r e t _ f a s t _ p a t h
.Lintr_ret_to_delay_slot_2 :
2016-01-08 09:59:10 +03:00
; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
2014-09-22 15:21:47 +04:00
sub s p , s p , S Z _ P T _ R E G S
st r9 , [ s p , - 4 ]
ld r9 , [ s p , 0 ]
sr r9 , [ e r e t ]
ld r9 , [ s p , 4 ]
sr r9 , [ e r s t a t u s ]
2016-01-08 09:59:10 +03:00
; restore AUX_USER_SP if returning to U mode
bbit0 r9 , S T A T U S _ U _ B I T , 1 f
ld r9 , [ s p , P T _ s p ]
sr r9 , [ A U X _ U S E R _ S P ]
1 :
2014-09-22 15:21:47 +04:00
ld r9 , [ s p , 8 ]
sr r9 , [ e r b t a ]
ld r9 , [ s p , - 4 ]
add s p , s p , S Z _ P T _ R E G S
2016-01-08 09:59:10 +03:00
; return from pure kernel mode to delay slot
2014-09-22 15:21:47 +04:00
rtie
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 17:00:41 +04:00
END( r e t _ f r o m _ e x c e p t i o n )
