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# ifndef __PPC_PCI_H
# define __PPC_PCI_H
# ifdef __KERNEL__
# include <linux/types.h>
# include <linux/slab.h>
# include <linux/string.h>
# include <linux/mm.h>
# include <asm/scatterlist.h>
# include <asm/io.h>
# include <asm/pci-bridge.h>
# include <asm-generic/pci-dma-compat.h>
struct pci_dev ;
/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
# define IOBASE_BRIDGE_NUMBER 0
# define IOBASE_MEMORY 1
# define IOBASE_IO 2
# define IOBASE_ISA_IO 3
# define IOBASE_ISA_MEM 4
/*
* Set this to 1 if you want the kernel to re - assign all PCI
* bus numbers
*/
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extern int pci_assign_all_buses ;
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# define pcibios_assign_all_busses() (pci_assign_all_buses)
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# define pcibios_scan_all_fns(a, b) 0
# define PCIBIOS_MIN_IO 0x1000
# define PCIBIOS_MIN_MEM 0x10000000
extern inline void pcibios_set_master ( struct pci_dev * dev )
{
/* No special bus mastering setup handling */
}
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extern inline void pcibios_penalize_isa_irq ( int irq , int active )
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{
/* We don't do dynamic PCI IRQ allocation */
}
extern unsigned long pci_resource_to_bus ( struct pci_dev * pdev , struct resource * res ) ;
/*
* The PCI bus bridge can translate addresses issued by the processor ( s )
* into a different address on the PCI bus . On 32 - bit cpus , we assume
* this mapping is 1 - 1 , but on 64 - bit systems it often isn ' t .
*
* Obsolete ! Drivers should now use pci_resource_to_bus
*/
extern unsigned long phys_to_bus ( unsigned long pa ) ;
extern unsigned long pci_phys_to_bus ( unsigned long pa , int busnr ) ;
extern unsigned long pci_bus_to_phys ( unsigned int ba , int busnr ) ;
/* The PCI address space does equal the physical memory
* address space . The networking and block device layers use
* this boolean for bounce buffer decisions .
*/
# define PCI_DMA_BUS_IS_PHYS (1)
[POWERPC] Define pci_unmap_addr() et al. when CONFIG_NOT_COHERENT_CACHE=y
The current PowerPC code makes pci_unmap_addr(), pci_unmap_addr_set(),
and friends trivial for all 32-bit kernels. This is reasonable, since
for those kernels it is true that pci_unmap_single() does not need the
DMA address from the original DMA mapping -- in fact, it is a NOP.
However, I recently tried the tg3 driver on a PowerPC 440SPe machine,
which runs a 32-bit kernel and has non-cache-coherent PCI DMA. I
found that the tg3 driver crashed in pci_dma_sync_single_for_cpu(),
since for non-coherent systems, that function must invalidate the
cache for the DMA address range requested, and therefore it does use
the address passed in. tg3 uses a DMA address it stashes away with
pci_unmap_addr_set() and retrieves with pci_unmap_addr(). Of course,
since pci_unmap_addr() is defined to (0) right now, this doesn't work.
It seems to me that the tg3 driver is using pci_unmap_addr() in a
legitimate way -- I wouldn't want to have to teach all drivers that
they should use pci_unmap_addr() if they only need the address for
unmapping functions, but if they want the pci_dma_sync functions, then
they have to store the DMA address without the helper macros.
The right fix therefore seems to be in the definition of the macros in
<asm/pci.h> -- we should use the trivial versions only for 32-bit
kernels for coherent systems, and the real versions for both 64-bit
kernels and non-coherent systems.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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# ifdef CONFIG_NOT_COHERENT_CACHE
/*
* pci_unmap_ { page , single } are NOPs but pci_dma_sync_single_for_cpu ( )
* and so on are not , so . . .
*/
# define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
dma_addr_t ADDR_NAME ;
# define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
__u32 LEN_NAME ;
# define pci_unmap_addr(PTR, ADDR_NAME) \
( ( PTR ) - > ADDR_NAME )
# define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
( ( ( PTR ) - > ADDR_NAME ) = ( VAL ) )
# define pci_unmap_len(PTR, LEN_NAME) \
( ( PTR ) - > LEN_NAME )
# define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
( ( ( PTR ) - > LEN_NAME ) = ( VAL ) )
# else /* coherent */
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/* pci_unmap_{page,single} is a nop so... */
# define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
# define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
# define pci_unmap_addr(PTR, ADDR_NAME) (0)
# define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
# define pci_unmap_len(PTR, LEN_NAME) (0)
# define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
[POWERPC] Define pci_unmap_addr() et al. when CONFIG_NOT_COHERENT_CACHE=y
The current PowerPC code makes pci_unmap_addr(), pci_unmap_addr_set(),
and friends trivial for all 32-bit kernels. This is reasonable, since
for those kernels it is true that pci_unmap_single() does not need the
DMA address from the original DMA mapping -- in fact, it is a NOP.
However, I recently tried the tg3 driver on a PowerPC 440SPe machine,
which runs a 32-bit kernel and has non-cache-coherent PCI DMA. I
found that the tg3 driver crashed in pci_dma_sync_single_for_cpu(),
since for non-coherent systems, that function must invalidate the
cache for the DMA address range requested, and therefore it does use
the address passed in. tg3 uses a DMA address it stashes away with
pci_unmap_addr_set() and retrieves with pci_unmap_addr(). Of course,
since pci_unmap_addr() is defined to (0) right now, this doesn't work.
It seems to me that the tg3 driver is using pci_unmap_addr() in a
legitimate way -- I wouldn't want to have to teach all drivers that
they should use pci_unmap_addr() if they only need the address for
unmapping functions, but if they want the pci_dma_sync functions, then
they have to store the DMA address without the helper macros.
The right fix therefore seems to be in the definition of the macros in
<asm/pci.h> -- we should use the trivial versions only for 32-bit
kernels for coherent systems, and the real versions for both 64-bit
kernels and non-coherent systems.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-12-06 15:15:38 -08:00
# endif /* CONFIG_NOT_COHERENT_CACHE */
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# ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice ( struct pci_dev * pdev ,
enum pci_dma_burst_strategy * strat ,
unsigned long * strategy_parameter )
{
* strat = PCI_DMA_BURST_INFINITY ;
* strategy_parameter = ~ 0UL ;
}
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# endif
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/* Return the index of the PCI controller for device PDEV. */
# define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
/* Set the name of the bus as it appears in /proc/bus/pci */
static inline int pci_proc_domain ( struct pci_bus * bus )
{
return 0 ;
}
/* Map a range of PCI memory or I/O space for a device into user space */
int pci_mmap_page_range ( struct pci_dev * pdev , struct vm_area_struct * vma ,
enum pci_mmap_state mmap_state , int write_combine ) ;
/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
# define HAVE_PCI_MMAP 1
extern void
pcibios_resource_to_bus ( struct pci_dev * dev , struct pci_bus_region * region ,
struct resource * res ) ;
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extern void
pcibios_bus_to_resource ( struct pci_dev * dev , struct resource * res ,
struct pci_bus_region * region ) ;
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static inline struct resource *
pcibios_select_root ( struct pci_dev * pdev , struct resource * res )
{
struct resource * root = NULL ;
if ( res - > flags & IORESOURCE_IO )
root = & ioport_resource ;
if ( res - > flags & IORESOURCE_MEM )
root = & iomem_resource ;
return root ;
}
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struct file ;
extern pgprot_t pci_phys_mem_access_prot ( struct file * file ,
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unsigned long pfn ,
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unsigned long size ,
pgprot_t prot ) ;
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# define HAVE_ARCH_PCI_RESOURCE_TO_USER
extern void pci_resource_to_user ( const struct pci_dev * dev , int bar ,
const struct resource * rsrc ,
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resource_size_t * start , resource_size_t * end ) ;
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# endif /* __KERNEL__ */
# endif /* __PPC_PCI_H */