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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
* Copyright ( C ) 2011 Freescale Semiconductor , Inc .
*/
# ifndef __DW_HDMI__
# define __DW_HDMI__
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# include <sound/hdmi-codec.h>
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struct drm_display_info ;
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struct drm_display_mode ;
struct drm_encoder ;
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struct dw_hdmi ;
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struct platform_device ;
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/**
* DOC : Supported input formats and encodings
*
* Depending on the Hardware configuration of the Controller IP , it supports
* a subset of the following input formats and encodings on its internal
* 48 bit bus .
*
* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | Format Name | Format Code | Encodings |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | RGB 4 : 4 : 4 8 bit | ` ` MEDIA_BUS_FMT_RGB888_1X24 ` ` | ` ` V4L2_YCBCR_ENC_DEFAULT ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | RGB 4 : 4 : 4 10 bits | ` ` MEDIA_BUS_FMT_RGB101010_1X30 ` ` | ` ` V4L2_YCBCR_ENC_DEFAULT ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | RGB 4 : 4 : 4 12 bits | ` ` MEDIA_BUS_FMT_RGB121212_1X36 ` ` | ` ` V4L2_YCBCR_ENC_DEFAULT ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | RGB 4 : 4 : 4 16 bits | ` ` MEDIA_BUS_FMT_RGB161616_1X48 ` ` | ` ` V4L2_YCBCR_ENC_DEFAULT ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 4 : 4 8 bit | ` ` MEDIA_BUS_FMT_YUV8_1X24 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 4 : 4 10 bits | ` ` MEDIA_BUS_FMT_YUV10_1X30 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 4 : 4 12 bits | ` ` MEDIA_BUS_FMT_YUV12_1X36 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 4 : 4 16 bits | ` ` MEDIA_BUS_FMT_YUV16_1X48 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_XV709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 2 : 2 8 bit | ` ` MEDIA_BUS_FMT_UYVY8_1X16 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 2 : 2 10 bits | ` ` MEDIA_BUS_FMT_UYVY10_1X20 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 2 : 2 12 bits | ` ` MEDIA_BUS_FMT_UYVY12_1X24 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 2 : 0 8 bit | ` ` MEDIA_BUS_FMT_UYYVYY8_0_5X24 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 2 : 0 10 bits | ` ` MEDIA_BUS_FMT_UYYVYY10_0_5X30 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 2 : 0 12 bits | ` ` MEDIA_BUS_FMT_UYYVYY12_0_5X36 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
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* | YCbCr 4 : 2 : 0 16 bits | ` ` MEDIA_BUS_FMT_UYYVYY16_0_5X48 ` ` | ` ` V4L2_YCBCR_ENC_601 ` ` |
* | | | or ` ` V4L2_YCBCR_ENC_709 ` ` |
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* + - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
*/
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enum {
DW_HDMI_RES_8 ,
DW_HDMI_RES_10 ,
DW_HDMI_RES_12 ,
DW_HDMI_RES_MAX ,
} ;
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enum dw_hdmi_phy_type {
DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00 ,
DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2 ,
DW_HDMI_PHY_DWC_MHL_PHY = 0xc2 ,
DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2 ,
DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2 ,
DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3 ,
DW_HDMI_PHY_VENDOR_PHY = 0xfe ,
} ;
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struct dw_hdmi_mpll_config {
unsigned long mpixelclock ;
struct {
u16 cpce ;
u16 gmp ;
} res [ DW_HDMI_RES_MAX ] ;
} ;
struct dw_hdmi_curr_ctrl {
unsigned long mpixelclock ;
u16 curr [ DW_HDMI_RES_MAX ] ;
} ;
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struct dw_hdmi_phy_config {
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unsigned long mpixelclock ;
u16 sym_ctr ; /*clock symbol and transmitter control*/
u16 term ; /*transmission termination value*/
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u16 vlev_ctr ; /* voltage level control */
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} ;
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struct dw_hdmi_phy_ops {
int ( * init ) ( struct dw_hdmi * hdmi , void * data ,
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const struct drm_display_info * display ,
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const struct drm_display_mode * mode ) ;
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void ( * disable ) ( struct dw_hdmi * hdmi , void * data ) ;
enum drm_connector_status ( * read_hpd ) ( struct dw_hdmi * hdmi , void * data ) ;
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void ( * update_hpd ) ( struct dw_hdmi * hdmi , void * data ,
bool force , bool disabled , bool rxsense ) ;
void ( * setup_hpd ) ( struct dw_hdmi * hdmi , void * data ) ;
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} ;
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struct dw_hdmi_plat_data {
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struct regmap * regm ;
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unsigned int output_port ;
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unsigned long input_bus_encoding ;
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bool use_drm_infoframe ;
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bool ycbcr_420_allowed ;
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/*
* Private data passed to all the . mode_valid ( ) and . configure_phy ( )
* callback functions .
*/
void * priv_data ;
/* Platform-specific mode validation (optional). */
enum drm_mode_status ( * mode_valid ) ( struct dw_hdmi * hdmi , void * data ,
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const struct drm_display_info * info ,
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const struct drm_display_mode * mode ) ;
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/* Platform-specific audio enable/disable (optional) */
void ( * enable_audio ) ( struct dw_hdmi * hdmi , int channel ,
int width , int rate , int non_pcm ) ;
void ( * disable_audio ) ( struct dw_hdmi * hdmi ) ;
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/* Vendor PHY support */
const struct dw_hdmi_phy_ops * phy_ops ;
const char * phy_name ;
void * phy_data ;
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unsigned int phy_force_vendor ;
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/* Synopsys PHY support */
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const struct dw_hdmi_mpll_config * mpll_cfg ;
const struct dw_hdmi_curr_ctrl * cur_ctr ;
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const struct dw_hdmi_phy_config * phy_config ;
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int ( * configure_phy ) ( struct dw_hdmi * hdmi , void * data ,
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unsigned long mpixelclock ) ;
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unsigned int disable_cec : 1 ;
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} ;
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struct dw_hdmi * dw_hdmi_probe ( struct platform_device * pdev ,
const struct dw_hdmi_plat_data * plat_data ) ;
void dw_hdmi_remove ( struct dw_hdmi * hdmi ) ;
void dw_hdmi_unbind ( struct dw_hdmi * hdmi ) ;
struct dw_hdmi * dw_hdmi_bind ( struct platform_device * pdev ,
struct drm_encoder * encoder ,
const struct dw_hdmi_plat_data * plat_data ) ;
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void dw_hdmi_resume ( struct dw_hdmi * hdmi ) ;
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void dw_hdmi_setup_rx_sense ( struct dw_hdmi * hdmi , bool hpd , bool rx_sense ) ;
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int dw_hdmi_set_plugged_cb ( struct dw_hdmi * hdmi , hdmi_codec_plugged_cb fn ,
struct device * codec_dev ) ;
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void dw_hdmi_set_sample_non_pcm ( struct dw_hdmi * hdmi , unsigned int non_pcm ) ;
void dw_hdmi_set_sample_width ( struct dw_hdmi * hdmi , unsigned int width ) ;
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void dw_hdmi_set_sample_rate ( struct dw_hdmi * hdmi , unsigned int rate ) ;
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void dw_hdmi_set_channel_count ( struct dw_hdmi * hdmi , unsigned int cnt ) ;
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void dw_hdmi_set_channel_status ( struct dw_hdmi * hdmi , u8 * channel_status ) ;
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void dw_hdmi_set_channel_allocation ( struct dw_hdmi * hdmi , unsigned int ca ) ;
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void dw_hdmi_audio_enable ( struct dw_hdmi * hdmi ) ;
void dw_hdmi_audio_disable ( struct dw_hdmi * hdmi ) ;
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void dw_hdmi_set_high_tmds_clock_ratio ( struct dw_hdmi * hdmi ,
const struct drm_display_info * display ) ;
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/* PHY configuration */
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void dw_hdmi_phy_i2c_set_addr ( struct dw_hdmi * hdmi , u8 address ) ;
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void dw_hdmi_phy_i2c_write ( struct dw_hdmi * hdmi , unsigned short data ,
unsigned char addr ) ;
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void dw_hdmi_phy_gen1_reset ( struct dw_hdmi * hdmi ) ;
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void dw_hdmi_phy_gen2_pddq ( struct dw_hdmi * hdmi , u8 enable ) ;
void dw_hdmi_phy_gen2_txpwron ( struct dw_hdmi * hdmi , u8 enable ) ;
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void dw_hdmi_phy_gen2_reset ( struct dw_hdmi * hdmi ) ;
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enum drm_connector_status dw_hdmi_phy_read_hpd ( struct dw_hdmi * hdmi ,
void * data ) ;
void dw_hdmi_phy_update_hpd ( struct dw_hdmi * hdmi , void * data ,
bool force , bool disabled , bool rxsense ) ;
void dw_hdmi_phy_setup_hpd ( struct dw_hdmi * hdmi , void * data ) ;
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bool dw_hdmi_bus_fmt_is_420 ( struct dw_hdmi * hdmi ) ;
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# endif /* __IMX_HDMI_H__ */