2005-04-17 02:20:36 +04:00
/ *
* Low- l e v e l S L B r o u t i n e s
*
* Copyright ( C ) 2 0 0 4 D a v i d G i b s o n < d w g @au.ibm.com>, IBM
*
* Based o n e a r l i e r C v e r s i o n :
* Dave E n g e b r e t s e n a n d M i k e C o r r i g a n { e n g e b r e t | m i k e j c } @us.ibm.com
* Copyright ( c ) 2 0 0 1 D a v e E n g e b r e t s e n
* Copyright ( C ) 2 0 0 2 A n t o n B l a n c h a r d < a n t o n @au.ibm.com>, IBM
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* as p u b l i s h e d b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version
* 2 of t h e L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
* /
# include < a s m / p r o c e s s o r . h >
# include < a s m / p p c _ a s m . h >
2005-09-09 22:57:26 +04:00
# include < a s m / a s m - o f f s e t s . h >
2005-04-17 02:20:36 +04:00
# include < a s m / c p u t a b l e . h >
2005-11-07 03:06:55 +03:00
# include < a s m / p a g e . h >
# include < a s m / m m u . h >
# include < a s m / p g t a b l e . h >
2006-09-25 12:19:00 +04:00
# include < a s m / f i r m w a r e . h >
2005-04-17 02:20:36 +04:00
2005-11-07 03:06:55 +03:00
/ * void s l b _ a l l o c a t e _ r e a l m o d e ( u n s i g n e d l o n g e a ) ;
2005-04-17 02:20:36 +04:00
*
* Create a n S L B e n t r y f o r t h e g i v e n E A ( u s e r o r k e r n e l ) .
* r3 = f a u l t i n g a d d r e s s , r13 = P A C A
* r9 , r10 , r11 a r e c l o b b e r e d b y t h i s f u n c t i o n
* No o t h e r r e g i s t e r s a r e e x a m i n e d o r c h a n g e d .
* /
2005-11-07 03:06:55 +03:00
_ GLOBAL( s l b _ a l l o c a t e _ r e a l m o d e )
2013-03-13 07:34:54 +04:00
/ *
* check f o r b a d k e r n e l / u s e r a d d r e s s
* ( ea & ~ R E G I O N _ M A S K ) > = P G T A B L E _ R A N G E
* /
rldicr. r9 ,r3 ,4 ,( 6 3 - 4 6 - 4 )
bne- 8 f
2005-04-17 02:20:36 +04:00
srdi r9 ,r3 ,6 0 / * g e t r e g i o n * /
2013-03-13 07:34:54 +04:00
srdi r10 ,r3 ,S I D _ S H I F T / * g e t e s i d * /
2005-12-05 19:24:33 +03:00
cmpldi c r7 ,r9 ,0 x c / * c m p P A G E _ O F F S E T f o r l a t e r u s e * /
2005-04-17 02:20:36 +04:00
2005-12-05 19:24:33 +03:00
/* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
2005-04-17 02:20:36 +04:00
blt c r7 ,0 f / * u s e r o r k e r n e l ? * /
/* kernel address: proto-VSID = ESID */
/ * WARNING - M A G I C : w e d o n ' t u s e t h e V S I D 0 x f f f f f f f f f , b u t
* this c o d e w i l l g e n e r a t e t h e p r o t o V S I D 0 x f f f f f f f f f f o r t h e
* top s e g m e n t . T h a t ' s o k , t h e s c r a m b l e b e l o w w i l l t r a n s l a t e
* it t o V S I D 0 , w h i c h i s r e s e r v e d a s a b a d V S I D - o n e w h i c h
* will n e v e r h a v e a n y p a g e s i n i t . * /
[POWERPC] vmemmap fixes to use smaller pages
This changes vmemmap to use a different region (region 0xf) of the
address space, and to configure the page size of that region
dynamically at boot.
The problem with the current approach of always using 16M pages is that
it's not well suited to machines that have small amounts of memory such
as small partitions on pseries, or PS3's.
In fact, on the PS3, failure to allocate the 16M page backing vmmemmap
tends to prevent hotplugging the HV's "additional" memory, thus limiting
the available memory even more, from my experience down to something
like 80M total, which makes it really not very useable.
The logic used by my match to choose the vmemmap page size is:
- If 16M pages are available and there's 1G or more RAM at boot,
use that size.
- Else if 64K pages are available, use that
- Else use 4K pages
I've tested on a POWER6 (16M pages) and on an iSeries POWER3 (4K pages)
and it seems to work fine.
Note that I intend to change the way we organize the kernel regions &
SLBs so the actual region will change from 0xf back to something else at
one point, as I simplify the SLB miss handler, but that will be for a
later patch.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-30 09:41:48 +04:00
/ * Check i f h i t t i n g t h e l i n e a r m a p p i n g o r s o m e o t h e r k e r n e l s p a c e
2005-11-07 03:06:55 +03:00
* /
bne c r7 ,1 f
/ * Linear m a p p i n g e n c o d i n g b i t s , t h e " l i " i n s t r u c t i o n b e l o w w i l l
* be p a t c h e d b y t h e k e r n e l a t b o o t
* /
_ GLOBAL( s l b _ m i s s _ k e r n e l _ l o a d _ l i n e a r )
li r11 ,0
2012-09-10 06:52:55 +04:00
/ *
2013-03-13 07:34:54 +04:00
* context = ( M A X _ U S E R _ C O N T E X T ) + ( ( e a > > 6 0 ) - 0 x c ) + 1
* r9 = r e g i o n i d .
2012-09-10 06:52:55 +04:00
* /
2013-03-13 07:34:54 +04:00
addis r9 ,r9 ,( M A X _ U S E R _ C O N T E X T - 0 x c + 1 ) @ha
addi r9 ,r9 ,( M A X _ U S E R _ C O N T E X T - 0 x c + 1 ) @l
2007-10-11 14:37:10 +04:00
BEGIN_ F T R _ S E C T I O N
2005-11-07 03:06:55 +03:00
b s l b _ f i n i s h _ l o a d
2011-04-06 23:48:50 +04:00
END_ M M U _ F T R _ S E C T I O N _ I F C L R ( M M U _ F T R _ 1 T _ S E G M E N T )
2007-10-11 14:37:10 +04:00
b s l b _ f i n i s h _ l o a d _ 1 T
2005-11-07 03:06:55 +03:00
[POWERPC] vmemmap fixes to use smaller pages
This changes vmemmap to use a different region (region 0xf) of the
address space, and to configure the page size of that region
dynamically at boot.
The problem with the current approach of always using 16M pages is that
it's not well suited to machines that have small amounts of memory such
as small partitions on pseries, or PS3's.
In fact, on the PS3, failure to allocate the 16M page backing vmmemmap
tends to prevent hotplugging the HV's "additional" memory, thus limiting
the available memory even more, from my experience down to something
like 80M total, which makes it really not very useable.
The logic used by my match to choose the vmemmap page size is:
- If 16M pages are available and there's 1G or more RAM at boot,
use that size.
- Else if 64K pages are available, use that
- Else use 4K pages
I've tested on a POWER6 (16M pages) and on an iSeries POWER3 (4K pages)
and it seems to work fine.
Note that I intend to change the way we organize the kernel regions &
SLBs so the actual region will change from 0xf back to something else at
one point, as I simplify the SLB miss handler, but that will be for a
later patch.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-30 09:41:48 +04:00
1 :
# ifdef C O N F I G _ S P A R S E M E M _ V M E M M A P
/* Check virtual memmap region. To be patches at kernel boot */
cmpldi c r0 ,r9 ,0 x f
bne 1 f
_ GLOBAL( s l b _ m i s s _ k e r n e l _ l o a d _ v m e m m a p )
li r11 ,0
b 6 f
1 :
# endif / * C O N F I G _ S P A R S E M E M _ V M E M M A P * /
2009-10-13 00:43:47 +04:00
/ * vmalloc m a p p i n g g e t s t h e e n c o d i n g f r o m t h e P A C A a s t h e m a p p i n g
* can b e d e m o t e d f r o m 6 4 K - > 4 K d y n a m i c a l l y o n s o m e m a c h i n e s
2005-11-07 03:06:55 +03:00
* /
2006-06-15 04:45:18 +04:00
clrldi r11 ,r10 ,4 8
cmpldi r11 ,( V M A L L O C _ S I Z E > > 2 8 ) - 1
bgt 5 f
lhz r11 ,P A C A V M A L L O C S L L P ( r13 )
2007-10-11 14:37:10 +04:00
b 6 f
2006-06-15 04:45:18 +04:00
5 :
2009-10-13 00:43:47 +04:00
/* IO mapping */
_ GLOBAL( s l b _ m i s s _ k e r n e l _ l o a d _ i o )
2005-11-07 03:06:55 +03:00
li r11 ,0
2007-10-11 14:37:10 +04:00
6 :
2012-09-10 06:52:55 +04:00
/ *
2013-03-13 07:34:54 +04:00
* context = ( M A X _ U S E R _ C O N T E X T ) + ( ( e a > > 6 0 ) - 0 x c ) + 1
* r9 = r e g i o n i d .
2012-09-10 06:52:55 +04:00
* /
2013-03-13 07:34:54 +04:00
addis r9 ,r9 ,( M A X _ U S E R _ C O N T E X T - 0 x c + 1 ) @ha
addi r9 ,r9 ,( M A X _ U S E R _ C O N T E X T - 0 x c + 1 ) @l
2007-10-11 14:37:10 +04:00
BEGIN_ F T R _ S E C T I O N
2005-11-07 03:06:55 +03:00
b s l b _ f i n i s h _ l o a d
2011-04-06 23:48:50 +04:00
END_ M M U _ F T R _ S E C T I O N _ I F C L R ( M M U _ F T R _ 1 T _ S E G M E N T )
2007-10-11 14:37:10 +04:00
b s l b _ f i n i s h _ l o a d _ 1 T
2005-11-07 03:06:55 +03:00
2013-03-13 07:34:54 +04:00
0 :
2007-05-08 10:27:27 +04:00
/ * when u s i n g s l i c e s , w e e x t r a c t t h e p s i z e o f f t h e s l i c e b i t m a p s
* and t h e n w e n e e d t o g e t t h e s l l p e n c o d i n g o f f t h e m m u _ p s i z e _ d e f s
* array.
*
* XXX T h i s i s a b i t i n e f f i c i e n t e s p e c i a l l y f o r t h e n o r m a l c a s e ,
* so w e s h o u l d t r y t o i m p l e m e n t a f a s t p a t h f o r t h e s t a n d a r d p a g e
* size u s i n g t h e o l d s l l p v a l u e s o w e a v o i d t h e a r r a y . W e c a n n o t
* really d o d y n a m i c p a t c h i n g u n f o r t u n a t e l y a s p r o c e s s e s m i g h t f l i p
* between 4 k a n d 6 4 k s t a n d a r d p a g e s i z e
* /
# ifdef C O N F I G _ P P C _ M M _ S L I C E S
2012-09-10 06:52:52 +04:00
/* r10 have esid */
[PATCH] ppc64: Fix bug in SLB miss handler for hugepages
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad5653491813959277fb87a2fef54c4e05) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 11:57:52 +03:00
cmpldi r10 ,1 6
2012-09-10 06:52:52 +04:00
/* below SLICE_LOW_TOP */
[PATCH] ppc64: Fix bug in SLB miss handler for hugepages
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad5653491813959277fb87a2fef54c4e05) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 11:57:52 +03:00
blt 5 f
2012-09-10 06:52:52 +04:00
/ *
* Handle h p s i z e s ,
* r9 i s g e t _ p a c a ( ) - > c o n t e x t . h i g h _ s l i c e s _ p s i z e [ i n d e x ] , r11 i s m a s k _ i n d e x
* /
srdi r11 ,r10 ,( S L I C E _ H I G H _ S H I F T - S L I C E _ L O W _ S H I F T + 1 ) / * i n d e x * /
addi r9 ,r11 ,P A C A H I G H S L I C E P S I Z E
lbzx r9 ,r13 ,r9 / * r9 i s h p s i z e s [ r11 ] * /
/* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
rldicl r11 ,r10 ,( 6 4 - ( S L I C E _ H I G H _ S H I F T - S L I C E _ L O W _ S H I F T ) ) ,6 3
b 6 f
[PATCH] ppc64: Fix bug in SLB miss handler for hugepages
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad5653491813959277fb87a2fef54c4e05) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 11:57:52 +03:00
2012-09-10 06:52:52 +04:00
5 :
/ *
* Handle l p s i z e s
* r9 i s g e t _ p a c a ( ) - > c o n t e x t . l o w _ s l i c e s _ p s i z e , r11 i s i n d e x
* /
ld r9 ,P A C A L O W S L I C E S P S I Z E ( r13 )
mr r11 ,r10
6 :
sldi r11 ,r11 ,2 / * i n d e x * 4 * /
/* Extract the psize and multiply to get an array offset */
2007-05-08 10:27:27 +04:00
srd r9 ,r9 ,r11
andi. r9 ,r9 ,0 x f
mulli r9 ,r9 ,M M U P S I Z E D E F S I Z E
2005-08-11 10:55:21 +04:00
2007-05-08 10:27:27 +04:00
/ * Now g e t t o t h e a r r a y a n d o b t a i n t h e s l l p
* /
ld r11 ,P A C A T O C ( r13 )
ld r11 ,m m u _ p s i z e _ d e f s @got(r11)
add r11 ,r11 ,r9
ld r11 ,M M U P S I Z E S L L P ( r11 )
ori r11 ,r11 ,S L B _ V S I D _ U S E R
# else
/* paca context sllp already contains the SLB_VSID_USER bits */
2006-06-15 04:45:18 +04:00
lhz r11 ,P A C A C O N T E X T S L L P ( r13 )
2007-05-08 10:27:27 +04:00
# endif / * C O N F I G _ P P C _ M M _ S L I C E S * /
2005-11-07 03:06:55 +03:00
ld r9 ,P A C A C O N T E X T I D ( r13 )
2007-10-11 14:37:10 +04:00
BEGIN_ F T R _ S E C T I O N
cmpldi r10 ,0 x10 0 0
bge s l b _ f i n i s h _ l o a d _ 1 T
2011-04-06 23:48:50 +04:00
END_ M M U _ F T R _ S E C T I O N _ I F S E T ( M M U _ F T R _ 1 T _ S E G M E N T )
2005-11-07 03:06:55 +03:00
b s l b _ f i n i s h _ l o a d
8 : /* invalid EA */
li r10 ,0 / * B A D _ V S I D * /
2013-03-13 07:34:54 +04:00
li r9 ,0 / * B A D _ V S I D * /
2005-11-07 03:06:55 +03:00
li r11 ,S L B _ V S I D _ U S E R / * f l a g s d o n ' t m u c h m a t t e r * /
b s l b _ f i n i s h _ l o a d
# ifdef _ _ D I S A B L E D _ _
/ * void s l b _ a l l o c a t e _ u s e r ( u n s i g n e d l o n g e a ) ;
*
* Create a n S L B e n t r y f o r t h e g i v e n E A ( u s e r o r k e r n e l ) .
* r3 = f a u l t i n g a d d r e s s , r13 = P A C A
* r9 , r10 , r11 a r e c l o b b e r e d b y t h i s f u n c t i o n
* No o t h e r r e g i s t e r s a r e e x a m i n e d o r c h a n g e d .
*
* It i s c a l l e d w i t h t r a n s l a t i o n e n a b l e d i n o r d e r t o b e a b l e t o w a l k t h e
* page t a b l e s . T h i s i s n o t c u r r e n t l y u s e d .
* /
_ GLOBAL( s l b _ a l l o c a t e _ u s e r )
/* r3 = faulting address */
srdi r10 ,r3 ,2 8 / * g e t e s i d * /
crset 4 * c r7 + l t / * s e t " u s e r " f l a g f o r l a t e r * /
/* check if we fit in the range covered by the pagetables*/
srdi. r9 ,r3 ,P G T A B L E _ E A D D R _ S I Z E
crnot 4 * c r0 + e q ,4 * c r0 + e q
beqlr
2005-04-17 02:20:36 +04:00
2005-11-07 03:06:55 +03:00
/ * now w e n e e d t o g e t t o t h e p a g e t a b l e s i n o r d e r t o g e t t h e p a g e
* size e n c o d i n g f r o m t h e P M D . I n t h e f u t u r e , w e ' l l b e a b l e t o d e a l
* with 1 T s e g m e n t s t o o b y g e t t i n g t h e e n c o d i n g f r o m t h e P G D i n s t e a d
* /
ld r9 ,P A C A P G D I R ( r13 )
cmpldi c r0 ,r9 ,0
beqlr
rlwinm r11 ,r10 ,8 ,2 5 ,2 8
ldx r9 ,r9 ,r11 / * g e t p g d _ t * /
cmpldi c r0 ,r9 ,0
beqlr
rlwinm r11 ,r10 ,3 ,1 7 ,2 8
ldx r9 ,r9 ,r11 / * g e t p m d _ t * /
cmpldi c r0 ,r9 ,0
beqlr
/* build vsid flags */
andi. r11 ,r9 ,S L B _ V S I D _ L L P
ori r11 ,r11 ,S L B _ V S I D _ U S E R
/* get context to calculate proto-VSID */
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ld r9 ,P A C A C O N T E X T I D ( r13 )
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/* fall through slb_finish_load */
# endif / * _ _ D I S A B L E D _ _ * /
2005-04-17 02:20:36 +04:00
2005-11-07 03:06:55 +03:00
/ *
* Finish l o a d i n g o f a n S L B e n t r y a n d r e t u r n
*
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* r3 = E A , r9 = c o n t e x t , r10 = E S I D , r11 = f l a g s , c l o b b e r s r9 , c r7 = < > P A G E _ O F F S E T
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* /
slb_finish_load :
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rldimi r10 ,r9 ,E S I D _ B I T S ,0
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ASM_ V S I D _ S C R A M B L E ( r10 ,r9 ,2 5 6 M )
2012-09-10 06:52:53 +04:00
/ *
* bits a b o v e V S I D _ B I T S _ 2 5 6 M n e e d t o b e i g n o r e d f r o m r10
* also c o m b i n e V S I D a n d f l a g s
* /
rldimi r11 ,r10 ,S L B _ V S I D _ S H I F T ,( 6 4 - ( S L B _ V S I D _ S H I F T + V S I D _ B I T S _ 2 5 6 M ) )
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/* r3 = EA, r11 = VSID data */
/ *
* Find a s l o t , r o u n d r o b i n . P r e v i o u s l y w e t r i e d t o f i n d a
* free s l o t f i r s t b u t t h a t t o o k t o o l o n g . U n f o r t u n a t e l y w e
* dont h a v e a n y L R U i n f o r m a t i o n t o h e l p u s c h o o s e a s l o t .
* /
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7 : ld r10 ,P A C A S T A B R R ( r13 )
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addi r10 ,r10 ,1
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/* This gets soft patched on boot. */
_ GLOBAL( s l b _ c o m p a r e _ r r _ t o _ s i z e )
cmpldi r10 ,0
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blt+ 4 f
li r10 ,S L B _ N U M _ B O L T E D
4 :
std r10 ,P A C A S T A B R R ( r13 )
3 :
rldimi r3 ,r10 ,0 ,3 6 / * r3 = E A [ 0 : 3 5 ] | e n t r y * /
oris r10 ,r3 ,S L B _ E S I D _ V @h /* r3 |= SLB_ESID_V */
/* r3 = ESID data, r11 = VSID data */
2005-04-17 02:20:36 +04:00
/ *
* No n e e d f o r a n i s y n c b e f o r e o r a f t e r t h i s s l b m t e . T h e e x c e p t i o n
* we e n t e r w i t h a n d t h e r f i d w e e x i t w i t h a r e c o n t e x t s y n c h r o n i z i n g .
* /
slbmte r11 ,r10
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/* we're done for kernel addresses */
crclr 4 * c r0 + e q / * s e t r e s u l t t o " s u c c e s s " * /
bgelr c r7
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/* Update the slb cache */
lhz r3 ,P A C A S L B C A C H E P T R ( r13 ) / * o f f s e t = p a c a - > s l b _ c a c h e _ p t r * /
cmpldi r3 ,S L B _ C A C H E _ E N T R I E S
bge 1 f
/* still room in the slb cache */
2012-09-10 06:52:54 +04:00
sldi r11 ,r3 ,2 / * r11 = o f f s e t * s i z e o f ( u 3 2 ) * /
srdi r10 ,r10 ,2 8 / * g e t t h e 3 6 b i t s o f t h e E S I D * /
add r11 ,r11 ,r13 / * r11 = ( u 3 2 * ) p a c a + o f f s e t * /
stw r10 ,P A C A S L B C A C H E ( r11 ) / * p a c a - > s l b _ c a c h e [ o f f s e t ] = e s i d * /
2005-04-17 02:20:36 +04:00
addi r3 ,r3 ,1 / * o f f s e t + + * /
b 2 f
1 : /* offset >= SLB_CACHE_ENTRIES */
li r3 ,S L B _ C A C H E _ E N T R I E S + 1
2 :
sth r3 ,P A C A S L B C A C H E P T R ( r13 ) / * p a c a - > s l b _ c a c h e _ p t r = o f f s e t * /
2005-11-07 03:06:55 +03:00
crclr 4 * c r0 + e q / * s e t r e s u l t t o " s u c c e s s " * /
2005-04-17 02:20:36 +04:00
blr
2007-10-11 14:37:10 +04:00
/ *
* Finish l o a d i n g o f a 1 T S L B e n t r y ( f o r t h e k e r n e l l i n e a r m a p p i n g ) a n d r e t u r n .
*
2013-03-13 07:34:54 +04:00
* r3 = E A , r9 = c o n t e x t , r10 = E S I D ( 2 5 6 M B ) , r11 = f l a g s , c l o b b e r s r9
2007-10-11 14:37:10 +04:00
* /
slb_finish_load_1T :
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srdi r10 ,r10 ,( S I D _ S H I F T _ 1 T - S I D _ S H I F T ) / * g e t 1 T E S I D * /
2013-03-13 07:34:55 +04:00
rldimi r10 ,r9 ,E S I D _ B I T S _ 1 T ,0
2007-10-11 14:37:10 +04:00
ASM_ V S I D _ S C R A M B L E ( r10 ,r9 ,1 T )
2012-09-10 06:52:53 +04:00
/ *
* bits a b o v e V S I D _ B I T S _ 1 T n e e d t o b e i g n o r e d f r o m r10
* also c o m b i n e V S I D a n d f l a g s
* /
rldimi r11 ,r10 ,S L B _ V S I D _ S H I F T _ 1 T ,( 6 4 - ( S L B _ V S I D _ S H I F T _ 1 T + V S I D _ B I T S _ 1 T ) )
2007-10-11 14:37:10 +04:00
li r10 ,M M U _ S E G S I Z E _ 1 T
rldimi r11 ,r10 ,S L B _ V S I D _ S S I Z E _ S H I F T ,0 / * i n s e r t s e g m e n t s i z e * /
/* r3 = EA, r11 = VSID data */
clrrdi r3 ,r3 ,S I D _ S H I F T _ 1 T / * c l e a r o u t n o n - E S I D b i t s * /
b 7 b
