linux/drivers/pinctrl/ralink/Kconfig

# SPDX-License-Identifier: GPL-2.0-only
menu "Ralink pinctrl drivers"
        depends on RALINK

config PINCTRL_RALINK
        bool "Ralink pin control support"
        default y if RALINK

config PINCTRL_RT2880
        bool "RT2880 pinctrl driver for RALINK/Mediatek SOCs"
        select PINMUX
        select GENERIC_PINCONF

config PINCTRL_MT7621
        bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs"
        depends on RALINK && SOC_MT7621
        select PINCTRL_RT2880

endmenu
pinctrl: ralink: add a pinctrl driver for the rt2880 family These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each pin individually, these socs have mux groups that when set will effect 1-N pins. Pin groups have a 2, 4 or 8 different muxes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2020-12-08 08:55:23 +01:00			`# SPDX-License-Identifier: GPL-2.0-only`
			`menu "Ralink pinctrl drivers"`
			`depends on RALINK`

			`config PINCTRL_RALINK`
			`bool "Ralink pin control support"`
			`default y if RALINK`

			`config PINCTRL_RT2880`
			`bool "RT2880 pinctrl driver for RALINK/Mediatek SOCs"`
			`select PINMUX`
			`select GENERIC_PINCONF`

pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file Move all related code for SoC MT7621 into a new driver located in 'pinctrl-mt7621.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-3-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2021-06-04 13:51:55 +02:00			`config PINCTRL_MT7621`
			`bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs"`
			`depends on RALINK && SOC_MT7621`
			`select PINCTRL_RT2880`

pinctrl: ralink: add a pinctrl driver for the rt2880 family These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each pin individually, these socs have mux groups that when set will effect 1-N pins. Pin groups have a 2, 4 or 8 different muxes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2020-12-08 08:55:23 +01:00			`endmenu`