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linux/arch/arm/boot/dts/sun5i-a13.dtsi

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ARM: sunxi: Add device tree for the A13 and the Olinuxino board Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-14 20:17:04 +01:00
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
/include/ "skeleton.dtsi"
ARM: sunxi: Add device tree for the A13 and the Olinuxino board Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-14 20:17:04 +01:00
/ {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
interrupt-parent = <&intc>;
cpus {
ARM: dts: add missing cpu #address-cell values A recent series has added CPU numbers to a lot of dts files, but unfortunately in a few cases the #address-cells and #size-cells values are missing, which causes build warnings. This adds the missing ones for sunxi and sama5 that I found through build testing. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2013-06-10 16:48:36 +02:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
cpu@0 {
ARM: dts: sunxi: cpus/cpu nodes dts updates This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-18 18:41:57 +01:00
device_type = "cpu";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
compatible = "arm,cortex-a8";
ARM: dts: sunxi: cpus/cpu nodes dts updates This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-18 18:41:57 +01:00
reg = <0x0>;
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
};
};
ARM: sunxi: Add device tree for the A13 and the Olinuxino board Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-14 20:17:04 +01:00
memory {
reg = <0x40000000 0x20000000>;
};
ARM: sunxi: Add pinctrl node to the device tree Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 22:30:36 +01:00
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
dummy: dummy {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
osc24M: osc24M@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
reg = <0x01c20050 0x4>;
ARM: sunxi: unify osc24M_fixed and osc24M Now that the clock driver supports the gatable oscillator as one single clock, drop osc24M_fixed and move the relevant properties to osc24M Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-09 10:48:04 -03:00
clock-frequency = <24000000>;
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
};
osc32k: osc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};
ARM: sunxi: add PLL4 support This commit adds the PLL4 definition to the sun4i, sun5i and sun7i device trees. PLL4 is compatible with PLL1. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 00:32:35 -03:00
pll4: pll4@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
};
ARM: sunxi: add PLL5 and PLL6 support This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 00:32:38 -03:00
pll5: pll5@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
pll6: pll6@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
};
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
};
axi_gates: axi_gates@01c2005c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-output-names = "axi_dram";
};
ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
};
ahb_gates: ahb_gates@01c20060 {
#clock-cells = <1>;
ARM: sun5i: Update the clock compatible strings The Allwinner A13 has a smaller clock set than the one found in the A10. Fix the A13 device tree and documentation to reflect this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 22:14:41 +02:00
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
ARM: sun5i: Update the clock compatible strings The Allwinner A13 has a smaller clock set than the one found in the A10. Fix the A13 device tree and documentation to reflect this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 22:14:41 +02:00
clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
"ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
"ahb_de_fe", "ahb_iep", "ahb_mali400";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
};
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
};
apb0_gates: apb0_gates@01c20068 {
#clock-cells = <1>;
ARM: sun5i: Update the clock compatible strings The Allwinner A13 has a smaller clock set than the one found in the A10. Fix the A13 device tree and documentation to reflect this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 22:14:41 +02:00
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
ARM: sun5i: Update the clock compatible strings The Allwinner A13 has a smaller clock set than the one found in the A10. Fix the A13 device tree and documentation to reflect this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 22:14:41 +02:00
clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
};
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
ARM: sunxi: add PLL5 and PLL6 support This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 00:32:38 -03:00
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
};
apb1_gates: apb1_gates@01c2006c {
#clock-cells = <1>;
ARM: sun5i: Update the clock compatible strings The Allwinner A13 has a smaller clock set than the one found in the A10. Fix the A13 device tree and documentation to reflect this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 22:14:41 +02:00
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
ARM: sun5i: Update the clock compatible strings The Allwinner A13 has a smaller clock set than the one found in the A10. Fix the A13 device tree and documentation to reflect this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-04-19 22:14:41 +02:00
"apb1_i2c2", "apb1_uart1", "apb1_uart3";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
};
ARM: sun5i: dt: mod0 clocks This commit adds all the mod0 clocks available on A10 and A13. The list has been constructed by looking at the Allwinner code release for A10S and A13. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 00:32:42 -03:00
nand_clk: clk@01c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
};
ms_clk: clk@01c20084 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c20084 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ms";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
};
ts_clk: clk@01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c20098 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ts";
};
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ss";
};
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi0";
};
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi1";
};
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi2";
};
ir0_clk: clk@01c200b0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c200b0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir0";
};
ARM: sunxi: dt: add nodes for the mbus clock mbus is the memory bus clock, and it is present on both sun5i and sun7i machines. Its register layout is compatible with the mod0 one. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-23 00:32:44 -03:00
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-mod0-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mbus";
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
};
ARM: sun5i: dt: Fix A13 SoC bus base address There was a typo in the base address used for the soc node in the A13 device tree. Fix it with the proper base address. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-03 16:07:36 +02:00
soc@01c00000 {
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
intc: interrupt-controller@01c20400 {
ARM: sunxi: dt: Update interrupt controller compatible string Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-24 19:20:52 +01:00
compatible = "allwinner,sun4i-ic";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
sunxi: dts: Report the pinctrl nodes as gpio-controllers Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-01-27 19:26:05 +01:00
pio: pinctrl@01c20800 {
ARM: sunxi: Add pinctrl node to the device tree Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 22:30:36 +01:00
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
ARM: sunxi: dt: Register the pio node as interrupt controller Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-06 15:00:48 +02:00
interrupts = <28>;
arm: sunxi: Add clock to pinctrl node The port controller needs the apb0_pio clock enabled to be able to work. This commit declares that on the device tree. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-27 18:20:41 -03:00
clocks = <&apb0_gates 5>;
sunxi: dts: Report the pinctrl nodes as gpio-controllers Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-01-27 19:26:05 +01:00
gpio-controller;
ARM: sunxi: dt: Register the pio node as interrupt controller Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-06 15:00:48 +02:00
interrupt-controller;
ARM: sunxi: Add pinctrl node to the device tree Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 22:30:36 +01:00
#address-cells = <1>;
#size-cells = <0>;
sunxi: dts: Report the pinctrl nodes as gpio-controllers Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-01-27 19:26:05 +01:00
#gpio-cells = <3>;
ARM: sunxi: Add uart1 pinctrl groups Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 22:30:37 +01:00
uart1_pins_a: uart1@0 {
allwinner,pins = "PE10", "PE11";
allwinner,function = "uart1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart1_pins_b: uart1@1 {
allwinner,pins = "PG3", "PG4";
allwinner,function = "uart1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
ARM: sun5i: dt: Add i2c muxing options The i2c controller found on the Allwinner A13 has only one muxing option available for each controller. Add them to the dtsi Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
2013-03-10 13:36:02 +01:00
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
i2c1_pins_a: i2c1@0 {
allwinner,pins = "PB15", "PB16";
allwinner,function = "i2c1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
i2c2_pins_a: i2c2@0 {
allwinner,pins = "PB17", "PB18";
allwinner,function = "i2c2";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
ARM: sunxi: Add pinctrl node to the device tree Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 22:30:36 +01:00
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
timer@01c20c00 {
ARM: sunxi: dt: Update timer compatible string Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-24 19:00:17 +01:00
compatible = "allwinner,sun4i-timer";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
reg = <0x01c20c00 0x90>;
interrupts = <22>;
clocks = <&osc24M>;
};
wdt: watchdog@01c20c90 {
ARM: sunxi: dt: Update watchdog compatible string Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-24 19:32:34 +01:00
compatible = "allwinner,sun4i-wdt";
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
reg = <0x01c20c90 0x10>;
};
ARM: sunxi: dt: Add sunxi-sid to dts for sun4i, sun5i and sun7i This patch shall add support for the sunxi-sid driver to the device tree for A10, A10s, A13 and A20. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-09-03 12:33:28 +02:00
sid: eeprom@01c23800 {
compatible = "allwinner,sun4i-sid";
reg = <0x01c23800 0x10>;
};
ARM: dts: sun5i: Add rtp controller node Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-31 17:20:51 +01:00
rtp: rtp@01c25000 {
compatible = "allwinner,sun4i-ts";
reg = <0x01c25000 0x100>;
interrupts = <29>;
};
ARM: sunxi: dt: Reorganize the dtsi In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-13 20:07:37 +01:00
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 17>;
status = "disabled";
};
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 19>;
status = "disabled";
};
ARM: sunxi: dt: Add i2c controller nodes to the DTSI The Allwinner A10 and A13 both have 3 i2c controller embedded. Add those to the common sunxi dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
2013-03-10 13:34:36 +01:00
i2c0: i2c@01c2ac00 {
compatible = "allwinner,sun4i-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
clocks = <&apb1_gates 0>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@01c2b000 {
compatible = "allwinner,sun4i-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <8>;
clocks = <&apb1_gates 1>;
clock-frequency = <100000>;
status = "disabled";
};
i2c2: i2c@01c2b400 {
compatible = "allwinner,sun4i-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <9>;
clocks = <&apb1_gates 2>;
clock-frequency = <100000>;
status = "disabled";
};
ARM: sun5i: a13: Add support for the High Speed Timers The Allwinner A13 has support for two high speed timers. Now that we have a driver to support it, we can enable them in the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2013-11-07 12:01:48 +01:00
timer@01c60000 {
compatible = "allwinner,sun5i-a13-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <82>, <83>;
clocks = <&ahb_gates 28>;
};
ARM: sunxi: Add pinctrl node to the device tree Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 22:30:36 +01:00
};
ARM: sunxi: Add device tree for the A13 and the Olinuxino board Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2012-11-14 20:17:04 +01:00
};
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