2019-06-03 07:44:50 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
2012-03-05 11:49:28 +00:00
/ *
* Based o n a r c h / a r m / m m / p r o c . S
*
* Copyright ( C ) 2 0 0 1 D e e p B l u e S o l u t i o n s L t d .
* Copyright ( C ) 2 0 1 2 A R M L t d .
* Author : Catalin M a r i n a s < c a t a l i n . m a r i n a s @arm.com>
* /
# include < l i n u x / i n i t . h >
# include < l i n u x / l i n k a g e . h >
# include < a s m / a s s e m b l e r . h >
# include < a s m / a s m - o f f s e t s . h >
# include < a s m / h w c a p . h >
# include < a s m / p g t a b l e . h >
2016-04-27 17:47:07 +01:00
# include < a s m / p g t a b l e - h w d e f . h >
2016-02-24 17:44:57 -08:00
# include < a s m / c p u f e a t u r e . h >
# include < a s m / a l t e r n a t i v e . h >
2012-03-05 11:49:28 +00:00
2014-04-02 17:55:40 +01:00
# ifdef C O N F I G _ A R M 6 4 _ 6 4 K _ P A G E S
# define T C R _ T G _ F L A G S T C R _ T G 0 _ 6 4 K | T C R _ T G 1 _ 6 4 K
2015-10-19 14:19:37 +01:00
# elif d e f i n e d ( C O N F I G _ A R M 6 4 _ 1 6 K _ P A G E S )
# define T C R _ T G _ F L A G S T C R _ T G 0 _ 1 6 K | T C R _ T G 1 _ 1 6 K
# else / * C O N F I G _ A R M 6 4 _ 4 K _ P A G E S * /
2014-04-02 17:55:40 +01:00
# define T C R _ T G _ F L A G S T C R _ T G 0 _ 4 K | T C R _ T G 1 _ 4 K
# endif
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# ifdef C O N F I G _ R A N D O M I Z E _ B A S E
# define T C R _ K A S L R _ F L A G S T C R _ N F D 1
# else
# define T C R _ K A S L R _ F L A G S 0
# endif
2014-04-02 17:55:40 +01:00
# define T C R _ S M P _ F L A G S T C R _ S H A R E D
2012-03-05 11:49:28 +00:00
2014-04-02 17:55:40 +01:00
/* PTWs cacheable, inner/outer WBWA */
# define T C R _ C A C H E _ F L A G S T C R _ I R G N _ W B W A | T C R _ O R G N _ W B W A
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# ifdef C O N F I G _ K A S A N _ S W _ T A G S
# define T C R _ K A S A N _ F L A G S T C R _ T B I 1
# else
# define T C R _ K A S A N _ F L A G S 0
# endif
2019-12-11 18:40:09 +00:00
/* Default MAIR_EL1 */
# define M A I R _ E L 1 _ S E T \
( MAIR_ A T T R I D X ( M A I R _ A T T R _ D E V I C E _ n G n R n E , M T _ D E V I C E _ n G n R n E ) | \
MAIR_ A T T R I D X ( M A I R _ A T T R _ D E V I C E _ n G n R E , M T _ D E V I C E _ n G n R E ) | \
MAIR_ A T T R I D X ( M A I R _ A T T R _ D E V I C E _ G R E , M T _ D E V I C E _ G R E ) | \
MAIR_ A T T R I D X ( M A I R _ A T T R _ N O R M A L _ N C , M T _ N O R M A L _ N C ) | \
MAIR_ A T T R I D X ( M A I R _ A T T R _ N O R M A L , M T _ N O R M A L ) | \
MAIR_ A T T R I D X ( M A I R _ A T T R _ N O R M A L _ W T , M T _ N O R M A L _ W T ) )
2012-03-05 11:49:28 +00:00
2015-01-26 18:33:44 +00:00
# ifdef C O N F I G _ C P U _ P M
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/ * *
* cpu_ d o _ s u s p e n d - s a v e C P U r e g i s t e r s c o n t e x t
*
* x0 : virtual a d d r e s s o f c o n t e x t p o i n t e r
* /
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SYM_ F U N C _ S T A R T ( c p u _ d o _ s u s p e n d )
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mrs x2 , t p i d r _ e l 0
mrs x3 , t p i d r r o _ e l 0
mrs x4 , c o n t e x t i d r _ e l 1
2019-04-08 18:17:19 +01:00
mrs x5 , o s d l r _ e l 1
mrs x6 , c p a c r _ e l 1
mrs x7 , t c r _ e l 1
mrs x8 , v b a r _ e l 1
mrs x9 , m d s c r _ e l 1
mrs x10 , o s l s r _ e l 1
mrs x11 , s c t l r _ e l 1
2018-01-08 15:38:06 +00:00
alternative_ i f _ n o t A R M 6 4 _ H A S _ V I R T _ H O S T _ E X T N
2019-04-08 18:17:19 +01:00
mrs x12 , t p i d r _ e l 1
2018-01-08 15:38:06 +00:00
alternative_ e l s e
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mrs x12 , t p i d r _ e l 2
2018-01-08 15:38:06 +00:00
alternative_ e n d i f
2019-04-08 18:17:19 +01:00
mrs x13 , s p _ e l 0
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stp x2 , x3 , [ x0 ]
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stp x4 , x5 , [ x0 , #16 ]
stp x6 , x7 , [ x0 , #32 ]
stp x8 , x9 , [ x0 , #48 ]
stp x10 , x11 , [ x0 , #64 ]
stp x12 , x13 , [ x0 , #80 ]
2013-07-17 10:14:45 +01:00
ret
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ E N D ( c p u _ d o _ s u s p e n d )
2013-07-17 10:14:45 +01:00
/ * *
* cpu_ d o _ r e s u m e - r e s t o r e C P U r e g i s t e r c o n t e x t
*
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* x0 : Address o f c o n t e x t p o i n t e r
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* /
2018-01-29 12:00:00 +00:00
.pushsection " .idmap .text " , " awx"
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SYM_ F U N C _ S T A R T ( c p u _ d o _ r e s u m e )
2013-07-17 10:14:45 +01:00
ldp x2 , x3 , [ x0 ]
ldp x4 , x5 , [ x0 , #16 ]
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ldp x6 , x8 , [ x0 , #32 ]
ldp x9 , x10 , [ x0 , #48 ]
ldp x11 , x12 , [ x0 , #64 ]
2016-11-03 20:23:09 +00:00
ldp x13 , x14 , [ x0 , #80 ]
2013-07-17 10:14:45 +01:00
msr t p i d r _ e l 0 , x2
msr t p i d r r o _ e l 0 , x3
msr c o n t e x t i d r _ e l 1 , x4
msr c p a c r _ e l 1 , x6
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/* Don't change t0sz here, mask those bits when restoring */
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mrs x7 , t c r _ e l 1
bfi x8 , x7 , T C R _ T 0 S Z _ O F F S E T , T C R _ T x S Z _ W I D T H
2016-04-27 17:47:07 +01:00
2013-07-17 10:14:45 +01:00
msr t c r _ e l 1 , x8
msr v b a r _ e l 1 , x9
2016-08-26 16:03:42 +01:00
/ *
* _ _ cpu_ s e t u p ( ) c l e a r e d M D S C R _ E L 1 . M D E a n d f r i e n d s , b e f o r e u n m a s k i n g
* debug e x c e p t i o n s . B y r e s t o r i n g M D S C R _ E L 1 h e r e , w e m a y t a k e a d e b u g
2017-11-02 12:12:34 +00:00
* exception. M a s k t h e m u n t i l l o c a l _ d a i f _ r e s t o r e ( ) i n c p u _ s u s p e n d ( )
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* resets t h e m .
* /
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disable_ d a i f
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msr m d s c r _ e l 1 , x10
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2016-04-27 17:47:07 +01:00
msr s c t l r _ e l 1 , x12
2018-01-08 15:38:06 +00:00
alternative_ i f _ n o t A R M 6 4 _ H A S _ V I R T _ H O S T _ E X T N
2016-11-03 20:23:09 +00:00
msr t p i d r _ e l 1 , x13
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alternative_ e l s e
msr t p i d r _ e l 2 , x13
alternative_ e n d i f
2016-11-03 20:23:09 +00:00
msr s p _ e l 0 , x14
2013-07-17 10:14:45 +01:00
/ *
* Restore o s l s r _ e l 1 b y w r i t i n g o s l a r _ e l 1
* /
2019-04-08 18:17:19 +01:00
msr o s d l r _ e l 1 , x5
2013-07-17 10:14:45 +01:00
ubfx x11 , x11 , #1 , #1
msr o s l a r _ e l 1 , x11
2016-01-13 14:50:03 +00:00
reset_ p m u s e r e n r _ e l 0 x0 / / D i s a b l e P M U a c c e s s f r o m E L 0
2018-01-15 19:38:59 +00:00
alternative_ i f A R M 6 4 _ H A S _ R A S _ E X T N
msr_ s S Y S _ D I S R _ E L 1 , x z r
alternative_ e l s e _ n o p _ e n d i f
2013-07-17 10:14:45 +01:00
isb
ret
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SYM_ F U N C _ E N D ( c p u _ d o _ r e s u m e )
2016-08-24 18:27:29 +01:00
.popsection
2013-07-17 10:14:45 +01:00
# endif
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/ *
2014-01-27 07:19:32 +00:00
* cpu_ d o _ s w i t c h _ m m ( p g d _ p h y s , t s k )
2012-03-05 11:49:28 +00:00
*
* Set t h e t r a n s l a t i o n t a b l e b a s e p o i n t e r t o b e p g d _ p h y s .
*
* - pgd_ p h y s - p h y s i c a l a d d r e s s o f n e w T T B
* /
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ S T A R T ( c p u _ d o _ s w i t c h _ m m )
2017-08-10 13:19:09 +01:00
mrs x2 , t t b r1 _ e l 1
2015-10-06 18:46:24 +01:00
mmid x1 , x1 / / g e t m m - > c o n t e x t . i d
2018-01-29 11:59:57 +00:00
phys_ t o _ t t b r x3 , x0
2018-07-31 14:08:56 +01:00
alternative_ i f A R M 6 4 _ H A S _ C N P
cbz x1 , 1 f / / s k i p C N P f o r r e s e r v e d A S I D
orr x3 , x3 , #T T B R _ C N P _ B I T
1 :
alternative_ e l s e _ n o p _ e n d i f
2018-01-10 13:18:30 +00:00
# ifdef C O N F I G _ A R M 6 4 _ S W _ T T B R 0 _ P A N
2018-01-24 08:27:08 +00:00
bfi x3 , x1 , #48 , #16 / / s e t t h e A S I D f i e l d i n T T B R 0
2018-01-10 13:18:30 +00:00
# endif
2017-08-10 13:19:09 +01:00
bfi x2 , x1 , #48 , #16 / / s e t t h e A S I D
msr t t b r1 _ e l 1 , x2 / / i n T T B R 1 ( s i n c e T C R . A 1 i s s e t )
isb
2018-01-24 08:27:08 +00:00
msr t t b r0 _ e l 1 , x3 / / n o w u p d a t e T T B R 0
2012-03-05 11:49:28 +00:00
isb
2018-01-02 18:19:39 +00:00
b p o s t _ t t b r _ u p d a t e _ w o r k a r o u n d / / B a c k t o C c o d e . . .
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ E N D ( c p u _ d o _ s w i t c h _ m m )
2012-03-05 11:49:28 +00:00
2018-01-29 12:00:00 +00:00
.pushsection " .idmap .text " , " awx"
2018-02-06 22:22:50 +00:00
.macro _ _ idmap_ c p u _ s e t _ r e s e r v e d _ t t b r1 , t m p1 , t m p2
adrp \ t m p1 , e m p t y _ z e r o _ p a g e
2018-01-29 11:59:57 +00:00
phys_ t o _ t t b r \ t m p2 , \ t m p1
2019-08-07 16:55:19 +01:00
offset_ t t b r1 \ t m p2 , \ t m p1
2018-02-06 22:22:50 +00:00
msr t t b r1 _ e l 1 , \ t m p2
isb
tlbi v m a l l e 1
dsb n s h
isb
.endm
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
/ *
2018-07-31 14:08:56 +01:00
* void i d m a p _ c p u _ r e p l a c e _ t t b r1 ( p h y s _ a d d r _ t t t b r1 )
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
*
* This i s t h e l o w - l e v e l c o u n t e r p a r t t o c p u _ r e p l a c e _ t t b r1 , a n d s h o u l d n o t b e
* called b y a n y t h i n g e l s e . I t c a n o n l y b e e x e c u t e d f r o m a T T B R 0 m a p p i n g .
* /
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ S T A R T ( i d m a p _ c p u _ r e p l a c e _ t t b r1 )
2017-11-02 12:12:34 +00:00
save_ a n d _ d i s a b l e _ d a i f f l a g s =x2
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
2018-02-06 22:22:50 +00:00
_ _ idmap_ c p u _ s e t _ r e s e r v e d _ t t b r1 x1 , x3
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
2019-08-07 16:55:19 +01:00
offset_ t t b r1 x0 , x3
2018-07-31 14:08:56 +01:00
msr t t b r1 _ e l 1 , x0
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
isb
2017-11-02 12:12:34 +00:00
restore_ d a i f x2
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
ret
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ E N D ( i d m a p _ c p u _ r e p l a c e _ t t b r1 )
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
.popsection
2018-02-06 22:22:50 +00:00
# ifdef C O N F I G _ U N M A P _ K E R N E L _ A T _ E L 0
2018-01-29 12:00:00 +00:00
.pushsection " .idmap .text " , " awx"
2018-02-06 22:22:50 +00:00
.macro _ _ idmap_ k p t i _ g e t _ p g t a b l e _ e n t , t y p e
dc c v a c , c u r _ \ ( ) \ t y p e \ ( ) p / / E n s u r e a n y e x i s t i n g d i r t y
dmb s y / / l i n e s a r e w r i t t e n b a c k b e f o r e
ldr \ t y p e , [ c u r _ \ ( ) \ t y p e \ ( ) p ] / / l o a d i n g t h e e n t r y
2018-02-13 13:14:09 +00:00
tbz \ t y p e , #0 , s k i p _ \ ( ) \ t y p e / / S k i p i n v a l i d a n d
tbnz \ t y p e , #11 , s k i p _ \ ( ) \ t y p e / / n o n - g l o b a l e n t r i e s
2018-02-06 22:22:50 +00:00
.endm
.macro _ _ idmap_ k p t i _ p u t _ p g t a b l e _ e n t _ n g , t y p e
orr \ t y p e , \ t y p e , #P T E _ N G / / S a m e b i t f o r b l o c k s a n d p a g e s
2018-06-22 16:23:45 +01:00
str \ t y p e , [ c u r _ \ ( ) \ t y p e \ ( ) p ] / / U p d a t e t h e e n t r y a n d e n s u r e
dmb s y / / t h a t i t i s v i s i b l e t o a l l
dc c i v a c , c u r _ \ ( ) \ t y p e \ ( ) p / / C P U s .
2018-02-06 22:22:50 +00:00
.endm
/ *
* void _ _ k p t i _ i n s t a l l _ n g _ m a p p i n g s ( i n t c p u , i n t n u m _ c p u s , p h y s _ a d d r _ t s w a p p e r )
*
* Called e x a c t l y o n c e f r o m s t o p _ m a c h i n e c o n t e x t b y e a c h C P U f o u n d d u r i n g b o o t .
* /
__idmap_kpti_flag :
.long 1
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ S T A R T ( i d m a p _ k p t i _ i n s t a l l _ n g _ m a p p i n g s )
2018-02-06 22:22:50 +00:00
cpu . r e q w0
num_ c p u s . r e q w1
swapper_ p a . r e q x2
swapper_ t t b . r e q x3
flag_ p t r . r e q x4
cur_ p g d p . r e q x5
end_ p g d p . r e q x6
pgd . r e q x7
cur_ p u d p . r e q x8
end_ p u d p . r e q x9
pud . r e q x10
cur_ p m d p . r e q x11
end_ p m d p . r e q x12
pmd . r e q x13
cur_ p t e p . r e q x14
end_ p t e p . r e q x15
pte . r e q x16
mrs s w a p p e r _ t t b , t t b r1 _ e l 1
arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 22:50:39 +00:00
restore_ t t b r1 s w a p p e r _ t t b
2018-02-06 22:22:50 +00:00
adr f l a g _ p t r , _ _ i d m a p _ k p t i _ f l a g
cbnz c p u , _ _ i d m a p _ k p t i _ s e c o n d a r y
/* We're the boot CPU. Wait for the others to catch up */
sevl
1 : wfe
2019-12-06 14:13:37 -08:00
ldaxr w17 , [ f l a g _ p t r ]
eor w17 , w17 , n u m _ c p u s
cbnz w17 , 1 b
2018-02-06 22:22:50 +00:00
/* We need to walk swapper, so turn off the MMU. */
pre_ d i s a b l e _ m m u _ w o r k a r o u n d
2019-12-06 14:13:37 -08:00
mrs x17 , s c t l r _ e l 1
bic x17 , x17 , #S C T L R _ E L x _ M
msr s c t l r _ e l 1 , x17
2018-02-06 22:22:50 +00:00
isb
/* Everybody is enjoying the idmap, so we can rewrite swapper. */
/* PGD */
mov c u r _ p g d p , s w a p p e r _ p a
add e n d _ p g d p , c u r _ p g d p , #( P T R S _ P E R _ P G D * 8 )
do_pgd : _ _ idmap_ k p t i _ g e t _ p g t a b l e _ e n t p g d
tbnz p g d , #1 , w a l k _ p u d s
next_pgd :
2018-02-13 13:14:09 +00:00
_ _ idmap_ k p t i _ p u t _ p g t a b l e _ e n t _ n g p g d
skip_pgd :
2018-02-06 22:22:50 +00:00
add c u r _ p g d p , c u r _ p g d p , #8
cmp c u r _ p g d p , e n d _ p g d p
b. n e d o _ p g d
/* Publish the updated tables and nuke all the TLBs */
dsb s y
tlbi v m a l l e 1 i s
dsb i s h
isb
/* We're done: fire up the MMU again */
2019-12-06 14:13:37 -08:00
mrs x17 , s c t l r _ e l 1
orr x17 , x17 , #S C T L R _ E L x _ M
msr s c t l r _ e l 1 , x17
2018-02-06 22:22:50 +00:00
isb
2019-08-27 18:12:57 +01:00
/ *
* Invalidate t h e l o c a l I - c a c h e s o t h a t a n y i n s t r u c t i o n s f e t c h e d
* speculatively f r o m t h e P o C a r e d i s c a r d e d , s i n c e t h e y m a y h a v e
* been d y n a m i c a l l y p a t c h e d a t t h e P o U .
* /
ic i a l l u
dsb n s h
isb
2018-02-06 22:22:50 +00:00
/* Set the flag to zero to indicate that we're all done */
str w z r , [ f l a g _ p t r ]
ret
/* PUD */
walk_puds :
.if CONFIG_PGTABLE_LEVELS > 3
pte_ t o _ p h y s c u r _ p u d p , p g d
add e n d _ p u d p , c u r _ p u d p , #( P T R S _ P E R _ P U D * 8 )
do_pud : _ _ idmap_ k p t i _ g e t _ p g t a b l e _ e n t p u d
tbnz p u d , #1 , w a l k _ p m d s
next_pud :
2018-02-13 13:14:09 +00:00
_ _ idmap_ k p t i _ p u t _ p g t a b l e _ e n t _ n g p u d
skip_pud :
2018-02-06 22:22:50 +00:00
add c u r _ p u d p , c u r _ p u d p , 8
cmp c u r _ p u d p , e n d _ p u d p
b. n e d o _ p u d
b n e x t _ p g d
.else /* CONFIG_PGTABLE_LEVELS <= 3 */
mov p u d , p g d
b w a l k _ p m d s
next_pud :
b n e x t _ p g d
.endif
/* PMD */
walk_pmds :
.if CONFIG_PGTABLE_LEVELS > 2
pte_ t o _ p h y s c u r _ p m d p , p u d
add e n d _ p m d p , c u r _ p m d p , #( P T R S _ P E R _ P M D * 8 )
do_pmd : _ _ idmap_ k p t i _ g e t _ p g t a b l e _ e n t p m d
tbnz p m d , #1 , w a l k _ p t e s
next_pmd :
2018-02-13 13:14:09 +00:00
_ _ idmap_ k p t i _ p u t _ p g t a b l e _ e n t _ n g p m d
skip_pmd :
2018-02-06 22:22:50 +00:00
add c u r _ p m d p , c u r _ p m d p , #8
cmp c u r _ p m d p , e n d _ p m d p
b. n e d o _ p m d
b n e x t _ p u d
.else /* CONFIG_PGTABLE_LEVELS <= 2 */
mov p m d , p u d
b w a l k _ p t e s
next_pmd :
b n e x t _ p u d
.endif
/* PTE */
walk_ptes :
pte_ t o _ p h y s c u r _ p t e p , p m d
add e n d _ p t e p , c u r _ p t e p , #( P T R S _ P E R _ P T E * 8 )
do_pte : _ _ idmap_ k p t i _ g e t _ p g t a b l e _ e n t p t e
_ _ idmap_ k p t i _ p u t _ p g t a b l e _ e n t _ n g p t e
2018-02-13 13:14:09 +00:00
skip_pte :
2018-02-06 22:22:50 +00:00
add c u r _ p t e p , c u r _ p t e p , #8
cmp c u r _ p t e p , e n d _ p t e p
b. n e d o _ p t e
b n e x t _ p m d
2019-12-06 14:13:37 -08:00
.unreq cpu
.unreq num_cpus
.unreq swapper_pa
.unreq cur_pgdp
.unreq end_pgdp
.unreq pgd
.unreq cur_pudp
.unreq end_pudp
.unreq pud
.unreq cur_pmdp
.unreq end_pmdp
.unreq pmd
.unreq cur_ptep
.unreq end_ptep
.unreq pte
2018-02-06 22:22:50 +00:00
/* Secondary CPUs end up here */
__idmap_kpti_secondary :
/* Uninstall swapper before surgery begins */
2019-12-06 14:13:37 -08:00
_ _ idmap_ c p u _ s e t _ r e s e r v e d _ t t b r1 x16 , x17
2018-02-06 22:22:50 +00:00
/* Increment the flag to let the boot CPU we're ready */
2019-12-06 14:13:37 -08:00
1 : ldxr w16 , [ f l a g _ p t r ]
add w16 , w16 , #1
stxr w17 , w16 , [ f l a g _ p t r ]
2018-02-06 22:22:50 +00:00
cbnz w17 , 1 b
/* Wait for the boot CPU to finish messing around with swapper */
sevl
1 : wfe
2019-12-06 14:13:37 -08:00
ldxr w16 , [ f l a g _ p t r ]
cbnz w16 , 1 b
2018-02-06 22:22:50 +00:00
/* All done, act like nothing happened */
2019-12-06 14:13:37 -08:00
offset_ t t b r1 s w a p p e r _ t t b , x16
2018-02-06 22:22:50 +00:00
msr t t b r1 _ e l 1 , s w a p p e r _ t t b
isb
ret
.unreq swapper_ttb
.unreq flag_ptr
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ E N D ( i d m a p _ k p t i _ i n s t a l l _ n g _ m a p p i n g s )
2018-02-06 22:22:50 +00:00
.popsection
# endif
2012-03-05 11:49:28 +00:00
/ *
* _ _ cpu_ s e t u p
*
* Initialise t h e p r o c e s s o r f o r t u r n i n g t h e M M U o n . R e t u r n i n x0 t h e
* value o f t h e S C T L R _ E L 1 r e g i s t e r .
* /
2018-01-29 12:00:00 +00:00
.pushsection " .idmap .text " , " awx"
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ S T A R T ( _ _ c p u _ s e t u p )
2015-10-06 18:46:22 +01:00
tlbi v m a l l e 1 / / I n v a l i d a t e l o c a l T L B
dsb n s h
2012-03-05 11:49:28 +00:00
mov x0 , #3 < < 2 0
msr c p a c r _ e l 1 , x0 / / E n a b l e F P / A S I M D
2015-08-20 11:47:13 +01:00
mov x0 , #1 < < 1 2 / / R e s e t m d s c r _ e l 1 a n d d i s a b l e
msr m d s c r _ e l 1 , x0 / / a c c e s s t o t h e D C C f r o m E L 0
arm64: debug: unmask PSTATE.D earlier
Clearing PSTATE.D is one of the requirements for generating a debug
exception. The arm64 booting protocol requires that PSTATE.D is set,
since many of the debug registers (for example, the hw_breakpoint
registers) are UNKNOWN out of reset and could potentially generate
spurious, fatal debug exceptions in early boot code if PSTATE.D was
clear. Once the debug registers have been safely initialised, PSTATE.D
is cleared, however this is currently broken for two reasons:
(1) The boot CPU clears PSTATE.D in a postcore_initcall and secondary
CPUs clear PSTATE.D in secondary_start_kernel. Since the initcall
runs after SMP (and the scheduler) have been initialised, there is
no guarantee that it is actually running on the boot CPU. In this
case, the boot CPU is left with PSTATE.D set and is not capable of
generating debug exceptions.
(2) In a preemptible kernel, we may explicitly schedule on the IRQ
return path to EL1. If an IRQ occurs with PSTATE.D set in the idle
thread, then we may schedule the kthread_init thread, run the
postcore_initcall to clear PSTATE.D and then context switch back
to the idle thread before returning from the IRQ. The exception
return path will then restore PSTATE.D from the stack, and set it
again.
This patch fixes the problem by moving the clearing of PSTATE.D earlier
to proc.S. This has the desirable effect of clearing it in one place for
all CPUs, long before we have to worry about the scheduler or any
exception handling. We ensure that the previous reset of MDSCR_EL1 has
completed before unmasking the exception, so that any spurious
exceptions resulting from UNKNOWN debug registers are not generated.
Without this patch applied, the kprobes selftests have been seen to fail
under KVM, where we end up attempting to step the OOL instruction buffer
with PSTATE.D set and therefore fail to complete the step.
Cc: <stable@vger.kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-07-19 15:07:37 +01:00
isb / / U n m a s k d e b u g e x c e p t i o n s n o w ,
enable_ d b g / / s i n c e t h i s i s p e r - c p u
2016-01-13 14:50:03 +00:00
reset_ p m u s e r e n r _ e l 0 x0 / / D i s a b l e P M U a c c e s s f r o m E L 0
2012-03-05 11:49:28 +00:00
/ *
2019-12-11 18:40:09 +00:00
* Memory r e g i o n a t t r i b u t e s
2012-03-05 11:49:28 +00:00
* /
2019-12-11 18:40:09 +00:00
mov_ q x5 , M A I R _ E L 1 _ S E T
2012-03-05 11:49:28 +00:00
msr m a i r _ e l 1 , x5
/ *
* Prepare S C T L R
* /
2018-01-15 19:38:55 +00:00
mov_ q x0 , S C T L R _ E L 1 _ S E T
2012-03-05 11:49:28 +00:00
/ *
* Set/ p r e p a r e T C R a n d T T B R . W e u s e 5 1 2 G B ( 3 9 - b i t ) a d d r e s s r a n g e f o r
* both u s e r a n d k e r n e l .
* /
2014-04-02 17:55:40 +01:00
ldr x10 , =TCR_TxSZ ( V A _ B I T S ) | T C R _ C A C H E _ F L A G S | T C R _ S M P _ F L A G S | \
2018-02-27 14:15:49 +00:00
TCR_ T G _ F L A G S | T C R _ K A S L R _ F L A G S | T C R _ A S I D 1 6 | \
2018-12-28 00:30:31 -08:00
TCR_ T B I 0 | T C R _ A 1 | T C R _ K A S A N _ F L A G S
2019-02-26 18:43:41 +00:00
tcr_ c l e a r _ e r r a t a _ b i t s x10 , x9 , x5
2018-12-06 22:50:41 +00:00
2019-08-07 16:55:22 +01:00
# ifdef C O N F I G _ A R M 6 4 _ V A _ B I T S _ 5 2
2019-08-07 16:55:23 +01:00
ldr_ l x9 , v a b i t s _ a c t u a l
2018-12-06 22:50:41 +00:00
sub x9 , x z r , x9
add x9 , x9 , #64
2019-08-07 16:55:22 +01:00
tcr_ s e t _ t 1 s z x10 , x9
2018-12-06 22:50:41 +00:00
# else
ldr_ l x9 , i d m a p _ t 0 s z
# endif
tcr_ s e t _ t 0 s z x10 , x9
arm64: mm: increase VA range of identity map
The page size and the number of translation levels, and hence the supported
virtual address range, are build-time configurables on arm64 whose optimal
values are use case dependent. However, in the current implementation, if
the system's RAM is located at a very high offset, the virtual address range
needs to reflect that merely because the identity mapping, which is only used
to enable or disable the MMU, requires the extended virtual range to map the
physical memory at an equal virtual offset.
This patch relaxes that requirement, by increasing the number of translation
levels for the identity mapping only, and only when actually needed, i.e.,
when system RAM's offset is found to be out of reach at runtime.
Tested-by: Laura Abbott <lauraa@codeaurora.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2015-03-19 16:42:27 +00:00
2014-03-07 08:49:25 +00:00
/ *
2017-12-13 17:07:17 +00:00
* Set t h e I P S b i t s i n T C R _ E L 1 .
2014-03-07 08:49:25 +00:00
* /
2017-12-13 17:07:17 +00:00
tcr_ c o m p u t e _ p a _ s i z e x10 , #T C R _ I P S _ S H I F T , x 5 , x6
2015-07-10 17:24:28 +01:00
# ifdef C O N F I G _ A R M 6 4 _ H W _ A F D B M
/ *
2018-03-26 15:12:48 +01:00
* Enable h a r d w a r e u p d a t e o f t h e A c c e s s F l a g s b i t .
* Hardware d i r t y b i t m a n a g e m e n t i s e n a b l e d l a t e r ,
* via c a p a b i l i t i e s .
2015-07-10 17:24:28 +01:00
* /
mrs x9 , I D _ A A 6 4 M M F R 1 _ E L 1
and x9 , x9 , #0xf
2018-03-26 15:12:48 +01:00
cbz x9 , 1 f
orr x10 , x10 , #T C R _ H A / / h a r d w a r e A c c e s s f l a g u p d a t e
1 :
2015-07-10 17:24:28 +01:00
# endif / * C O N F I G _ A R M 6 4 _ H W _ A F D B M * /
2012-03-05 11:49:28 +00:00
msr t c r _ e l 1 , x10
ret / / r e t u r n t o h e a d . S
2020-01-06 19:58:18 +00:00
SYM_ F U N C _ E N D ( _ _ c p u _ s e t u p )
