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/*
* Device Tree file for Marvell Armada XP evaluation board
* (DB-78460-BP)
*
* Copyright (C) 2012 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
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/include/ "armada-xp-mv78460.dtsi"
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/ {
model = "Marvell Armada XP Evaluation Board";
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compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
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reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
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};
soc {
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internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
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};
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serial@12100 {
clock-frequency = <250000000>;
status = "okay";
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};
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serial@12200 {
clock-frequency = <250000000>;
status = "okay";
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};
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serial@12300 {
clock-frequency = <250000000>;
status = "okay";
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};
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sata@a0000 {
nr-ports = <2>;
status = "okay";
};
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mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
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phy1: ethernet-phy@1 {
reg = <1>;
};
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phy2: ethernet-phy@2 {
reg = <25>;
};
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phy3: ethernet-phy@3 {
reg = <27>;
};
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};
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ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
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mvsdio@d4000 {
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
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status = "okay";
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/* No CD or WP GPIOs */
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broken-cd;
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};
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usb@50000 {
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status = "okay";
};
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usb@51000 {
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status = "okay";
};
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usb@52000 {
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status = "okay";
};
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spi0: spi@10600 {
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status = "okay";
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spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
};
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};
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pcie-controller {
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status = "okay";
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/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
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};
};
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};
};