2005-10-10 22:36:14 +10:00
/ *
* PowerPC v e r s i o n
* Copyright ( C ) 1 9 9 5 - 1 9 9 6 G a r y T h o m a s ( g d t @linuxppc.org)
* Rewritten b y C o r t D o u g a n ( c o r t @cs.nmt.edu) for PReP
* Copyright ( C ) 1 9 9 6 C o r t D o u g a n < c o r t @cs.nmt.edu>
* Adapted f o r P o w e r M a c i n t o s h b y P a u l M a c k e r r a s .
* Low- l e v e l e x c e p t i o n h a n d l e r s a n d M M U s u p p o r t
* rewritten b y P a u l M a c k e r r a s .
* Copyright ( C ) 1 9 9 6 P a u l M a c k e r r a s .
* MPC8 x x m o d i f i c a t i o n s C o p y r i g h t ( C ) 1 9 9 7 D a n M a l e k ( d m a l e k @jlc.net).
*
* This f i l e c o n t a i n s t h e s y s t e m c a l l e n t r y c o d e , c o n t e x t s w i t c h
* code, a n d e x c e p t i o n / i n t e r r u p t r e t u r n c o d e f o r P o w e r P C .
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* as p u b l i s h e d b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version
* 2 of t h e L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
* /
# include < l i n u x / e r r n o . h >
powerpc/kernel: Switch to using MAX_ERRNO
Currently on powerpc we have our own #define for the highest (negative)
errno value, called _LAST_ERRNO. This is defined to be 516, for reasons
which are not clear.
The generic code, and x86, use MAX_ERRNO, which is defined to be 4095.
In particular seccomp uses MAX_ERRNO to restrict the value that a
seccomp filter can return.
Currently with the mismatch between _LAST_ERRNO and MAX_ERRNO, a seccomp
tracer wanting to return 600, expecting it to be seen as an error, would
instead find on powerpc that userspace sees a successful syscall with a
return value of 600.
To avoid this inconsistency, switch powerpc to use MAX_ERRNO.
We are somewhat confident that generic syscalls that can return a
non-error value above negative MAX_ERRNO have already been updated to
use force_successful_syscall_return().
I have also checked all the powerpc specific syscalls, and believe that
none of them expect to return a non-error value between -MAX_ERRNO and
-516. So this change should be safe ...
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Kees Cook <keescook@chromium.org>
2015-07-23 20:21:01 +10:00
# include < l i n u x / e r r . h >
2005-10-10 22:36:14 +10:00
# include < a s m / u n i s t d . h >
# include < a s m / p r o c e s s o r . h >
# include < a s m / p a g e . h >
# include < a s m / m m u . h >
# include < a s m / t h r e a d _ i n f o . h >
2018-07-24 01:07:54 +10:00
# include < a s m / c o d e - p a t c h i n g - a s m . h >
2005-10-10 22:36:14 +10:00
# include < a s m / p p c _ a s m . h >
# include < a s m / a s m - o f f s e t s . h >
# include < a s m / c p u t a b l e . h >
2006-09-25 18:19:00 +10:00
# include < a s m / f i r m w a r e . h >
2007-01-01 18:45:34 +00:00
# include < a s m / b u g . h >
2008-04-17 14:34:59 +10:00
# include < a s m / p t r a c e . h >
2008-04-17 14:35:01 +10:00
# include < a s m / i r q f l a g s . h >
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
# include < a s m / h w _ i r q . h >
2013-05-13 16:16:43 +00:00
# include < a s m / c o n t e x t _ t r a c k i n g . h >
2015-06-12 11:06:32 +10:00
# include < a s m / t m . h >
2016-04-26 10:28:50 +10:00
# include < a s m / p p c - o p c o d e . h >
2018-04-24 14:15:59 +10:00
# include < a s m / b a r r i e r . h >
2016-01-13 23:33:46 -05:00
# include < a s m / e x p o r t . h >
2018-07-05 16:24:57 +00:00
# include < a s m / a s m - c o m p a t . h >
2018-01-10 03:07:15 +11:00
# ifdef C O N F I G _ P P C _ B O O K 3 S
# include < a s m / e x c e p t i o n - 6 4 s . h >
# else
# include < a s m / e x c e p t i o n - 6 4 e . h >
# endif
2018-07-05 16:25:01 +00:00
# include < a s m / f e a t u r e - f i x u p s . h >
2005-10-10 22:36:14 +10:00
/ *
* System c a l l s .
* /
.section " .toc " , " aw"
2014-02-04 16:05:53 +11:00
SYS_CALL_TABLE :
.tc _ c a l l _ t a b l e [ T C ] ,s y s _ c a l l _ t a b l e
2005-10-10 22:36:14 +10:00
2018-12-17 16:10:35 +05:30
COMPAT_SYS_CALL_TABLE :
.tc _ s y s _ c a l l _ t a b l e [ T C ] ,c o m p a t _ s y s _ c a l l _ t a b l e
2005-10-10 22:36:14 +10:00
/* This value is used to mark exception frames on the stack. */
exception_marker :
2008-04-17 14:34:59 +10:00
.tc _ E X C _ M A R K E R [ T C ] ,S T A C K _ F R A M E _ R E G S _ M A R K E R
2005-10-10 22:36:14 +10:00
.section " .text "
.align 7
.globl system_call_common
system_call_common :
2015-06-12 11:06:32 +10:00
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
BEGIN_ F T R _ S E C T I O N
extrdi. r10 , r12 , 1 , ( 6 3 - M S R _ T S _ T _ L G ) / * t r a n s a c t i o n a c t i v e ? * /
2017-06-29 23:19:16 +05:30
bne . L t a b o r t _ s y s c a l l
2015-06-12 11:06:32 +10:00
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ T M )
# endif
2005-10-10 22:36:14 +10:00
andi. r10 ,r12 ,M S R _ P R
mr r10 ,r1
addi r1 ,r1 ,- I N T _ F R A M E _ S I Z E
beq- 1 f
ld r1 ,P A C A K S A V E ( r13 )
1 : std r10 ,0 ( r1 )
std r11 ,_ N I P ( r1 )
std r12 ,_ M S R ( r1 )
std r0 ,G P R 0 ( r1 )
std r10 ,G P R 1 ( r1 )
2012-12-06 21:46:37 +00:00
beq 2 f / * i f f r o m k e r n e l m o d e * /
2018-12-12 16:03:05 +02:00
# ifdef C O N F I G _ P P C _ F S L _ B O O K 3 E
START_ B T B _ F L U S H _ S E C T I O N
BTB_ F L U S H ( r10 )
END_ B T B _ F L U S H _ S E C T I O N
# endif
2016-05-17 08:33:46 +02:00
ACCOUNT_ C P U _ U S E R _ E N T R Y ( r13 , r10 , r11 )
2012-12-06 21:46:37 +00:00
2 : std r2 ,G P R 2 ( r1 )
2005-10-10 22:36:14 +10:00
std r3 ,G P R 3 ( r1 )
2012-04-05 03:44:48 +00:00
mfcr r2
2005-10-10 22:36:14 +10:00
std r4 ,G P R 4 ( r1 )
std r5 ,G P R 5 ( r1 )
std r6 ,G P R 6 ( r1 )
std r7 ,G P R 7 ( r1 )
std r8 ,G P R 8 ( r1 )
li r11 ,0
std r11 ,G P R 9 ( r1 )
std r11 ,G P R 1 0 ( r1 )
std r11 ,G P R 1 1 ( r1 )
std r11 ,G P R 1 2 ( r1 )
2012-04-04 18:24:29 +00:00
std r11 ,_ X E R ( r1 )
2012-04-04 18:26:39 +00:00
std r11 ,_ C T R ( r1 )
2005-10-10 22:36:14 +10:00
std r9 ,G P R 1 3 ( r1 )
mflr r10
2012-04-05 03:44:48 +00:00
/ *
* This c l e a r s C R 0 . S O ( b i t 2 8 ) , w h i c h i s t h e e r r o r i n d i c a t i o n o n
* return f r o m t h i s s y s t e m c a l l .
* /
rldimi r2 ,r11 ,2 8 ,( 6 3 - 2 8 )
2005-10-10 22:36:14 +10:00
li r11 ,0 x c01
std r10 ,_ L I N K ( r1 )
std r11 ,_ T R A P ( r1 )
std r3 ,O R I G _ G P R 3 ( r1 )
2012-04-05 03:44:48 +00:00
std r2 ,_ C C R ( r1 )
2005-10-10 22:36:14 +10:00
ld r2 ,P A C A T O C ( r13 )
addi r9 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
ld r11 ,e x c e p t i o n _ m a r k e r @toc(r2)
std r11 ,- 1 6 ( r9 ) / * " r e g s h e r e " m a r k e r * /
2012-07-25 07:56:04 +02:00
# if d e f i n e d ( C O N F I G _ V I R T _ C P U _ A C C O U N T I N G _ N A T I V E ) & & d e f i n e d ( C O N F I G _ P P C _ S P L P A R )
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
BEGIN_ F W _ F T R _ S E C T I O N
beq 3 3 f
/* if from user, see if there are any DTL entries to process */
ld r10 ,P A C A L P P A C A P T R ( r13 ) / * g e t p t r t o V P A * /
ld r11 ,P A C A _ D T L _ R I D X ( r13 ) / * g e t l o g r e a d i n d e x * /
2013-08-07 02:01:46 +10:00
addi r10 ,r10 ,L P P A C A _ D T L I D X
LDX_ B E r10 ,0 ,r10 / * g e t l o g w r i t e i n d e x * /
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
cmpd c r1 ,r11 ,r10
beq+ c r1 ,3 3 f
2014-02-04 16:04:35 +11:00
bl a c c u m u l a t e _ s t o l e n _ t i m e
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
REST_ G P R ( 0 ,r1 )
REST_ 4 G P R S ( 3 ,r1 )
REST_ 2 G P R S ( 7 ,r1 )
addi r9 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
33 :
END_ F W _ F T R _ S E C T I O N _ I F S E T ( F W _ F E A T U R E _ S P L P A R )
2012-07-25 07:56:04 +02:00
# endif / * C O N F I G _ V I R T _ C P U _ A C C O U N T I N G _ N A T I V E & & C O N F I G _ P P C _ S P L P A R * /
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
2012-03-01 15:40:23 +11:00
/ *
* A s y s c a l l s h o u l d a l w a y s b e c a l l e d w i t h i n t e r r u p t s e n a b l e d
* so w e j u s t u n c o n d i t i o n a l l y h a r d - e n a b l e h e r e . W h e n s o m e k i n d
* of i r q t r a c i n g i s u s e d , w e a d d i t i o n a l l y c h e c k t h a t c o n d i t i o n
* is c o r r e c t
* /
2017-12-20 09:25:54 +05:30
# if d e f i n e d ( C O N F I G _ P P C _ I R Q _ S O F T _ M A S K _ D E B U G ) & & d e f i n e d ( C O N F I G _ B U G )
2017-12-20 09:25:50 +05:30
lbz r10 ,P A C A I R Q S O F T M A S K ( r13 )
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
1 : tdnei r10 ,I R Q S _ E N A B L E D
2012-03-01 15:40:23 +11:00
EMIT_ B U G _ E N T R Y 1 b ,_ _ F I L E _ _ ,_ _ L I N E _ _ ,B U G F L A G _ W A R N I N G
# endif
2009-07-23 23:15:59 +00:00
# ifdef C O N F I G _ P P C _ B O O K 3 E
wrteei 1
# else
2016-09-15 19:04:46 +10:00
li r11 ,M S R _ R I
2005-10-10 22:36:14 +10:00
ori r11 ,r11 ,M S R _ E E
mtmsrd r11 ,1
2009-07-23 23:15:59 +00:00
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
2005-10-10 22:36:14 +10:00
2017-06-29 23:19:17 +05:30
system_call : /* label this so stack traces look sane */
2012-03-01 15:40:23 +11:00
/ * We d o n e e d t o s e t S O F T E i n t h e s t a c k f r a m e o r t h e r e t u r n
* from i n t e r r u p t w i l l b e p a i n f u l
* /
2017-12-20 09:25:42 +05:30
li r10 ,I R Q S _ E N A B L E D
2012-03-01 15:40:23 +11:00
std r10 ,S O F T E ( r1 )
2019-01-12 09:55:50 +00:00
ld r11 , P A C A _ T H R E A D _ I N F O ( r13 )
2005-10-10 22:36:14 +10:00
ld r10 ,T I _ F L A G S ( r11 )
2015-01-15 12:01:42 +11:00
andi. r11 ,r10 ,_ T I F _ S Y S C A L L _ D O T R A C E
2017-06-29 23:19:16 +05:30
bne . L s y s c a l l _ d o t r a c e / * d o e s n o t r e t u r n * /
2005-10-10 22:36:14 +10:00
cmpldi 0 ,r0 ,N R _ s y s c a l l s
2017-06-29 23:19:16 +05:30
bge- . L s y s c a l l _ e n o s y s
2005-10-10 22:36:14 +10:00
2017-06-29 23:19:17 +05:30
.Lsyscall :
2005-10-10 22:36:14 +10:00
/ *
* Need t o v e c t o r t o 3 2 B i t o r d e f a u l t s y s _ c a l l _ t a b l e h e r e ,
* based o n c a l l e r ' s r u n - m o d e / p e r s o n a l i t y .
* /
2014-02-04 16:05:53 +11:00
ld r11 ,S Y S _ C A L L _ T A B L E @toc(2)
powerpc: Redefine TIF_32BITS thread flag
Moving TIF_32BIT to use bit 20 instead of 4 in the task flag field.
This change is making room for an upcoming new task macro
(_TIF_SYSCALL_EMU) which is preferred to set a bit in the lower 16-bits
part of the word.
This upcoming flag macro will take part in a composed macro
(_TIF_SYSCALL_DOTRACE) which will contain other flags as well, and it is
preferred that the whole _TIF_SYSCALL_DOTRACE macro only sets the lower 16
bits of a word, so, it could be handled using immediate operations (as load
immediate, add immediate, ...) where the immediate operand (SI) is limited
to 16-bits.
Another possible solution would be using the LOAD_REG_IMMEDIATE() macro
to load a full 64-bits word immediate, but it takes 5 operations instead of
one.
Having TIF_32BITS being redefined to use an upper bit is not a problem
since there is only one place in the assembly code where TIF_32BIT is being
used, and it could be replaced with an operation with right shift (addis),
since it is used alone, i.e. not being part of a composed macro, which has
different bits set, and would require LOAD_REG_IMMEDIATE().
Tested on a 64 bits Big Endian machine running a 32 bits task.
Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-09-20 13:45:05 -03:00
andis. r10 ,r10 ,_ T I F _ 3 2 B I T @h
2005-10-10 22:36:14 +10:00
beq 1 5 f
2018-12-17 16:10:35 +05:30
ld r11 ,C O M P A T _ S Y S _ C A L L _ T A B L E @toc(2)
2005-10-10 22:36:14 +10:00
clrldi r3 ,r3 ,3 2
clrldi r4 ,r4 ,3 2
clrldi r5 ,r5 ,3 2
clrldi r6 ,r6 ,3 2
clrldi r7 ,r7 ,3 2
clrldi r8 ,r8 ,3 2
15 :
2018-12-17 16:10:35 +05:30
slwi r0 ,r0 ,3
2018-04-24 14:15:59 +10:00
barrier_ n o s p e c _ a s m
/ *
* Prevent t h e l o a d o f t h e h a n d l e r b e l o w ( b a s e d o n t h e u s e r - p a s s e d
* system c a l l n u m b e r ) b e i n g s p e c u l a t i v e l y e x e c u t e d u n t i l t h e t e s t
* against N R _ s y s c a l l s a n d b r a n c h t o . L s y s c a l l _ e n o s y s a b o v e h a s
* committed.
* /
2014-02-04 16:07:47 +11:00
ldx r12 ,r11 ,r0 / * F e t c h s y s t e m c a l l h a n d l e r [ p t r ] * /
mtctr r12
2005-10-10 22:36:14 +10:00
bctrl / * C a l l h a n d l e r * /
2014-12-05 21:16:59 +11:00
.Lsyscall_exit :
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
std r3 ,R E S U L T ( r1 )
2018-06-02 08:44:01 -04:00
# ifdef C O N F I G _ D E B U G _ R S E Q
/* Check whether the syscall is issued inside a restartable sequence */
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl r s e q _ s y s c a l l
ld r3 ,R E S U L T ( r1 )
# endif
2019-01-12 09:55:50 +00:00
ld r12 , P A C A _ T H R E A D _ I N F O ( r13 )
2005-10-10 22:36:14 +10:00
ld r8 ,_ M S R ( r1 )
2009-07-23 23:15:59 +00:00
# ifdef C O N F I G _ P P C _ B O O K 3 S
/* No MSR:RI on BookE */
2005-10-10 22:36:14 +10:00
andi. r10 ,r8 ,M S R _ R I
2017-06-29 23:19:19 +05:30
beq- . L u n r e c o v _ r e s t o r e
2009-07-23 23:15:59 +00:00
# endif
2017-06-29 23:19:18 +05:30
/ *
* This i s a f e w i n s t r u c t i o n s i n t o t h e a c t u a l s y s c a l l e x i t p a t h ( w h i c h a c t u a l l y
* starts a t . L s y s c a l l _ e x i t ) t o c a t e r t o k p r o b e b l a c k l i s t i n g a n d t o r e d u c e t h e
* number o f v i s i b l e s y m b o l s f o r p r o f i l i n g p u r p o s e s .
*
* We c a n p r o b e f r o m s y s t e m _ c a l l u n t i l t h i s p o i n t a s M S R _ R I i s s e t . B u t o n c e i t
* is c l e a r e d b e l o w , w e w o n ' t b e a b l e t o t a k e a t r a p .
*
* This i s b l a c k l i s t e d f r o m k p r o b e s f u r t h e r b e l o w w i t h _ A S M _ N O K P R O B E _ S Y M B O L ( ) .
* /
system_call_exit :
2012-03-01 15:40:23 +11:00
/ *
* Disable i n t e r r u p t s s o c u r r e n t _ t h r e a d _ i n f o ( ) - > f l a g s c a n ' t c h a n g e ,
2009-07-23 23:15:59 +00:00
* and s o t h a t w e d o n ' t g e t i n t e r r u p t e d a f t e r l o a d i n g S R R 0 / 1 .
2018-11-29 17:42:24 +11:00
*
* Leave M S R _ R I e n a b l e d f o r n o w , b e c a u s e w i t h T H R E A D _ I N F O _ I N _ T A S K w e
* could f a u l t o n t h e l o a d o f t h e T I _ F L A G S b e l o w .
2009-07-23 23:15:59 +00:00
* /
# ifdef C O N F I G _ P P C _ B O O K 3 E
wrteei 0
# else
2018-11-29 17:42:24 +11:00
li r11 ,M S R _ R I
2012-05-29 12:22:00 +00:00
mtmsrd r11 ,1
2009-07-23 23:15:59 +00:00
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
2005-10-10 22:36:14 +10:00
ld r9 ,T I _ F L A G S ( r12 )
powerpc/kernel: Switch to using MAX_ERRNO
Currently on powerpc we have our own #define for the highest (negative)
errno value, called _LAST_ERRNO. This is defined to be 516, for reasons
which are not clear.
The generic code, and x86, use MAX_ERRNO, which is defined to be 4095.
In particular seccomp uses MAX_ERRNO to restrict the value that a
seccomp filter can return.
Currently with the mismatch between _LAST_ERRNO and MAX_ERRNO, a seccomp
tracer wanting to return 600, expecting it to be seen as an error, would
instead find on powerpc that userspace sees a successful syscall with a
return value of 600.
To avoid this inconsistency, switch powerpc to use MAX_ERRNO.
We are somewhat confident that generic syscalls that can return a
non-error value above negative MAX_ERRNO have already been updated to
use force_successful_syscall_return().
I have also checked all the powerpc specific syscalls, and believe that
none of them expect to return a non-error value between -MAX_ERRNO and
-516. So this change should be safe ...
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Kees Cook <keescook@chromium.org>
2015-07-23 20:21:01 +10:00
li r11 ,- M A X _ E R R N O
2015-01-15 12:01:42 +11:00
andi. r0 ,r9 ,( _ T I F _ S Y S C A L L _ D O T R A C E | _ T I F _ S I N G L E S T E P | _ T I F _ U S E R _ W O R K _ M A S K | _ T I F _ P E R S Y S C A L L _ M A S K )
2017-06-29 23:19:16 +05:30
bne- . L s y s c a l l _ e x i t _ w o r k
2016-02-29 17:53:47 +11:00
2017-08-07 21:25:01 +10:00
andi. r0 ,r8 ,M S R _ F P
beq 2 f
2016-02-29 17:53:47 +11:00
# ifdef C O N F I G _ A L T I V E C
2017-08-07 21:25:01 +10:00
andis. r0 ,r8 ,M S R _ V E C @h
bne 3 f
2016-02-29 17:53:47 +11:00
# endif
2017-08-07 21:25:01 +10:00
2 : addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl r e s t o r e _ m a t h
ld r8 ,_ M S R ( r1 )
ld r3 ,R E S U L T ( r1 )
li r11 ,- M A X _ E R R N O
2016-02-29 17:53:47 +11:00
2017-08-07 21:25:01 +10:00
3 : cmpld r3 ,r11
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
ld r5 ,_ C C R ( r1 )
2017-06-29 23:19:16 +05:30
bge- . L s y s c a l l _ e r r o r
2012-04-04 18:23:27 +00:00
.Lsyscall_error_cont :
2005-10-10 22:36:14 +10:00
ld r7 ,_ N I P ( r1 )
2010-08-11 01:40:27 +00:00
BEGIN_ F T R _ S E C T I O N
2005-10-10 22:36:14 +10:00
stdcx. r0 ,0 ,r1 / * t o c l e a r t h e r e s e r v a t i o n * /
2010-08-11 01:40:27 +00:00
END_ F T R _ S E C T I O N _ I F C L R ( C P U _ F T R _ S T C X _ C H E C K S _ A D D R E S S )
2005-10-10 22:36:14 +10:00
andi. r6 ,r8 ,M S R _ P R
ld r4 ,_ L I N K ( r1 )
2009-07-23 23:15:59 +00:00
2018-11-29 17:42:24 +11:00
# ifdef C O N F I G _ P P C _ B O O K 3 S
/ *
* Clear M S R _ R I , M S R _ E E i s a l r e a d y a n d r e m a i n s d i s a b l e d . W e c o u l d d o
* this l a t e r , b u t t e s t i n g s h o w s t h a t d o i n g i t h e r e c a u s e s l e s s s l o w
* down t h a n d o i n g i t c l o s e r t o t h e r f i d .
* /
li r11 ,0
mtmsrd r11 ,1
# endif
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-24 10:06:59 +11:00
beq- 1 f
2016-05-17 08:33:46 +02:00
ACCOUNT_ C P U _ U S E R _ E X I T ( r13 , r11 , r12 )
2015-11-25 14:25:17 +11:00
BEGIN_ F T R _ S E C T I O N
HMT_ M E D I U M _ L O W
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ H A S _ P P R )
2018-11-26 18:11:58 -02:00
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
std r8 , P A C A T M S C R A T C H ( r13 )
# endif
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-24 10:06:59 +11:00
ld r13 ,G P R 1 3 ( r1 ) / * o n l y r e s t o r e r13 i f r e t u r n i n g t o u s e r m o d e * /
2018-01-10 03:07:15 +11:00
ld r2 ,G P R 2 ( r1 )
ld r1 ,G P R 1 ( r1 )
mtlr r4
mtcr r5
mtspr S P R N _ S R R 0 ,r7
mtspr S P R N _ S R R 1 ,r8
RFI_ T O _ U S E R
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
/* exit to kernel */
2005-10-10 22:36:14 +10:00
1 : ld r2 ,G P R 2 ( r1 )
ld r1 ,G P R 1 ( r1 )
mtlr r4
mtcr r5
mtspr S P R N _ S R R 0 ,r7
mtspr S P R N _ S R R 1 ,r8
2018-01-10 03:07:15 +11:00
RFI_ T O _ K E R N E L
2005-10-10 22:36:14 +10:00
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
2017-06-29 23:19:16 +05:30
.Lsyscall_error :
2005-10-10 22:36:14 +10:00
oris r5 ,r5 ,0 x10 0 0 / * S e t S O b i t i n C R * /
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
neg r3 ,r3
2005-10-10 22:36:14 +10:00
std r5 ,_ C C R ( r1 )
2012-04-04 18:23:27 +00:00
b . L s y s c a l l _ e r r o r _ c o n t
2017-06-09 01:35:05 +10:00
2005-10-10 22:36:14 +10:00
/* Traced system call support */
2017-06-29 23:19:16 +05:30
.Lsyscall_dotrace :
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
2005-10-10 22:36:14 +10:00
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2014-02-04 16:04:35 +11:00
bl d o _ s y s c a l l _ t r a c e _ e n t e r
2015-07-23 20:21:02 +10:00
2008-07-27 16:51:03 +10:00
/ *
2015-07-23 20:21:02 +10:00
* We u s e t h e r e t u r n v a l u e o f d o _ s y s c a l l _ t r a c e _ e n t e r ( ) a s t h e s y s c a l l
* number. I f t h e s y s c a l l w a s r e j e c t e d f o r a n y r e a s o n d o _ s y s c a l l _ t r a c e _ e n t e r ( )
* returns a n i n v a l i d s y s c a l l n u m b e r a n d t h e t e s t b e l o w a g a i n s t
* NR_ s y s c a l l s w i l l f a i l .
2008-07-27 16:51:03 +10:00
* /
mr r0 ,r3
2015-07-23 20:21:02 +10:00
/* Restore argument registers just clobbered and/or possibly changed. */
2005-10-10 22:36:14 +10:00
ld r3 ,G P R 3 ( r1 )
ld r4 ,G P R 4 ( r1 )
ld r5 ,G P R 5 ( r1 )
ld r6 ,G P R 6 ( r1 )
ld r7 ,G P R 7 ( r1 )
ld r8 ,G P R 8 ( r1 )
2015-07-23 20:21:02 +10:00
2017-06-29 23:19:17 +05:30
/* Repopulate r9 and r10 for the syscall path */
2005-10-10 22:36:14 +10:00
addi r9 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2019-01-12 09:55:50 +00:00
ld r10 , P A C A _ T H R E A D _ I N F O ( r13 )
2005-10-10 22:36:14 +10:00
ld r10 ,T I _ F L A G S ( r10 )
2015-07-23 20:21:02 +10:00
cmpldi r0 ,N R _ s y s c a l l s
2017-06-29 23:19:17 +05:30
blt+ . L s y s c a l l
2015-07-23 20:21:02 +10:00
/* Return code is already in r3 thanks to do_syscall_trace_enter() */
b . L s y s c a l l _ e x i t
2005-10-10 22:36:14 +10:00
2017-06-29 23:19:16 +05:30
.Lsyscall_enosys :
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
li r3 ,- E N O S Y S
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
2017-06-29 23:19:16 +05:30
.Lsyscall_exit_work :
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
/ * If T I F _ R E S T O R E A L L i s s e t , d o n ' t s c r i b b l e o n e i t h e r r3 o r c c r .
If T I F _ N O E R R O R i s s e t , j u s t s a v e r3 a s i t i s . * /
andi. r0 ,r9 ,_ T I F _ R E S T O R E A L L
2006-03-08 13:24:22 +11:00
beq+ 0 f
REST_ N V G P R S ( r1 )
b 2 f
powerpc/kernel: Switch to using MAX_ERRNO
Currently on powerpc we have our own #define for the highest (negative)
errno value, called _LAST_ERRNO. This is defined to be 516, for reasons
which are not clear.
The generic code, and x86, use MAX_ERRNO, which is defined to be 4095.
In particular seccomp uses MAX_ERRNO to restrict the value that a
seccomp filter can return.
Currently with the mismatch between _LAST_ERRNO and MAX_ERRNO, a seccomp
tracer wanting to return 600, expecting it to be seen as an error, would
instead find on powerpc that userspace sees a successful syscall with a
return value of 600.
To avoid this inconsistency, switch powerpc to use MAX_ERRNO.
We are somewhat confident that generic syscalls that can return a
non-error value above negative MAX_ERRNO have already been updated to
use force_successful_syscall_return().
I have also checked all the powerpc specific syscalls, and believe that
none of them expect to return a non-error value between -MAX_ERRNO and
-516. So this change should be safe ...
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Kees Cook <keescook@chromium.org>
2015-07-23 20:21:01 +10:00
0 : cmpld r3 ,r11 / * r11 i s - M A X _ E R R N O * /
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
blt+ 1 f
andi. r0 ,r9 ,_ T I F _ N O E R R O R
bne- 1 f
ld r5 ,_ C C R ( r1 )
neg r3 ,r3
oris r5 ,r5 ,0 x10 0 0 / * S e t S O b i t i n C R * /
std r5 ,_ C C R ( r1 )
1 : std r3 ,G P R 3 ( r1 )
2 : andi. r0 ,r9 ,( _ T I F _ P E R S Y S C A L L _ M A S K )
beq 4 f
2006-03-08 13:24:22 +11:00
/* Clear per-syscall TIF flags if any are set. */
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
li r11 ,_ T I F _ P E R S Y S C A L L _ M A S K
addi r12 ,r12 ,T I _ F L A G S
3 : ldarx r10 ,0 ,r12
andc r10 ,r10 ,r11
stdcx. r10 ,0 ,r12
bne- 3 b
subi r12 ,r12 ,T I _ F L A G S
2006-03-08 13:24:22 +11:00
4 : /* Anything else left to do? */
2015-11-25 14:25:18 +11:00
BEGIN_ F T R _ S E C T I O N
2018-10-13 00:15:16 +11:00
lis r3 ,D E F A U L T _ P P R @highest /* Set default PPR */
2015-11-25 14:25:18 +11:00
sldi r3 ,r3 ,3 2 / * b i t s 1 1 - 1 3 a r e u s e d f o r p p r * /
2018-10-13 00:15:16 +11:00
std r3 ,_ P P R ( r1 )
2015-11-25 14:25:18 +11:00
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ H A S _ P P R )
2015-01-15 12:01:42 +11:00
andi. r0 ,r9 ,( _ T I F _ S Y S C A L L _ D O T R A C E | _ T I F _ S I N G L E S T E P )
2014-02-04 16:04:35 +11:00
beq r e t _ f r o m _ e x c e p t _ l i t e
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
/* Re-enable interrupts */
2009-07-23 23:15:59 +00:00
# ifdef C O N F I G _ P P C _ B O O K 3 E
wrteei 1
# else
2016-09-15 19:04:46 +10:00
li r10 ,M S R _ R I
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
ori r10 ,r10 ,M S R _ E E
mtmsrd r10 ,1
2009-07-23 23:15:59 +00:00
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
2005-10-10 22:36:14 +10:00
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2014-02-04 16:04:35 +11:00
bl d o _ s y s c a l l _ t r a c e _ l e a v e
b r e t _ f r o m _ e x c e p t
2005-10-10 22:36:14 +10:00
2015-06-12 11:06:32 +10:00
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
2017-06-29 23:19:16 +05:30
.Ltabort_syscall :
2015-06-12 11:06:32 +10:00
/* Firstly we need to enable TM in the kernel */
mfmsr r10
2016-07-25 14:26:51 +10:00
li r9 , 1
rldimi r10 , r9 , M S R _ T M _ L G , 6 3 - M S R _ T M _ L G
2015-06-12 11:06:32 +10:00
mtmsrd r10 , 0
/* tabort, this dooms the transaction, nothing else */
2016-07-25 14:26:51 +10:00
li r9 , ( T M _ C A U S E _ S Y S C A L L | T M _ C A U S E _ P E R S I S T E N T )
TABORT( R 9 )
2015-06-12 11:06:32 +10:00
/ *
* Return d i r e c t l y t o u s e r s p a c e . W e h a v e c o r r u p t e d u s e r r e g i s t e r s t a t e ,
* but u s e r s p a c e w i l l n e v e r s e e t h a t r e g i s t e r s t a t e . E x e c u t i o n w i l l
* resume a f t e r t h e t b e g i n o f t h e a b o r t e d t r a n s a c t i o n w i t h t h e
* checkpointed r e g i s t e r s t a t e .
* /
2016-07-25 14:26:51 +10:00
li r9 , M S R _ R I
andc r10 , r10 , r9
2015-06-12 11:06:32 +10:00
mtmsrd r10 , 1
mtspr S P R N _ S R R 0 , r11
mtspr S P R N _ S R R 1 , r12
2018-01-10 03:07:15 +11:00
RFI_ T O _ U S E R
2015-06-12 11:06:32 +10:00
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
# endif
2017-06-29 23:19:16 +05:30
_ ASM_ N O K P R O B E _ S Y M B O L ( s y s t e m _ c a l l _ c o m m o n ) ;
2017-06-29 23:19:18 +05:30
_ ASM_ N O K P R O B E _ S Y M B O L ( s y s t e m _ c a l l _ e x i t ) ;
2015-06-12 11:06:32 +10:00
2005-10-10 22:36:14 +10:00
/* Save non-volatile GPRs, if not already saved. */
_ GLOBAL( s a v e _ n v g p r s )
ld r11 ,_ T R A P ( r1 )
andi. r0 ,r11 ,1
beqlr-
SAVE_ N V G P R S ( r1 )
clrrdi r0 ,r11 ,1
std r0 ,_ T R A P ( r1 )
blr
2017-06-29 23:19:19 +05:30
_ ASM_ N O K P R O B E _ S Y M B O L ( s a v e _ n v g p r s ) ;
2005-10-10 22:36:14 +10:00
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
2005-10-10 22:36:14 +10:00
/ *
* The s i g s u s p e n d a n d r t _ s i g s u s p e n d s y s t e m c a l l s c a n c a l l d o _ s i g n a l
* and t h u s p u t t h e p r o c e s s i n t o t h e s t o p p e d s t a t e w h e r e w e m i g h t
* want t o e x a m i n e i t s u s e r s t a t e w i t h p t r a c e . T h e r e f o r e w e n e e d
* to s a v e a l l t h e n o n v o l a t i l e r e g i s t e r s ( r14 - r31 ) b e f o r e c a l l i n g
* the C c o d e . S i m i l a r l y , f o r k , v f o r k a n d c l o n e n e e d t h e f u l l
* register s t a t e o n t h e s t a c k s o t h a t i t c a n b e c o p i e d t o t h e c h i l d .
* /
_ GLOBAL( p p c _ f o r k )
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
bl s y s _ f o r k
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
2005-10-10 22:36:14 +10:00
_ GLOBAL( p p c _ v f o r k )
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
bl s y s _ v f o r k
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
2005-10-10 22:36:14 +10:00
_ GLOBAL( p p c _ c l o n e )
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
bl s y s _ c l o n e
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
2005-10-10 22:36:14 +10:00
2006-03-08 13:24:22 +11:00
_ GLOBAL( p p c32 _ s w a p c o n t e x t )
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
bl c o m p a t _ s y s _ s w a p c o n t e x t
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
2006-03-08 13:24:22 +11:00
_ GLOBAL( p p c64 _ s w a p c o n t e x t )
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
bl s y s _ s w a p c o n t e x t
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
2006-03-08 13:24:22 +11:00
powerpc: Add a proper syscall for switching endianness
We currently have a "special" syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
exception entry.
That has a few problems, firstly the syscall number is outside of the
usual range, which confuses various tools. For example strace doesn't
recognise the syscall at all.
Secondly it's handled explicitly as a special case in the syscall
exception entry, which is complicated enough without it.
As a first step toward removing the special syscall, we need to add a
regular syscall that implements the same functionality.
The logic is simple, it simply toggles the MSR_LE bit in the userspace
MSR. This is the same as the special syscall, with the caveat that the
special syscall clobbers fewer registers.
This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-03-28 21:35:16 +11:00
_ GLOBAL( p p c _ s w i t c h _ e n d i a n )
bl s a v e _ n v g p r s
bl s y s _ s w i t c h _ e n d i a n
b . L s y s c a l l _ e x i t
2005-10-10 22:36:14 +10:00
_ GLOBAL( r e t _ f r o m _ f o r k )
2014-02-04 16:04:35 +11:00
bl s c h e d u l e _ t a i l
2005-10-10 22:36:14 +10:00
REST_ N V G P R S ( r1 )
li r3 ,0
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
2005-10-10 22:36:14 +10:00
2012-09-12 18:32:42 -04:00
_ GLOBAL( r e t _ f r o m _ k e r n e l _ t h r e a d )
2014-02-04 16:04:35 +11:00
bl s c h e d u l e _ t a i l
2012-09-12 18:32:42 -04:00
REST_ N V G P R S ( r1 )
mtlr r14
mr r3 ,r15
2016-06-06 22:26:10 +05:30
# ifdef P P C 6 4 _ E L F _ A B I _ v2
2014-02-04 16:08:51 +11:00
mr r12 ,r14
# endif
2012-09-12 18:32:42 -04:00
blrl
li r3 ,0
2014-12-05 21:16:59 +11:00
b . L s y s c a l l _ e x i t
2012-08-31 15:48:05 -04:00
2018-07-24 01:07:54 +10:00
# ifdef C O N F I G _ P P C _ B O O K 3 S _ 6 4
# define F L U S H _ C O U N T _ C A C H E \
1 : nop; \
patch_ s i t e 1 b , p a t c h _ _ c a l l _ f l u s h _ c o u n t _ c a c h e
# define B C C T R _ F L U S H . l o n g 0 x4 c40 0 4 2 0
.macro nops number
.rept \ number
nop
.endr
.endm
.balign 32
.global flush_count_cache
flush_count_cache :
/* Save LR into r9 */
mflr r9
.rept 64
bl . + 4
.endr
b 1 f
nops 6
.balign 32
/* Restore LR */
1 : mtlr r9
li r9 ,0 x7 f f f
mtctr r9
BCCTR_ F L U S H
2 : nop
patch_ s i t e 2 b p a t c h _ _ f l u s h _ c o u n t _ c a c h e _ r e t u r n
nops 3
.rept 278
.balign 32
BCCTR_ F L U S H
nops 7
.endr
blr
# else
# define F L U S H _ C O U N T _ C A C H E
# endif / * C O N F I G _ P P C _ B O O K 3 S _ 6 4 * /
2005-10-10 22:36:14 +10:00
/ *
* This r o u t i n e s w i t c h e s b e t w e e n t w o d i f f e r e n t t a s k s . T h e p r o c e s s
* state o f o n e i s s a v e d o n i t s k e r n e l s t a c k . T h e n t h e s t a t e
* of t h e o t h e r i s r e s t o r e d f r o m i t s k e r n e l s t a c k . T h e m e m o r y
* management h a r d w a r e i s u p d a t e d t o t h e s e c o n d p r o c e s s ' s s t a t e .
* Finally, w e c a n r e t u r n t o t h e s e c o n d p r o c e s s , v i a r e t _ f r o m _ e x c e p t .
* On e n t r y , r3 p o i n t s t o t h e T H R E A D f o r t h e c u r r e n t t a s k , r4
* points t o t h e T H R E A D f o r t h e n e w t a s k .
*
* Note : there a r e t w o w a y s t o g e t t o t h e " g o i n g o u t " p o r t i o n
* of t h i s c o d e ; either by coming in via the entry (_switch)
* or v i a " f o r k " w h i c h m u s t s e t u p a n e n v i r o n m e n t e q u i v a l e n t
* to t h e " _ s w i t c h " p a t h . I f y o u c h a n g e t h i s y o u ' l l h a v e t o c h a n g e
* the f o r k c o d e a l s o .
*
* The c o d e w h i c h c r e a t e s t h e n e w t a s k c o n t e x t i s i n ' c o p y _ t h r e a d '
2006-01-23 10:58:20 -06:00
* in a r c h / p o w e r p c / k e r n e l / p r o c e s s . c
2005-10-10 22:36:14 +10:00
* /
.align 7
_ GLOBAL( _ s w i t c h )
mflr r0
std r0 ,1 6 ( r1 )
stdu r1 ,- S W I T C H _ F R A M E _ S I Z E ( r1 )
/* r3-r13 are caller saved -- Cort */
SAVE_ 8 G P R S ( 1 4 , r1 )
SAVE_ 1 0 G P R S ( 2 2 , r1 )
2015-10-29 11:43:56 +11:00
std r0 ,_ N I P ( r1 ) / * R e t u r n t o s w i t c h c a l l e r * /
2005-10-10 22:36:14 +10:00
mfcr r23
std r23 ,_ C C R ( r1 )
std r1 ,K S P ( r3 ) / * S e t o l d s t a c k p o i n t e r * /
2018-07-24 01:07:54 +10:00
FLUSH_ C O U N T _ C A C H E
2017-06-09 01:36:08 +10:00
/ *
* On S M P k e r n e l s , c a r e m u s t b e t a k e n b e c a u s e a t a s k m a y b e
* scheduled o f f C P U x a n d o n t o C P U y . M e m o r y o r d e r i n g m u s t b e
* considered.
*
* Cacheable s t o r e s o n C P U x w i l l b e v i s i b l e w h e n t h e t a s k i s
* scheduled o n C P U y b y v i r t u e o f t h e c o r e s c h e d u l e r b a r r i e r s
* ( see " N o t e s o n P r o g r a m - O r d e r g u a r a n t e e s o n S M P s y s t e m s . " i n
* kernel/ s c h e d / c o r e . c ) .
*
* Uncacheable s t o r e s i n t h e c a s e o f i n v o l u n t a r y p r e e m p t i o n m u s t
* be t a k e n c a r e o f . T h e s m p _ m b _ _ b e f o r e _ s p i n _ l o c k ( ) i n _ _ s c h e d u l e ( )
* is i m p l e m e n t e d a s h w s y n c o n p o w e r p c , w h i c h o r d e r s M M I O t o o . S o
* long a s t h e r e i s a n h w s y n c i n t h e c o n t e x t s w i t c h p a t h , i t w i l l
* be e x e c u t e d o n t h e s o u r c e C P U a f t e r t h e t a s k h a s p e r f o r m e d
* all M M I O o p s o n t h a t C P U , a n d o n t h e d e s t i n a t i o n C P U b e f o r e t h e
* task p e r f o r m s a n y M M I O o p s t h e r e .
2005-10-10 22:36:14 +10:00
* /
2010-08-11 01:40:27 +00:00
/ *
2017-06-09 01:36:07 +10:00
* The k e r n e l c o n t e x t s w i t c h p a t h m u s t c o n t a i n a s p i n _ l o c k ,
* which c o n t a i n s l a r x / s t c x , w h i c h w i l l c l e a r a n y r e s e r v a t i o n
* of t h e t a s k b e i n g s w i t c h e d .
2010-08-11 01:40:27 +00:00
* /
2013-05-29 19:34:27 +00:00
# ifdef C O N F I G _ P P C _ B O O K 3 S
/ * Cancel a l l e x p l i c t u s e r s t r e a m s a s t h e y w i l l h a v e n o u s e a f t e r c o n t e x t
* switch a n d w i l l s t o p t h e H W f r o m c r e a t i n g s t r e a m s i t s e l f
* /
2018-02-21 05:08:26 +10:00
DCBT_ B O O K 3 S _ S T O P _ A L L _ S T R E A M _ I D S ( r6 )
2013-05-29 19:34:27 +00:00
# endif
2005-10-10 22:36:14 +10:00
addi r6 ,r4 ,- T H R E A D / * C o n v e r t T H R E A D t o ' c u r r e n t ' * /
std r6 ,P A C A C U R R E N T ( r13 ) / * S e t n e w ' c u r r e n t ' * /
2018-09-27 07:05:55 +00:00
# if d e f i n e d ( C O N F I G _ S T A C K P R O T E C T O R )
ld r6 , T A S K _ C A N A R Y ( r6 )
std r6 , P A C A _ C A N A R Y ( r13 )
# endif
2005-10-10 22:36:14 +10:00
ld r8 ,K S P ( r4 ) / * n e w s t a c k p o i n t e r * /
2017-10-19 15:08:43 +11:00
# ifdef C O N F I G _ P P C _ B O O K 3 S _ 6 4
2016-04-29 23:26:07 +10:00
BEGIN_ M M U _ F T R _ S E C T I O N
b 2 f
2016-07-27 13:19:01 +10:00
END_ M M U _ F T R _ S E C T I O N _ I F S E T ( M M U _ F T R _ T Y P E _ R A D I X )
2007-10-11 20:37:10 +10:00
BEGIN_ F T R _ S E C T I O N
2005-10-10 22:36:14 +10:00
clrrdi r6 ,r8 ,2 8 / * g e t i t s E S I D * /
clrrdi r9 ,r1 ,2 8 / * g e t c u r r e n t s p E S I D * /
2014-07-10 12:29:20 +10:00
FTR_ S E C T I O N _ E L S E
2007-10-11 20:37:10 +10:00
clrrdi r6 ,r8 ,4 0 / * g e t i t s 1 T E S I D * /
clrrdi r9 ,r1 ,4 0 / * g e t c u r r e n t s p 1 T E S I D * /
2014-07-10 12:29:20 +10:00
ALT_ M M U _ F T R _ S E C T I O N _ E N D _ I F C L R ( M M U _ F T R _ 1 T _ S E G M E N T )
2005-10-10 22:36:14 +10:00
clrldi. r0 ,r6 ,2 / * i s n e w E S I D c00 0 0 0 0 0 0 ? * /
cmpd c r1 ,r6 ,r9 / * o r i s n e w E S I D t h e s a m e a s c u r r e n t E S I D ? * /
cror e q ,4 * c r1 + e q ,e q
beq 2 f / * i f y e s , d o n ' t s l b i e i t * /
/* Bolt in the new stack SLB entry */
ld r7 ,K S P _ V S I D ( r4 ) / * G e t n e w s t a c k ' s V S I D * /
oris r0 ,r6 ,( S L B _ E S I D _ V ) @h
ori r0 ,r0 ,( S L B _ N U M _ B O L T E D - 1 ) @l
2007-10-11 20:37:10 +10:00
BEGIN_ F T R _ S E C T I O N
li r9 ,M M U _ S E G S I Z E _ 1 T / * i n s e r t B f i e l d * /
oris r6 ,r6 ,( M M U _ S E G S I Z E _ 1 T < < S L B I E _ S S I Z E _ S H I F T ) @h
rldimi r7 ,r9 ,S L B _ V S I D _ S S I Z E _ S H I F T ,0
2011-04-06 19:48:50 +00:00
END_ M M U _ F T R _ S E C T I O N _ I F S E T ( M M U _ F T R _ 1 T _ S E G M E N T )
2006-08-07 16:19:19 +10:00
2007-08-24 16:58:37 +10:00
/ * Update t h e l a s t b o l t e d S L B . N o w r i t e b a r r i e r s a r e n e e d e d
* here, p r o v i d e d w e o n l y u p d a t e t h e c u r r e n t C P U ' s S L B s h a d o w
* buffer.
* /
2006-08-07 16:19:19 +10:00
ld r9 ,P A C A _ S L B S H A D O W P T R ( r13 )
2006-08-09 17:00:30 +10:00
li r12 ,0
2013-08-07 02:01:46 +10:00
std r12 ,S L B S H A D O W _ S T A C K E S I D ( r9 ) / * C l e a r E S I D * /
li r12 ,S L B S H A D O W _ S T A C K V S I D
STDX_ B E r7 ,r12 ,r9 / * S a v e V S I D * /
li r12 ,S L B S H A D O W _ S T A C K E S I D
STDX_ B E r0 ,r12 ,r9 / * S a v e E S I D * /
2006-08-07 16:19:19 +10:00
2011-04-06 19:48:50 +00:00
/ * No n e e d t o c h e c k f o r M M U _ F T R _ N O _ S L B I E _ B h e r e , s i n c e w h e n
2007-10-16 00:58:59 +10:00
* we h a v e 1 T B s e g m e n t s , t h e o n l y C P U s k n o w n t o h a v e t h e e r r a t a
* only s u p p o r t l e s s t h a n 1 T B o f s y s t e m m e m o r y a n d w e ' l l n e v e r
* actually h i t t h i s c o d e p a t h .
* /
powerpc/mm/hash: Add missing isync prior to kernel stack SLB switch
Currently we do not have an isync, or any other context synchronizing
instruction prior to the slbie/slbmte in _switch() that updates the
SLB entry for the kernel stack.
However that is not correct as outlined in the ISA.
From Power ISA Version 3.0B, Book III, Chapter 11, page 1133:
"Changing the contents of ... the contents of SLB entries ... can
have the side effect of altering the context in which data
addresses and instruction addresses are interpreted, and in which
instructions are executed and data accesses are performed.
...
These side effects need not occur in program order, and therefore
may require explicit synchronization by software.
...
The synchronizing instruction before the context-altering
instruction ensures that all instructions up to and including that
synchronizing instruction are fetched and executed in the context
that existed before the alteration."
And page 1136:
"For data accesses, the context synchronizing instruction before the
slbie, slbieg, slbia, slbmte, tlbie, or tlbiel instruction ensures
that all preceding instructions that access data storage have
completed to a point at which they have reported all exceptions
they will cause."
We're not aware of any bugs caused by this, but it should be fixed
regardless.
Add the missing isync when updating kernel stack SLB entry.
Cc: stable@vger.kernel.org
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
[mpe: Flesh out change log with more ISA text & explanation]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-05-30 18:48:04 +05:30
isync
2005-10-10 22:36:14 +10:00
slbie r6
2018-09-15 01:30:46 +10:00
BEGIN_ F T R _ S E C T I O N
2005-10-10 22:36:14 +10:00
slbie r6 / * W o r k a r o u n d P O W E R 5 < D D 2 . 1 i s s u e * /
2018-09-15 01:30:46 +10:00
END_ F T R _ S E C T I O N _ I F C L R ( C P U _ F T R _ A R C H _ 2 0 7 S )
2005-10-10 22:36:14 +10:00
slbmte r7 ,r0
isync
2 :
2017-10-19 15:08:43 +11:00
# endif / * C O N F I G _ P P C _ B O O K 3 S _ 6 4 * /
2009-07-23 23:15:59 +00:00
2019-01-17 23:23:57 +11:00
clrrdi r7 , r8 , T H R E A D _ S H I F T / * b a s e o f n e w s t a c k * /
2005-10-10 22:36:14 +10:00
/ * Note : this u s e s S W I T C H _ F R A M E _ S I Z E r a t h e r t h a n I N T _ F R A M E _ S I Z E
because w e d o n ' t n e e d t o l e a v e t h e 2 8 8 - b y t e A B I g a p a t t h e
top o f t h e k e r n e l s t a c k . * /
addi r7 ,r7 ,T H R E A D _ S I Z E - S W I T C H _ F R A M E _ S I Z E
2017-06-09 01:36:06 +10:00
/ *
* PMU i n t e r r u p t s i n r a d i x m a y c o m e i n h e r e . T h e y w i l l u s e r1 , n o t
* PACAKSAVE, s o t h i s s t a c k s w i t c h w i l l n o t c a u s e a p r o b l e m . T h e y
* will s t o r e t o t h e p r o c e s s s t a c k , w h i c h m a y t h e n b e m i g r a t e d t o
* another C P U . H o w e v e r t h e r q l o c k r e l e a s e o n t h i s C P U p a i r e d w i t h
* the r q l o c k a c q u i r e o n t h e n e w C P U b e f o r e t h e s t a c k b e c o m e s
* active o n t h e n e w C P U , w i l l o r d e r t h o s e s t o r e s .
* /
2005-10-10 22:36:14 +10:00
mr r1 ,r8 / * s t a r t u s i n g n e w s t a c k p o i n t e r * /
std r7 ,P A C A K S A V E ( r13 )
2012-09-03 16:51:10 +00:00
ld r6 ,_ C C R ( r1 )
mtcrf 0 x F F ,r6
2005-10-10 22:36:14 +10:00
/* r3-r13 are destroyed -- Cort */
REST_ 8 G P R S ( 1 4 , r1 )
REST_ 1 0 G P R S ( 2 2 , r1 )
/* convert old thread to its task_struct for return value */
addi r3 ,r3 ,- T H R E A D
ld r7 ,_ N I P ( r1 ) / * R e t u r n t o _ s w i t c h c a l l e r i n n e w t a s k * /
mtlr r7
addi r1 ,r1 ,S W I T C H _ F R A M E _ S I Z E
blr
.align 7
_ GLOBAL( r e t _ f r o m _ e x c e p t )
ld r11 ,_ T R A P ( r1 )
andi. r0 ,r11 ,1
2014-02-04 16:04:35 +11:00
bne r e t _ f r o m _ e x c e p t _ l i t e
2005-10-10 22:36:14 +10:00
REST_ N V G P R S ( r1 )
_ GLOBAL( r e t _ f r o m _ e x c e p t _ l i t e )
/ *
* Disable i n t e r r u p t s s o t h a t c u r r e n t _ t h r e a d _ i n f o ( ) - > f l a g s
* can' t c h a n g e b e t w e e n w h e n w e t e s t i t a n d w h e n w e r e t u r n
* from t h e i n t e r r u p t .
* /
2009-07-23 23:15:59 +00:00
# ifdef C O N F I G _ P P C _ B O O K 3 E
wrteei 0
# else
2016-09-15 19:04:46 +10:00
li r10 ,M S R _ R I
2012-03-02 11:33:52 +11:00
mtmsrd r10 ,1 / * U p d a t e m a c h i n e s t a t e * /
2009-07-23 23:15:59 +00:00
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
2005-10-10 22:36:14 +10:00
2019-01-12 09:55:50 +00:00
ld r9 , P A C A _ T H R E A D _ I N F O ( r13 )
2005-10-10 22:36:14 +10:00
ld r3 ,_ M S R ( r1 )
2013-05-22 09:50:59 +05:30
# ifdef C O N F I G _ P P C _ B O O K 3 E
ld r10 ,P A C A C U R R E N T ( r13 )
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
2005-10-10 22:36:14 +10:00
ld r4 ,T I _ F L A G S ( r9 )
andi. r3 ,r3 ,M S R _ P R
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
beq r e s u m e _ k e r n e l
2013-05-22 09:50:59 +05:30
# ifdef C O N F I G _ P P C _ B O O K 3 E
lwz r3 ,( T H R E A D + T H R E A D _ D B C R 0 ) ( r10 )
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
2005-10-10 22:36:14 +10:00
/* Check current_thread_info()->flags */
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
andi. r0 ,r4 ,_ T I F _ U S E R _ W O R K _ M A S K
2013-05-22 09:50:59 +05:30
bne 1 f
2016-02-29 17:53:47 +11:00
# ifdef C O N F I G _ P P C _ B O O K 3 E
2013-05-22 09:50:59 +05:30
/ *
* Check t o s e e i f t h e d b c r0 r e g i s t e r i s s e t u p t o d e b u g .
* Use t h e i n t e r n a l d e b u g m o d e b i t t o d o t h i s .
* /
andis. r0 ,r3 ,D B C R 0 _ I D M @h
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
beq r e s t o r e
2013-05-22 09:50:59 +05:30
mfmsr r0
rlwinm r0 ,r0 ,0 ,~ M S R _ D E / * C l e a r M S R . D E * /
mtmsr r0
mtspr S P R N _ D B C R 0 ,r3
li r10 , - 1
mtspr S P R N _ D B S R ,r10
b r e s t o r e
# else
2016-02-29 17:53:47 +11:00
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
bl r e s t o r e _ m a t h
b r e s t o r e
2013-05-22 09:50:59 +05:30
# endif
1 : andi. r0 ,r4 ,_ T I F _ N E E D _ R E S C H E D
beq 2 f
2014-02-04 16:04:35 +11:00
bl r e s t o r e _ i n t e r r u p t s
2013-05-13 16:16:43 +00:00
SCHEDULE_ U S E R
2014-02-04 16:04:35 +11:00
b r e t _ f r o m _ e x c e p t _ l i t e
powerpc: Don't corrupt transactional state when using FP/VMX in kernel
Currently, when we have a process using the transactional memory
facilities on POWER8 (that is, the processor is in transactional
or suspended state), and the process enters the kernel and the
kernel then uses the floating-point or vector (VMX/Altivec) facility,
we end up corrupting the user-visible FP/VMX/VSX state. This
happens, for example, if a page fault causes a copy-on-write
operation, because the copy_page function will use VMX to do the
copy on POWER8. The test program below demonstrates the bug.
The bug happens because when FP/VMX state for a transactional process
is stored in the thread_struct, we store the checkpointed state in
.fp_state/.vr_state and the transactional (current) state in
.transact_fp/.transact_vr. However, when the kernel wants to use
FP/VMX, it calls enable_kernel_fp() or enable_kernel_altivec(),
which saves the current state in .fp_state/.vr_state. Furthermore,
when we return to the user process we return with FP/VMX/VSX
disabled. The next time the process uses FP/VMX/VSX, we don't know
which set of state (the current register values, .fp_state/.vr_state,
or .transact_fp/.transact_vr) we should be using, since we have no
way to tell if we are still in the same transaction, and if not,
whether the previous transaction succeeded or failed.
Thus it is necessary to strictly adhere to the rule that if FP has
been enabled at any point in a transaction, we must keep FP enabled
for the user process with the current transactional state in the
FP registers, until we detect that it is no longer in a transaction.
Similarly for VMX; once enabled it must stay enabled until the
process is no longer transactional.
In order to keep this rule, we add a new thread_info flag which we
test when returning from the kernel to userspace, called TIF_RESTORE_TM.
This flag indicates that there is FP/VMX/VSX state to be restored
before entering userspace, and when it is set the .tm_orig_msr field
in the thread_struct indicates what state needs to be restored.
The restoration is done by restore_tm_state(). The TIF_RESTORE_TM
bit is set by new giveup_fpu/altivec_maybe_transactional helpers,
which are called from enable_kernel_fp/altivec, giveup_vsx, and
flush_fp/altivec_to_thread instead of giveup_fpu/altivec.
The other thing to be done is to get the transactional FP/VMX/VSX
state from .fp_state/.vr_state when doing reclaim, if that state
has been saved there by giveup_fpu/altivec_maybe_transactional.
Having done this, we set the FP/VMX bit in the thread's MSR after
reclaim to indicate that that part of the state is now valid
(having been reclaimed from the processor's checkpointed state).
Finally, in the signal handling code, we move the clearing of the
transactional state bits in the thread's MSR a bit earlier, before
calling flush_fp_to_thread(), so that we don't unnecessarily set
the TIF_RESTORE_TM bit.
This is the test program:
/* Michael Neuling 4/12/2013
*
* See if the altivec state is leaked out of an aborted transaction due to
* kernel vmx copy loops.
*
* gcc -m64 htm_vmxcopy.c -o htm_vmxcopy
*
*/
/* We don't use all of these, but for reference: */
int main(int argc, char *argv[])
{
long double vecin = 1.3;
long double vecout;
unsigned long pgsize = getpagesize();
int i;
int fd;
int size = pgsize*16;
char tmpfile[] = "/tmp/page_faultXXXXXX";
char buf[pgsize];
char *a;
uint64_t aborted = 0;
fd = mkstemp(tmpfile);
assert(fd >= 0);
memset(buf, 0, pgsize);
for (i = 0; i < size; i += pgsize)
assert(write(fd, buf, pgsize) == pgsize);
unlink(tmpfile);
a = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
assert(a != MAP_FAILED);
asm __volatile__(
"lxvd2x 40,0,%[vecinptr] ; " // set 40 to initial value
TBEGIN
"beq 3f ;"
TSUSPEND
"xxlxor 40,40,40 ; " // set 40 to 0
"std 5, 0(%[map]) ;" // cause kernel vmx copy page
TABORT
TRESUME
TEND
"li %[res], 0 ;"
"b 5f ;"
"3: ;" // Abort handler
"li %[res], 1 ;"
"5: ;"
"stxvd2x 40,0,%[vecoutptr] ; "
: [res]"=r"(aborted)
: [vecinptr]"r"(&vecin),
[vecoutptr]"r"(&vecout),
[map]"r"(a)
: "memory", "r0", "r3", "r4", "r5", "r6", "r7");
if (aborted && (vecin != vecout)){
printf("FAILED: vector state leaked on abort %f != %f\n",
(double)vecin, (double)vecout);
exit(1);
}
munmap(a, size);
close(fd);
printf("PASSED!\n");
return 0;
}
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-01-13 15:56:29 +11:00
2 :
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
andi. r0 ,r4 ,_ T I F _ U S E R _ W O R K _ M A S K & ~ _ T I F _ R E S T O R E _ T M
bne 3 f / * o n l y r e s t o r e T M i f n o t h i n g e l s e t o d o * /
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2014-02-04 16:04:35 +11:00
bl r e s t o r e _ t m _ s t a t e
powerpc: Don't corrupt transactional state when using FP/VMX in kernel
Currently, when we have a process using the transactional memory
facilities on POWER8 (that is, the processor is in transactional
or suspended state), and the process enters the kernel and the
kernel then uses the floating-point or vector (VMX/Altivec) facility,
we end up corrupting the user-visible FP/VMX/VSX state. This
happens, for example, if a page fault causes a copy-on-write
operation, because the copy_page function will use VMX to do the
copy on POWER8. The test program below demonstrates the bug.
The bug happens because when FP/VMX state for a transactional process
is stored in the thread_struct, we store the checkpointed state in
.fp_state/.vr_state and the transactional (current) state in
.transact_fp/.transact_vr. However, when the kernel wants to use
FP/VMX, it calls enable_kernel_fp() or enable_kernel_altivec(),
which saves the current state in .fp_state/.vr_state. Furthermore,
when we return to the user process we return with FP/VMX/VSX
disabled. The next time the process uses FP/VMX/VSX, we don't know
which set of state (the current register values, .fp_state/.vr_state,
or .transact_fp/.transact_vr) we should be using, since we have no
way to tell if we are still in the same transaction, and if not,
whether the previous transaction succeeded or failed.
Thus it is necessary to strictly adhere to the rule that if FP has
been enabled at any point in a transaction, we must keep FP enabled
for the user process with the current transactional state in the
FP registers, until we detect that it is no longer in a transaction.
Similarly for VMX; once enabled it must stay enabled until the
process is no longer transactional.
In order to keep this rule, we add a new thread_info flag which we
test when returning from the kernel to userspace, called TIF_RESTORE_TM.
This flag indicates that there is FP/VMX/VSX state to be restored
before entering userspace, and when it is set the .tm_orig_msr field
in the thread_struct indicates what state needs to be restored.
The restoration is done by restore_tm_state(). The TIF_RESTORE_TM
bit is set by new giveup_fpu/altivec_maybe_transactional helpers,
which are called from enable_kernel_fp/altivec, giveup_vsx, and
flush_fp/altivec_to_thread instead of giveup_fpu/altivec.
The other thing to be done is to get the transactional FP/VMX/VSX
state from .fp_state/.vr_state when doing reclaim, if that state
has been saved there by giveup_fpu/altivec_maybe_transactional.
Having done this, we set the FP/VMX bit in the thread's MSR after
reclaim to indicate that that part of the state is now valid
(having been reclaimed from the processor's checkpointed state).
Finally, in the signal handling code, we move the clearing of the
transactional state bits in the thread's MSR a bit earlier, before
calling flush_fp_to_thread(), so that we don't unnecessarily set
the TIF_RESTORE_TM bit.
This is the test program:
/* Michael Neuling 4/12/2013
*
* See if the altivec state is leaked out of an aborted transaction due to
* kernel vmx copy loops.
*
* gcc -m64 htm_vmxcopy.c -o htm_vmxcopy
*
*/
/* We don't use all of these, but for reference: */
int main(int argc, char *argv[])
{
long double vecin = 1.3;
long double vecout;
unsigned long pgsize = getpagesize();
int i;
int fd;
int size = pgsize*16;
char tmpfile[] = "/tmp/page_faultXXXXXX";
char buf[pgsize];
char *a;
uint64_t aborted = 0;
fd = mkstemp(tmpfile);
assert(fd >= 0);
memset(buf, 0, pgsize);
for (i = 0; i < size; i += pgsize)
assert(write(fd, buf, pgsize) == pgsize);
unlink(tmpfile);
a = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
assert(a != MAP_FAILED);
asm __volatile__(
"lxvd2x 40,0,%[vecinptr] ; " // set 40 to initial value
TBEGIN
"beq 3f ;"
TSUSPEND
"xxlxor 40,40,40 ; " // set 40 to 0
"std 5, 0(%[map]) ;" // cause kernel vmx copy page
TABORT
TRESUME
TEND
"li %[res], 0 ;"
"b 5f ;"
"3: ;" // Abort handler
"li %[res], 1 ;"
"5: ;"
"stxvd2x 40,0,%[vecoutptr] ; "
: [res]"=r"(aborted)
: [vecinptr]"r"(&vecin),
[vecoutptr]"r"(&vecout),
[map]"r"(a)
: "memory", "r0", "r3", "r4", "r5", "r6", "r7");
if (aborted && (vecin != vecout)){
printf("FAILED: vector state leaked on abort %f != %f\n",
(double)vecin, (double)vecout);
exit(1);
}
munmap(a, size);
close(fd);
printf("PASSED!\n");
return 0;
}
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-01-13 15:56:29 +11:00
b r e s t o r e
3 :
# endif
2014-02-04 16:04:35 +11:00
bl s a v e _ n v g p r s
2014-10-31 16:50:57 +11:00
/ *
* Use a n o n v o l a t i l e G P R t o s a v e a n d r e s t o r e o u r t h r e a d _ i n f o f l a g s
* across t h e c a l l t o r e s t o r e _ i n t e r r u p t s .
* /
mr r30 ,r4
2014-02-04 16:04:35 +11:00
bl r e s t o r e _ i n t e r r u p t s
2014-10-31 16:50:57 +11:00
mr r4 ,r30
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2014-02-04 16:04:35 +11:00
bl d o _ n o t i f y _ r e s u m e
b r e t _ f r o m _ e x c e p t
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
resume_kernel :
2012-09-16 23:54:30 +00:00
/* check current_thread_info, _TIF_EMULATE_STACK_STORE */
2013-09-26 16:41:34 +08:00
andis. r8 ,r4 ,_ T I F _ E M U L A T E _ S T A C K _ S T O R E @h
2012-09-16 23:54:30 +00:00
beq+ 1 f
addi r8 ,r1 ,I N T _ F R A M E _ S I Z E / * G e t t h e k p r o b e d f u n c t i o n e n t r y * /
2017-04-11 10:38:13 +05:30
ld r3 ,G P R 1 ( r1 )
2012-09-16 23:54:30 +00:00
subi r3 ,r3 ,I N T _ F R A M E _ S I Z E / * d s t : A l l o c a t e a t r a m p o l i n e e x c e p t i o n f r a m e * /
mr r4 ,r1 / * s r c : c u r r e n t e x c e p t i o n f r a m e * /
mr r1 ,r3 / * R e r o u t e t h e t r a m p o l i n e f r a m e t o r1 * /
/* Copy from the original to the trampoline. */
li r5 ,I N T _ F R A M E _ S I Z E / 8 / * s i z e : I N T _ F R A M E _ S I Z E * /
li r6 ,0 / * s t a r t o f f s e t : 0 * /
mtctr r5
2 : ldx r0 ,r6 ,r4
stdx r0 ,r6 ,r3
addi r6 ,r6 ,8
bdnz 2 b
2017-04-11 10:38:13 +05:30
/* Do real store operation to complete stdu */
ld r5 ,G P R 1 ( r1 )
2012-09-16 23:54:30 +00:00
std r8 ,0 ( r5 )
/* Clear _TIF_EMULATE_STACK_STORE flag */
lis r11 ,_ T I F _ E M U L A T E _ S T A C K _ S T O R E @h
addi r5 ,r9 ,T I _ F L A G S
2013-04-09 22:31:24 +00:00
0 : ldarx r4 ,0 ,r5
2012-09-16 23:54:30 +00:00
andc r4 ,r4 ,r11
stdcx. r4 ,0 ,r5
bne- 0 b
1 :
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
# ifdef C O N F I G _ P R E E M P T
/* Check if we need to preempt */
andi. r0 ,r4 ,_ T I F _ N E E D _ R E S C H E D
beq+ r e s t o r e
/* Check that preempt_count() == 0 and interrupts are enabled */
lwz r8 ,T I _ P R E E M P T ( r9 )
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
cmpwi c r0 ,r8 ,0
bne r e s t o r e
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
ld r0 ,S O F T E ( r1 )
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
andi. r0 ,r0 ,I R Q S _ D I S A B L E D
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
bne r e s t o r e
/ *
* Here w e a r e p r e e m p t i n g t h e c u r r e n t t a s k . W e w a n t t o m a k e
2013-07-16 11:09:30 +08:00
* sure w e a r e s o f t - d i s a b l e d f i r s t a n d r e c o n c i l e i r q s t a t e .
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
* /
2013-07-16 11:09:30 +08:00
RECONCILE_ I R Q _ S T A T E ( r3 ,r4 )
2014-02-04 16:04:35 +11:00
1 : bl p r e e m p t _ s c h e d u l e _ i r q
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
/* Re-test flags and eventually loop */
2019-01-12 09:55:50 +00:00
ld r9 , P A C A _ T H R E A D _ I N F O ( r13 )
2005-10-10 22:36:14 +10:00
ld r4 ,T I _ F L A G S ( r9 )
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
andi. r0 ,r4 ,_ T I F _ N E E D _ R E S C H E D
bne 1 b
2013-01-06 00:49:34 +00:00
/ *
* arch_ l o c a l _ i r q _ r e s t o r e ( ) f r o m p r e e m p t _ s c h e d u l e _ i r q a b o v e m a y
* enable h a r d i n t e r r u p t b u t w e r e a l l y s h o u l d d i s a b l e i n t e r r u p t s
* when w e r e t u r n f r o m t h e i n t e r r u p t , a n d s o t h a t w e d o n ' t g e t
* interrupted a f t e r l o a d i n g S R R 0 / 1 .
* /
# ifdef C O N F I G _ P P C _ B O O K 3 E
wrteei 0
# else
2016-09-15 19:04:46 +10:00
li r10 ,M S R _ R I
2013-01-06 00:49:34 +00:00
mtmsrd r10 ,1 / * U p d a t e m a c h i n e s t a t e * /
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
# endif / * C O N F I G _ P R E E M P T * /
2005-10-10 22:36:14 +10:00
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
.globl fast_exc_return_irq
fast_exc_return_irq :
2005-10-10 22:36:14 +10:00
restore :
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ *
2012-05-10 16:12:38 +00:00
* This i s t h e m a i n k e r n e l e x i t p a t h . F i r s t w e c h e c k i f w e
* are a b o u t t o r e - e n a b l e i n t e r r u p t s
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
* /
2008-07-16 14:21:34 +10:00
ld r5 ,S O F T E ( r1 )
2017-12-20 09:25:50 +05:30
lbz r6 ,P A C A I R Q S O F T M A S K ( r13 )
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
andi. r5 ,r5 ,I R Q S _ D I S A B L E D
bne . L r e s t o r e _ i r q _ o f f
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
2012-05-10 16:12:38 +00:00
/* We are enabling, were we already enabled ? Yes, just return */
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
andi. r6 ,r6 ,I R Q S _ D I S A B L E D
2017-06-29 23:19:19 +05:30
beq c r0 ,. L d o _ r e s t o r e
2005-10-10 22:36:14 +10:00
2012-05-10 16:12:38 +00:00
/ *
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
* We a r e a b o u t t o s o f t - e n a b l e i n t e r r u p t s ( w e a r e h a r d d i s a b l e d
* at t h i s p o i n t ) . W e c h e c k i f t h e r e ' s a n y t h i n g t h a t n e e d s t o
* be r e p l a y e d f i r s t .
* /
lbz r0 ,P A C A I R Q H A P P E N E D ( r13 )
cmpwi c r0 ,r0 ,0
2017-06-29 23:19:19 +05:30
bne- . L r e s t o r e _ c h e c k _ i r q _ r e p l a y
2007-02-07 13:13:26 +11:00
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ *
* Get h e r e w h e n n o t h i n g h a p p e n e d w h i l e s o f t - d i s a b l e d , j u s t
* soft- e n a b l e a n d m o v e - o n . W e w i l l h a r d - e n a b l e a s a s i d e
* effect o f r f i
* /
2017-06-29 23:19:19 +05:30
.Lrestore_no_replay :
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
TRACE_ E N A B L E _ I N T S
2017-12-20 09:25:42 +05:30
li r0 ,I R Q S _ E N A B L E D
2017-12-20 09:25:50 +05:30
stb r0 ,P A C A I R Q S O F T M A S K ( r13 ) ;
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ *
* Final r e t u r n p a t h . B o o k E i s h a n d l e d i n a d i f f e r e n t f i l e
* /
2017-06-29 23:19:19 +05:30
.Ldo_restore :
2009-07-23 23:15:59 +00:00
# ifdef C O N F I G _ P P C _ B O O K 3 E
2014-02-04 16:04:35 +11:00
b e x c e p t i o n _ r e t u r n _ b o o k 3 e
2009-07-23 23:15:59 +00:00
# else
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ *
* Clear t h e r e s e r v a t i o n . I f w e k n o w t h e C P U t r a c k s t h e a d d r e s s o f
* the r e s e r v a t i o n t h e n w e c a n p o t e n t i a l l y s a v e s o m e c y c l e s a n d u s e
* a l a r x . O n P O W E R 6 a n d P O W E R 7 t h i s i s s i g n i f i c a n t l y f a s t e r .
* /
BEGIN_ F T R _ S E C T I O N
stdcx. r0 ,0 ,r1 / * t o c l e a r t h e r e s e r v a t i o n * /
FTR_ S E C T I O N _ E L S E
ldarx r4 ,0 ,r1
ALT_ F T R _ S E C T I O N _ E N D _ I F C L R ( C P U _ F T R _ S T C X _ C H E C K S _ A D D R E S S )
/ *
* Some c o d e p a t h s u c h a s l o a d _ u p _ f p u o r a l t i v e c r e t u r n d i r e c t l y
* here. T h e y r u n e n t i r e l y h a r d d i s a b l e d a n d d o n o t a l t e r t h e
* interrupt s t a t e . T h e y a l s o d o n ' t u s e l w a r x / s t w c x . a n d t h u s
* are k n o w n n o t t o l e a v e d a n g l i n g r e s e r v a t i o n s .
* /
.globl fast_exception_return
fast_exception_return :
ld r3 ,_ M S R ( r1 )
2007-02-07 13:13:26 +11:00
ld r4 ,_ C T R ( r1 )
ld r0 ,_ L I N K ( r1 )
mtctr r4
mtlr r0
ld r4 ,_ X E R ( r1 )
mtspr S P R N _ X E R ,r4
REST_ 8 G P R S ( 5 , r1 )
2005-10-10 22:36:14 +10:00
andi. r0 ,r3 ,M S R _ R I
2017-06-29 23:19:19 +05:30
beq- . L u n r e c o v _ r e s t o r e
2005-10-10 22:36:14 +10:00
2007-02-07 13:13:26 +11:00
/ *
* Clear R I b e f o r e r e s t o r i n g r13 . I f w e a r e r e t u r n i n g t o
* userspace a n d w e t a k e a n e x c e p t i o n a f t e r r e s t o r i n g r13 ,
* we e n d u p c o r r u p t i n g t h e u s e r s p a c e r13 v a l u e .
* /
2016-09-15 19:04:46 +10:00
li r4 ,0
2007-02-07 13:13:26 +11:00
mtmsrd r4 ,1
2005-10-10 22:36:14 +10:00
2013-02-13 16:21:34 +00:00
# ifdef C O N F I G _ P P C _ T R A N S A C T I O N A L _ M E M
/* TM debug */
std r3 , P A C A T M S C R A T C H ( r13 ) / * S t a s h r e t u r n e d - t o M S R * /
# endif
2005-10-10 22:36:14 +10:00
/ *
* r1 3 i s o u r p e r c p u a r e a , o n l y r e s t o r e i t i f w e a r e r e t u r n i n g t o
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
* userspace t h e v a l u e s t o r e d i n t h e s t a c k f r a m e m a y b e l o n g t o
* another C P U .
2005-10-10 22:36:14 +10:00
* /
2007-02-07 13:13:26 +11:00
andi. r0 ,r3 ,M S R _ P R
2005-10-10 22:36:14 +10:00
beq 1 f
2013-11-05 16:33:22 +11:00
BEGIN_ F T R _ S E C T I O N
2018-10-13 00:15:16 +11:00
/* Restore PPR */
ld r2 ,_ P P R ( r1 )
mtspr S P R N _ P P R ,r2
2013-11-05 16:33:22 +11:00
END_ F T R _ S E C T I O N _ I F S E T ( C P U _ F T R _ H A S _ P P R )
2016-05-17 08:33:46 +02:00
ACCOUNT_ C P U _ U S E R _ E X I T ( r13 , r2 , r4 )
2005-10-10 22:36:14 +10:00
REST_ G P R ( 1 3 , r1 )
2018-01-10 03:07:15 +11:00
2007-02-07 13:13:26 +11:00
mtspr S P R N _ S R R 1 ,r3
2005-10-10 22:36:14 +10:00
ld r2 ,_ C C R ( r1 )
mtcrf 0 x F F ,r2
ld r2 ,_ N I P ( r1 )
mtspr S P R N _ S R R 0 ,r2
ld r0 ,G P R 0 ( r1 )
ld r2 ,G P R 2 ( r1 )
ld r3 ,G P R 3 ( r1 )
ld r4 ,G P R 4 ( r1 )
ld r1 ,G P R 1 ( r1 )
2018-01-10 03:07:15 +11:00
RFI_ T O _ U S E R
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
2005-10-10 22:36:14 +10:00
2018-01-10 03:07:15 +11:00
1 : mtspr S P R N _ S R R 1 ,r3
ld r2 ,_ C C R ( r1 )
mtcrf 0 x F F ,r2
ld r2 ,_ N I P ( r1 )
mtspr S P R N _ S R R 0 ,r2
2005-10-10 22:36:14 +10:00
powerpc/64s: Clear on-stack exception marker upon exception return
The ppc64 specific implementation of the reliable stacktracer,
save_stack_trace_tsk_reliable(), bails out and reports an "unreliable
trace" whenever it finds an exception frame on the stack. Stack frames
are classified as exception frames if the STACK_FRAME_REGS_MARKER
magic, as written by exception prologues, is found at a particular
location.
However, as observed by Joe Lawrence, it is possible in practice that
non-exception stack frames can alias with prior exception frames and
thus, that the reliable stacktracer can find a stale
STACK_FRAME_REGS_MARKER on the stack. It in turn falsely reports an
unreliable stacktrace and blocks any live patching transition to
finish. Said condition lasts until the stack frame is
overwritten/initialized by function call or other means.
In principle, we could mitigate this by making the exception frame
classification condition in save_stack_trace_tsk_reliable() stronger:
in addition to testing for STACK_FRAME_REGS_MARKER, we could also take
into account that for all exceptions executing on the kernel stack
- their stack frames's backlink pointers always match what is saved
in their pt_regs instance's ->gpr[1] slot and that
- their exception frame size equals STACK_INT_FRAME_SIZE, a value
uncommonly large for non-exception frames.
However, while these are currently true, relying on them would make
the reliable stacktrace implementation more sensitive towards future
changes in the exception entry code. Note that false negatives, i.e.
not detecting exception frames, would silently break the live patching
consistency model.
Furthermore, certain other places (diagnostic stacktraces, perf, xmon)
rely on STACK_FRAME_REGS_MARKER as well.
Make the exception exit code clear the on-stack
STACK_FRAME_REGS_MARKER for those exceptions running on the "normal"
kernel stack and returning to kernelspace: because the topmost frame
is ignored by the reliable stack tracer anyway, returns to userspace
don't need to take care of clearing the marker.
Furthermore, as I don't have the ability to test this on Book 3E or 32
bits, limit the change to Book 3S and 64 bits.
Fixes: df78d3f61480 ("powerpc/livepatch: Implement reliable stack tracing for the consistency model")
Reported-by: Joe Lawrence <joe.lawrence@redhat.com>
Signed-off-by: Nicolai Stange <nstange@suse.de>
Signed-off-by: Joe Lawrence <joe.lawrence@redhat.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-01-22 10:57:21 -05:00
/ *
* Leaving a s t a l e e x c e p t i o n _ m a r k e r o n t h e s t a c k c a n c o n f u s e
* the r e l i a b l e s t a c k u n w i n d e r l a t e r o n . C l e a r i t .
* /
li r2 ,0
std r2 ,S T A C K _ F R A M E _ O V E R H E A D - 1 6 ( r1 )
2018-01-10 03:07:15 +11:00
ld r0 ,G P R 0 ( r1 )
ld r2 ,G P R 2 ( r1 )
ld r3 ,G P R 3 ( r1 )
ld r4 ,G P R 4 ( r1 )
ld r1 ,G P R 1 ( r1 )
RFI_ T O _ K E R N E L
2005-10-10 22:36:14 +10:00
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
2009-07-23 23:15:59 +00:00
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
2012-05-10 16:12:38 +00:00
/ *
* We a r e r e t u r n i n g t o a c o n t e x t w i t h i n t e r r u p t s s o f t d i s a b l e d .
*
* However, w e m a y a l s o a b o u t t o h a r d e n a b l e , s o w e n e e d t o
* make s u r e t h a t i n t h i s c a s e , w e a l s o c l e a r P A C A _ I R Q _ H A R D _ D I S
* or t h a t b i t c a n g e t o u t o f s y n c a n d b a d t h i n g s w i l l h a p p e n
* /
2017-06-29 23:19:19 +05:30
.Lrestore_irq_off :
2012-05-10 16:12:38 +00:00
ld r3 ,_ M S R ( r1 )
lbz r7 ,P A C A I R Q H A P P E N E D ( r13 )
andi. r0 ,r3 ,M S R _ E E
beq 1 f
rlwinm r7 ,r7 ,0 ,~ P A C A _ I R Q _ H A R D _ D I S
stb r7 ,P A C A I R Q H A P P E N E D ( r13 )
2017-11-17 02:00:50 +10:00
1 :
2017-12-20 09:25:54 +05:30
# if d e f i n e d ( C O N F I G _ P P C _ I R Q _ S O F T _ M A S K _ D E B U G ) & & d e f i n e d ( C O N F I G _ B U G )
2017-11-17 02:00:50 +10:00
/* The interrupt should not have soft enabled. */
2017-12-20 09:25:50 +05:30
lbz r7 ,P A C A I R Q S O F T M A S K ( r13 )
1 : tdeqi r7 ,I R Q S _ E N A B L E D
2017-11-17 02:00:50 +10:00
EMIT_ B U G _ E N T R Y 1 b ,_ _ F I L E _ _ ,_ _ L I N E _ _ ,B U G F L A G _ W A R N I N G
# endif
2017-06-29 23:19:19 +05:30
b . L d o _ r e s t o r e
2012-05-10 16:12:38 +00:00
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ *
* Something d i d h a p p e n , c h e c k i f a r e - e m i t i s n e e d e d
* ( this a l s o c l e a r s p a c a - > i r q _ h a p p e n e d )
* /
2017-06-29 23:19:19 +05:30
.Lrestore_check_irq_replay :
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ * XXX : We c o u l d i m p l e m e n t a f a s t p a t h h e r e w h e r e w e c h e c k
* for i r q _ h a p p e n e d b e i n g j u s t 0 x01 , i n w h i c h c a s e w e c a n
* clear i t a n d r e t u r n . T h a t m e a n s t h a t w e w o u l d p o t e n t i a l l y
* miss a d e c r e m e n t e r h a v i n g w r a p p e d a l l t h e w a y a r o u n d .
*
* Still, t h i s m i g h t b e u s e f u l f o r t h i n g s l i k e h a s h _ p a g e
* /
2014-02-04 16:04:35 +11:00
bl _ _ c h e c k _ i r q _ r e p l a y
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
cmpwi c r0 ,r3 ,0
2017-06-29 23:19:19 +05:30
beq . L r e s t o r e _ n o _ r e p l a y
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ *
* We n e e d t o r e - e m i t a n i n t e r r u p t . W e d o s o b y r e - u s i n g o u r
* existing e x c e p t i o n f r a m e . W e f i r s t c h a n g e t h e t r a p v a l u e ,
* but w e n e e d t o e n s u r e w e p r e s e r v e t h e l o w n i b b l e o f i t
* /
ld r4 ,_ T R A P ( r1 )
clrldi r4 ,r4 ,6 0
or r4 ,r4 ,r3
std r4 ,_ T R A P ( r1 )
2018-06-03 22:24:32 +10:00
/ *
* PACA_ I R Q _ H A R D _ D I S w o n ' t a l w a y s b e s e t h e r e , s o s e t i t n o w
* to r e c o n c i l e t h e I R Q s t a t e . T r a c i n g i s a l r e a d y a c c o u n t e d f o r .
* /
lbz r4 ,P A C A I R Q H A P P E N E D ( r13 )
ori r4 ,r4 ,P A C A _ I R Q _ H A R D _ D I S
stb r4 ,P A C A I R Q H A P P E N E D ( r13 )
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
/ *
* Then f i n d t h e r i g h t h a n d l e r a n d c a l l i t . I n t e r r u p t s a r e
* still s o f t - d i s a b l e d a n d w e k e e p t h e m t h a t w a y .
* /
cmpwi c r0 ,r3 ,0 x50 0
bne 1 f
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D ;
2014-02-04 16:04:35 +11:00
bl d o _ I R Q
b r e t _ f r o m _ e x c e p t
2017-12-20 09:25:53 +05:30
1 : cmpwi c r0 ,r3 ,0 x f00
bne 1 f
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D ;
bl p e r f o r m a n c e _ m o n i t o r _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
2014-07-29 18:40:01 +05:30
1 : cmpwi c r0 ,r3 ,0 x e 6 0
bne 1 f
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D ;
bl h a n d l e _ h m i _ e x c e p t i o n
b r e t _ f r o m _ e x c e p t
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
1 : cmpwi c r0 ,r3 ,0 x90 0
bne 1 f
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D ;
2014-02-04 16:04:35 +11:00
bl t i m e r _ i n t e r r u p t
b r e t _ f r o m _ e x c e p t
2012-11-14 18:49:48 +00:00
# ifdef C O N F I G _ P P C _ D O O R B E L L
1 :
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
# ifdef C O N F I G _ P P C _ B O O K 3 E
2012-11-14 18:49:48 +00:00
cmpwi c r0 ,r3 ,0 x28 0
# else
2017-08-12 02:39:03 +10:00
cmpwi c r0 ,r3 ,0 x a00
2012-11-14 18:49:48 +00:00
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
bne 1 f
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D ;
2014-02-04 16:04:35 +11:00
bl d o o r b e l l _ e x c e p t i o n
2012-11-14 18:49:48 +00:00
# endif / * C O N F I G _ P P C _ D O O R B E L L * /
2014-02-04 16:04:35 +11:00
1 : b r e t _ f r o m _ e x c e p t / * W h a t e l s e t o d o h e r e ? * /
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 18:27:59 +11:00
2017-06-29 23:19:19 +05:30
.Lunrecov_restore :
2005-10-10 22:36:14 +10:00
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
2014-02-04 16:04:35 +11:00
bl u n r e c o v e r a b l e _ e x c e p t i o n
2017-06-29 23:19:19 +05:30
b . L u n r e c o v _ r e s t o r e
_ ASM_ N O K P R O B E _ S Y M B O L ( r e t _ f r o m _ e x c e p t ) ;
_ ASM_ N O K P R O B E _ S Y M B O L ( r e t _ f r o m _ e x c e p t _ l i t e ) ;
_ ASM_ N O K P R O B E _ S Y M B O L ( r e s u m e _ k e r n e l ) ;
_ ASM_ N O K P R O B E _ S Y M B O L ( f a s t _ e x c _ r e t u r n _ i r q ) ;
_ ASM_ N O K P R O B E _ S Y M B O L ( r e s t o r e ) ;
_ ASM_ N O K P R O B E _ S Y M B O L ( f a s t _ e x c e p t i o n _ r e t u r n ) ;
2005-10-10 22:36:14 +10:00
# ifdef C O N F I G _ P P C _ R T A S
/ *
* On C H R P , t h e R u n - T i m e A b s t r a c t i o n S e r v i c e s ( R T A S ) h a v e t o b e
* called w i t h t h e M M U o f f .
*
* In a d d i t i o n , w e n e e d t o b e i n 3 2 b m o d e , a t l e a s t f o r n o w .
*
* Note : r3 i s a n i n p u t p a r a m e t e r t o r t a s , s o d o n ' t t r a s h i t . . .
* /
_ GLOBAL( e n t e r _ r t a s )
mflr r0
std r0 ,1 6 ( r1 )
2018-10-12 13:14:06 +10:30
stdu r1 ,- S W I T C H _ F R A M E _ S I Z E ( r1 ) / * S a v e S P a n d c r e a t e s t a c k s p a c e . * /
2005-10-10 22:36:14 +10:00
/ * Because R T A S i s r u n n i n g i n 3 2 b m o d e , i t c l o b b e r s t h e h i g h o r d e r h a l f
* of a l l r e g i s t e r s t h a t i t s a v e s . W e t h e r e f o r e s a v e t h o s e r e g i s t e r s
* RTAS m i g h t t o u c h t o t h e s t a c k . ( r0 , r3 - r13 a r e c a l l e r s a v e d )
* /
SAVE_ G P R ( 2 , r1 ) / * S a v e t h e T O C * /
SAVE_ G P R ( 1 3 , r1 ) / * S a v e p a c a * /
SAVE_ 8 G P R S ( 1 4 , r1 ) / * S a v e t h e n o n - v o l a t i l e s * /
SAVE_ 1 0 G P R S ( 2 2 , r1 ) / * d i t t o * /
mfcr r4
std r4 ,_ C C R ( r1 )
mfctr r5
std r5 ,_ C T R ( r1 )
mfspr r6 ,S P R N _ X E R
std r6 ,_ X E R ( r1 )
mfdar r7
std r7 ,_ D A R ( r1 )
mfdsisr r8
std r8 ,_ D S I S R ( r1 )
2006-03-27 15:20:00 -08:00
/ * Temporary w o r k a r o u n d t o c l e a r C R u n t i l R T A S c a n b e m o d i f i e d t o
* ignore a l l b i t s .
* /
li r0 ,0
mtcr r0
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
# ifdef C O N F I G _ B U G
2005-10-10 22:36:14 +10:00
/ * There i s n o w a y i t i s a c c e p t a b l e t o g e t h e r e w i t h i n t e r r u p t s e n a b l e d ,
* check i t w i t h t h e a s m e q u i v a l e n t o f W A R N _ O N
* /
2017-12-20 09:25:50 +05:30
lbz r0 ,P A C A I R Q S O F T M A S K ( r13 )
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
1 : tdeqi r0 ,I R Q S _ E N A B L E D
2007-01-01 18:45:34 +00:00
EMIT_ B U G _ E N T R Y 1 b ,_ _ F I L E _ _ ,_ _ L I N E _ _ ,B U G F L A G _ W A R N I N G
# endif
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 09:25:49 +05:30
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 16:47:49 +10:00
/* Hard-disable interrupts */
mfmsr r6
rldicl r7 ,r6 ,4 8 ,1
rotldi r7 ,r7 ,1 6
mtmsrd r7 ,1
2005-10-10 22:36:14 +10:00
/ * Unfortunately, t h e s t a c k p o i n t e r a n d t h e M S R a r e a l s o c l o b b e r e d ,
* so t h e y a r e s a v e d i n t h e P A C A w h i c h a l l o w s u s t o r e s t o r e
* our o r i g i n a l s t a t e a f t e r R T A S r e t u r n s .
* /
std r1 ,P A C A R 1 ( r13 )
std r6 ,P A C A S A V E D M S R ( r13 )
/* Setup our real return addr */
2014-02-04 16:04:52 +11:00
LOAD_ R E G _ A D D R ( r4 ,r t a s _ r e t u r n _ l o c )
2006-01-13 14:56:25 +11:00
clrldi r4 ,r4 ,2 / * c o n v e r t t o r e a l m o d e a d d r e s s * /
2005-10-10 22:36:14 +10:00
mtlr r4
li r0 ,0
ori r0 ,r0 ,M S R _ E E | M S R _ S E | M S R _ B E | M S R _ R I
andc r0 ,r6 ,r0
li r9 ,1
rldicr r9 ,r9 ,M S R _ S F _ L G ,( 6 3 - M S R _ S F _ L G )
2013-09-23 12:04:45 +10:00
ori r9 ,r9 ,M S R _ I R | M S R _ D R | M S R _ F E 0 | M S R _ F E 1 | M S R _ F P | M S R _ R I | M S R _ L E
2005-10-10 22:36:14 +10:00
andc r6 ,r0 ,r9
2017-06-29 23:19:20 +05:30
__enter_rtas :
2005-10-10 22:36:14 +10:00
sync / * d i s a b l e i n t e r r u p t s s o S R R 0 / 1 * /
mtmsrd r0 / * d o n ' t g e t t r a s h e d * /
2006-01-13 14:56:25 +11:00
LOAD_ R E G _ A D D R ( r4 , r t a s )
2005-10-10 22:36:14 +10:00
ld r5 ,R T A S E N T R Y ( r4 ) / * g e t t h e r t a s - > e n t r y v a l u e * /
ld r4 ,R T A S B A S E ( r4 ) / * g e t t h e r t a s - > b a s e v a l u e * /
mtspr S P R N _ S R R 0 ,r5
mtspr S P R N _ S R R 1 ,r6
2018-01-10 03:07:15 +11:00
RFI_ T O _ K E R N E L
2005-10-10 22:36:14 +10:00
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
2014-02-04 16:04:52 +11:00
rtas_return_loc :
2013-09-23 12:04:45 +10:00
FIXUP_ E N D I A N
2017-12-22 21:17:10 +10:00
/ *
* Clear R I a n d s e t S F b e f o r e a n y t h i n g .
* /
mfmsr r6
li r0 ,M S R _ R I
andc r6 ,r6 ,r0
sldi r0 ,r0 ,( M S R _ S F _ L G - M S R _ R I _ L G )
or r6 ,r6 ,r0
sync
mtmsrd r6
2005-10-10 22:36:14 +10:00
/* relocation is off at this point */
2011-01-20 17:50:21 +11:00
GET_ P A C A ( r4 )
2006-01-13 14:56:25 +11:00
clrldi r4 ,r4 ,2 / * c o n v e r t t o r e a l m o d e a d d r e s s * /
2005-10-10 22:36:14 +10:00
2008-08-30 11:41:12 +10:00
bcl 2 0 ,3 1 ,$ + 4
0 : mflr r3
2014-02-04 16:04:52 +11:00
ld r3 ,( 1 f - 0 b ) ( r3 ) / * g e t & r t a s _ r e s t o r e _ r e g s * /
2008-08-30 11:41:12 +10:00
2005-10-10 22:36:14 +10:00
ld r1 ,P A C A R 1 ( r4 ) / * R e s t o r e o u r S P * /
ld r4 ,P A C A S A V E D M S R ( r4 ) / * R e s t o r e o u r M S R * /
mtspr S P R N _ S R R 0 ,r3
mtspr S P R N _ S R R 1 ,r4
2018-01-10 03:07:15 +11:00
RFI_ T O _ K E R N E L
2005-10-10 22:36:14 +10:00
b . / * p r e v e n t s p e c u l a t i v e e x e c u t i o n * /
2017-06-29 23:19:20 +05:30
_ ASM_ N O K P R O B E _ S Y M B O L ( _ _ e n t e r _ r t a s )
_ ASM_ N O K P R O B E _ S Y M B O L ( r t a s _ r e t u r n _ l o c )
2005-10-10 22:36:14 +10:00
2008-08-30 11:41:12 +10:00
.align 3
2017-03-09 16:42:12 +11:00
1 : .8byte r t a s _ r e s t o r e _ r e g s
2008-08-30 11:41:12 +10:00
2014-02-04 16:04:52 +11:00
rtas_restore_regs :
2005-10-10 22:36:14 +10:00
/* relocation is on at this point */
REST_ G P R ( 2 , r1 ) / * R e s t o r e t h e T O C * /
REST_ G P R ( 1 3 , r1 ) / * R e s t o r e p a c a * /
REST_ 8 G P R S ( 1 4 , r1 ) / * R e s t o r e t h e n o n - v o l a t i l e s * /
REST_ 1 0 G P R S ( 2 2 , r1 ) / * d i t t o * /
2011-01-20 17:50:21 +11:00
GET_ P A C A ( r13 )
2005-10-10 22:36:14 +10:00
ld r4 ,_ C C R ( r1 )
mtcr r4
ld r5 ,_ C T R ( r1 )
mtctr r5
ld r6 ,_ X E R ( r1 )
mtspr S P R N _ X E R ,r6
ld r7 ,_ D A R ( r1 )
mtdar r7
ld r8 ,_ D S I S R ( r1 )
mtdsisr r8
2018-10-12 13:14:06 +10:30
addi r1 ,r1 ,S W I T C H _ F R A M E _ S I Z E / * U n s t a c k o u r f r a m e * /
2005-10-10 22:36:14 +10:00
ld r0 ,1 6 ( r1 ) / * g e t r e t u r n a d d r e s s * /
mtlr r0
blr / * r e t u r n t o c a l l e r * /
# endif / * C O N F I G _ P P C _ R T A S * /
_ GLOBAL( e n t e r _ p r o m )
mflr r0
std r0 ,1 6 ( r1 )
2018-10-12 13:14:06 +10:30
stdu r1 ,- S W I T C H _ F R A M E _ S I Z E ( r1 ) / * S a v e S P a n d c r e a t e s t a c k s p a c e * /
2005-10-10 22:36:14 +10:00
/ * Because P R O M i s r u n n i n g i n 3 2 b m o d e , i t c l o b b e r s t h e h i g h o r d e r h a l f
* of a l l r e g i s t e r s t h a t i t s a v e s . W e t h e r e f o r e s a v e t h o s e r e g i s t e r s
* PROM m i g h t t o u c h t o t h e s t a c k . ( r0 , r3 - r13 a r e c a l l e r s a v e d )
* /
2009-07-23 23:15:07 +00:00
SAVE_ G P R ( 2 , r1 )
2005-10-10 22:36:14 +10:00
SAVE_ G P R ( 1 3 , r1 )
SAVE_ 8 G P R S ( 1 4 , r1 )
SAVE_ 1 0 G P R S ( 2 2 , r1 )
2009-07-23 23:15:07 +00:00
mfcr r10
2005-10-10 22:36:14 +10:00
mfmsr r11
2009-07-23 23:15:07 +00:00
std r10 ,_ C C R ( r1 )
2005-10-10 22:36:14 +10:00
std r11 ,_ M S R ( r1 )
2013-09-23 12:04:45 +10:00
/* Put PROM address in SRR0 */
mtsrr0 r4
/* Setup our trampoline return addr in LR */
bcl 2 0 ,3 1 ,$ + 4
0 : mflr r4
addi r4 ,r4 ,( 1 f - 0 b )
mtlr r4
2005-10-10 22:36:14 +10:00
2013-09-23 12:04:45 +10:00
/ * Prepare a 3 2 - b i t m o d e b i g e n d i a n M S R
2005-10-10 22:36:14 +10:00
* /
2009-07-23 23:15:59 +00:00
# ifdef C O N F I G _ P P C _ B O O K 3 E
rlwinm r11 ,r11 ,0 ,1 ,3 1
2013-09-23 12:04:45 +10:00
mtsrr1 r11
rfi
2009-07-23 23:15:59 +00:00
# else / * C O N F I G _ P P C _ B O O K 3 E * /
2013-09-23 12:04:45 +10:00
LOAD_ R E G _ I M M E D I A T E ( r12 , M S R _ S F | M S R _ I S F | M S R _ L E )
andc r11 ,r11 ,r12
mtsrr1 r11
2018-01-10 03:07:15 +11:00
RFI_ T O _ K E R N E L
2009-07-23 23:15:59 +00:00
# endif / * C O N F I G _ P P C _ B O O K 3 E * /
2005-10-10 22:36:14 +10:00
2013-09-23 12:04:45 +10:00
1 : /* Return from OF */
FIXUP_ E N D I A N
2005-10-10 22:36:14 +10:00
/ * Just m a k e s u r e t h a t r1 t o p 3 2 b i t s d i d n ' t g e t
* corrupt b y O F
* /
rldicl r1 ,r1 ,0 ,3 2
/* Restore the MSR (back to 64 bits) */
ld r0 ,_ M S R ( r1 )
2009-07-23 23:15:07 +00:00
MTMSRD( r0 )
2005-10-10 22:36:14 +10:00
isync
/* Restore other registers */
REST_ G P R ( 2 , r1 )
REST_ G P R ( 1 3 , r1 )
REST_ 8 G P R S ( 1 4 , r1 )
REST_ 1 0 G P R S ( 2 2 , r1 )
ld r4 ,_ C C R ( r1 )
mtcr r4
2018-10-12 13:14:06 +10:30
addi r1 ,r1 ,S W I T C H _ F R A M E _ S I Z E
2005-10-10 22:36:14 +10:00
ld r0 ,1 6 ( r1 )
mtlr r0
blr
