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/ *
* ARC C P U s t a r t u p C o d e
*
* Copyright ( C ) 2 0 0 4 , 2 0 0 7 - 2 0 1 0 , 2 0 1 1 - 2 0 1 2 S y n o p s y s , I n c . ( w w w . s y n o p s y s . c o m )
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
*
* Vineetg : Dec 2 0 0 7
* - Check i f w e a r e r u n n i n g o n S i m u l a t o r o r o n r e a l h a r d w a r e
* to s k i p c e r t a i n t h i n g s d u r i n g b o o t o n s i m u l a t o r
* /
# include < a s m / a s m - o f f s e t s . h >
# include < a s m / e n t r y . h >
# include < l i n u x / l i n k a g e . h >
# include < a s m / a r c r e g s . h >
.cpu A7
.section .init .text , " ax" ,@progbits
.type @function
.globl stext
stext :
;-------------------------------------------------------------------
; Don't clobber r0-r4 yet. It might have bootloader provided info
;-------------------------------------------------------------------
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
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# ifdef C O N F I G _ S M P
; Only Boot (Master) proceeds. Others wait in platform dependent way
; IDENTITY Reg [ 3 2 1 0 ]
; (cpu-id) ^^^ => Zero for UP ARC700
; => #Core-ID if SMP (Master 0)
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; Note that non-boot CPUs might not land here if halt-on-reset and
; instead breath life from @first_lines_of_secondary, but we still
; need to make sure only boot cpu takes this path.
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GET_ C P U _ I D r5
cmp r5 , 0
jnz a r c _ p l a t f o r m _ s m p _ w a i t _ t o _ b o o t
# endif
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; Clear BSS before updating any globals
; XXX: use ZOL here
mov r5 , _ _ b s s _ s t a r t
mov r6 , _ _ b s s _ s t o p
1 :
st. a b 0 , [ r5 ,4 ]
brlt r5 , r6 , 1 b
# ifdef C O N F I G _ C M D L I N E _ U B O O T
; support for bootloader provided cmdline
; If cmdline passed by u-boot, then
; r0 = 1 (because ATAGS parsing, now retired, used to use 0)
; r1 = magic number (board identity)
; r2 = addr of cmdline string (somewhere in memory/flash)
brne r0 , 1 , . L o t h e r _ b o o t u p _ c h o r e s ; u-boot didn't pass cmdline
breq r2 , 0 , . L o t h e r _ b o o t u p _ c h o r e s ; or cmdline is NULL
mov r5 , @command_line
1 :
ldb. a b r6 , [ r2 , 1 ]
breq r6 , 0 , . L o t h e r _ b o o t u p _ c h o r e s
b. d 1 b
stb. a b r6 , [ r5 , 1 ]
# endif
.Lother_bootup_chores :
; Identify if running on ISS vs Silicon
; IDENTITY Reg [ 3 2 1 0 ]
; (chip-id) ^^^^^ ==> 0xffff for ISS
lr r0 , [ i d e n t i t y ]
lsr r3 , r0 , 1 6
cmp r3 , 0 x f f f f
mov. z r4 , 0
mov. n z r4 , 1
st r4 , [ @running_on_hw]
; setup "current" tsk and optionally cache it in dedicated r25
mov r9 , @init_task
SET_ C U R R _ T A S K _ O N _ C P U r9 , r0 ; r9 = tsk, r0 = scratch
; setup stack (fp, sp)
mov f p , 0
; tsk->thread_info is really a PAGE, whose bottom hoists stack
GET_ T S K _ S T A C K _ B A S E r9 , s p ; r9 = tsk, sp = stack base(output)
j s t a r t _ k e r n e l ; "C" entry point
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# ifdef C O N F I G _ S M P
;----------------------------------------------------------------
; First lines of code run by secondary before jumping to 'C'
;----------------------------------------------------------------
.section .init .text , " ax" ,@progbits
.type _ l i n e s _ o f _ s e c o n d a r y , @function
.globl first_lines_of_secondary
first_lines_of_secondary :
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
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; setup per-cpu idle task as "current" on this CPU
ld r0 , [ @secondary_idle_tsk]
SET_ C U R R _ T A S K _ O N _ C P U r0 , r1
; setup stack (fp, sp)
mov f p , 0
; set it's stack base to tsk->thread_info bottom
GET_ T S K _ S T A C K _ B A S E r0 , s p
j s t a r t _ k e r n e l _ s e c o n d a r y
# endif
