2019-05-19 15:07:45 +03:00
# SPDX-License-Identifier: GPL-2.0-only
2006-05-24 04:18:44 +04:00
#
# DMA engine configuration
#
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menuconfig DMADEVICES
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bool "DMA Engine support"
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depends on HAS_DMA
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help
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DMA engines can do asynchronous data transfers without
involving the host CPU. Currently, this framework can be
used to offload memory copies in the network stack and
2008-06-27 12:21:11 +04:00
RAID operations in the MD driver. This menu only presents
DMA Device drivers supported by the configured arch, it may
be empty in some cases.
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2010-02-10 00:34:54 +03:00
config DMADEVICES_DEBUG
bool "DMA Engine debugging"
depends on DMADEVICES != n
help
This is an option for use by developers; most people should
say N here. This enables DMA engine core and driver debugging.
config DMADEVICES_VDEBUG
bool "DMA Engine verbose debugging"
depends on DMADEVICES_DEBUG != n
help
This is an option for use by developers; most people should
say N here. This enables deeper (more verbose) debugging of
the DMA engine core and drivers.
2007-10-16 12:27:42 +04:00
if DMADEVICES
comment "DMA Devices"
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#core
config ASYNC_TX_ENABLE_CHANNEL_SWITCH
bool
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config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
bool
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config DMA_ENGINE
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bool
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config DMA_VIRTUAL_CHANNELS
tristate
config DMA_ACPI
def_bool y
depends on ACPI
config DMA_OF
def_bool y
depends on OF
select DMA_ENGINE
#devices
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config ALTERA_MSGDMA
tristate "Altera / Intel mSGDMA Engine"
select DMA_ENGINE
help
Enable support for Altera / Intel mSGDMA controller.
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config AMBA_PL08X
bool "ARM PrimeCell PL080 or PL081 support"
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depends on ARM_AMBA
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Say yes if your platform has a PL08x DMAC device which can
provide DMA engine support. This includes the original ARM
PL080 and PL081, Samsungs PL080 derivative and Faraday
Technology's FTDMAC020 PL080 derivative.
2010-09-28 17:57:37 +04:00
2015-08-24 11:13:14 +03:00
config AMCC_PPC440SPE_ADMA
tristate "AMCC PPC440SPe ADMA support"
depends on 440SPe || 440SP
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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help
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Enable support for the AMCC PPC440SPe RAID engines.
2007-10-16 12:27:42 +04:00
2009-07-03 21:24:33 +04:00
config AT_HDMAC
tristate "Atmel AHB DMA support"
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depends on ARCH_AT91
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select DMA_ENGINE
help
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Support the Atmel AHB DMA controller.
2007-10-16 12:27:42 +04:00
2014-10-22 19:22:18 +04:00
config AT_XDMAC
tristate "Atmel XDMA support"
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depends on ARCH_AT91
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select DMA_ENGINE
help
Support the Atmel XDMA controller.
2007-10-16 12:27:42 +04:00
2015-08-24 11:13:14 +03:00
config AXI_DMAC
tristate "Analog Devices AXI-DMAC DMA support"
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depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_SOCFPGA || COMPILE_TEST
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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select REGMAP_MMIO
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help
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Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
controller is often used in Analog Device's reference designs for FPGA
platforms.
2006-05-24 04:18:44 +04:00
2017-05-15 08:04:54 +03:00
config BCM_SBA_RAID
tristate "Broadcom SBA RAID engine support"
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depends on ARM64 || COMPILE_TEST
depends on MAILBOX && RAID6_PQ
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select DMA_ENGINE
select DMA_ENGINE_RAID
select ASYNC_TX_DISABLE_XOR_VAL_DMA
select ASYNC_TX_DISABLE_PQ_VAL_DMA
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default m if ARCH_BCM_IPROC
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help
Enable support for Broadcom SBA RAID Engine. The SBA RAID
engine is available on most of the Broadcom iProc SoCs. It
has the capability to offload memcpy, xor and pq computation
for raid5/6.
2015-08-24 11:13:14 +03:00
config COH901318
bool "ST-Ericsson COH901318 DMA support"
select DMA_ENGINE
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depends on ARCH_U300 || COMPILE_TEST
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help
Enable support for ST-Ericsson COH 901 318 DMA.
config DMA_BCM2835
tristate "BCM2835 DMA engine support"
depends on ARCH_BCM2835
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
config DMA_JZ4780
tristate "JZ4780 DMA support"
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depends on MIPS || COMPILE_TEST
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select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
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This selects support for the DMA controller in Ingenic JZ4780 SoCs.
If you have a board based on such a SoC and wish to use DMA for
devices which can use the DMA controller, say Y or M here.
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config DMA_SA11X0
tristate "SA-11x0 DMA support"
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depends on ARCH_SA1100 || COMPILE_TEST
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support the DMA engine found on Intel StrongARM SA-1100 and
SA-1110 SoCs. This DMA engine can only be used with on-chip
devices.
2009-07-03 21:24:33 +04:00
2015-08-24 11:13:14 +03:00
config DMA_SUN4I
tristate "Allwinner A10 DMA SoCs support"
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depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for the DMA controller present in the sun4i,
sun5i and sun7i Allwinner ARM SoCs.
config DMA_SUN6I
tristate "Allwinner A31 SoCs DMA support"
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depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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depends on RESET_CONTROLLER
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Support for the DMA engine first found in Allwinner A31 SoCs.
2018-03-06 14:46:14 +03:00
config DW_AXI_DMAC
tristate "Synopsys DesignWare AXI DMA support"
depends on OF || COMPILE_TEST
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Enable support for Synopsys DesignWare AXI DMA controller.
NOTE: This driver wasn't tested on 64 bit platform because
of lack 64 bit platform with Synopsys DW AXI DMAC.
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config EP93XX_DMA
bool "Cirrus Logic EP93xx DMA support"
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depends on ARCH_EP93XX || COMPILE_TEST
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select DMA_ENGINE
help
Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
2014-10-22 19:22:18 +04:00
2008-03-01 17:42:48 +03:00
config FSL_DMA
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tristate "Freescale Elo series DMA support"
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depends on FSL_SOC
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select DMA_ENGINE
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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---help---
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Enable support for the Freescale Elo series DMA controllers.
The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
some Txxx and Bxxx parts.
2008-03-01 17:42:48 +03:00
2015-08-24 11:13:14 +03:00
config FSL_EDMA
tristate "Freescale eDMA engine support"
depends on OF
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Support the Freescale eDMA engine with programmable channel
multiplexing capability for DMA request sources(slot).
This module can be found on Freescale Vybrid and LS-1 SoCs.
2018-10-30 05:36:00 +03:00
config FSL_QDMA
tristate "NXP Layerscape qDMA engine support"
depends on ARM || ARM64
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
select DMA_ENGINE_RAID
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
help
Support the NXP Layerscape qDMA engine with command queue and legacy mode.
Channel virtualization is supported through enqueuing of DMA jobs to,
or dequeuing DMA jobs from, different work queues.
This module can be found on NXP Layerscape SoCs.
The qdma driver only work on SoCs with a DPAA hardware block.
2015-03-03 09:26:22 +03:00
config FSL_RAID
tristate "Freescale RAID engine Support"
depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
select DMA_ENGINE
select DMA_ENGINE_RAID
---help---
Enable support for Freescale RAID Engine. RAID Engine is
available on some QorIQ SoCs (like P5020/P5040). It has
the capability to offload memcpy, xor and pq computation
for raid5/6.
2015-08-24 11:13:14 +03:00
config IMG_MDC_DMA
tristate "IMG MDC support"
depends on MIPS || COMPILE_TEST
depends on MFD_SYSCON
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
help
Enable support for the IMG multi-threaded DMA controller (MDC).
2012-10-12 19:52:45 +04:00
2015-08-24 11:13:14 +03:00
config IMX_DMA
tristate "i.MX DMA support"
2011-08-24 10:41:09 +04:00
depends on ARCH_MXC
2008-07-08 22:58:36 +04:00
select DMA_ENGINE
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
help
2015-08-24 11:13:14 +03:00
Support the i.MX DMA engine. This engine is integrated into
Freescale i.MX1/21/27 chips.
2008-07-08 22:58:36 +04:00
2015-08-24 11:13:14 +03:00
config IMX_SDMA
tristate "i.MX SDMA support"
2011-08-24 10:41:09 +04:00
depends on ARCH_MXC
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
select DMA_ENGINE
2018-06-19 19:57:00 +03:00
select DMA_VIRTUAL_CHANNELS
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
help
2015-08-24 11:13:14 +03:00
Support the i.MX SDMA engine. This engine is integrated into
Freescale i.MX25/31/35/51/53/6 chips.
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
2015-09-21 19:48:45 +03:00
config INTEL_IDMA64
2015-09-04 21:10:18 +03:00
tristate "Intel integrated DMA 64-bit support"
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
help
2015-09-04 21:10:18 +03:00
Enable DMA support for Intel Low Power Subsystem such as found on
Intel Skylake PCH.
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 01:36:21 +03:00
2015-08-24 11:13:14 +03:00
config INTEL_IOATDMA
tristate "Intel I/OAT DMA support"
depends on PCI && X86_64
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 00:29:20 +03:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
select DMA_ENGINE_RAID
select DCA
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 00:29:20 +03:00
help
2015-08-24 11:13:14 +03:00
Enable support for the Intel(R) I/OAT DMA engine present
in recent Intel Xeon chipsets.
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 00:29:20 +03:00
2015-08-24 11:13:14 +03:00
Say Y here if you have such a chipset.
If unsure, say N.
config INTEL_IOP_ADMA
2019-08-09 19:33:18 +03:00
tristate "Intel IOP32x ADMA support"
2019-09-18 05:04:40 +03:00
depends on ARCH_IOP32X || COMPILE_TEST
2009-04-22 19:40:30 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
2009-04-22 19:40:30 +04:00
help
2015-08-24 11:13:14 +03:00
Enable support for the Intel(R) IOP Series RAID engines.
2009-04-22 19:40:30 +04:00
2015-08-24 11:13:14 +03:00
config INTEL_MIC_X100_DMA
tristate "Intel MIC X100 DMA Driver"
depends on 64BIT && X86 && INTEL_MIC_BUS
2012-06-06 09:25:27 +04:00
select DMA_ENGINE
help
2015-08-24 11:13:14 +03:00
This enables DMA support for the Intel Many Integrated Core
(MIC) family of PCIe form factor coprocessor X100 devices that
run a 64 bit Linux OS. This driver will be used by both MIC
host and card drivers.
2012-06-06 09:25:27 +04:00
2015-08-24 11:13:14 +03:00
If you are building host kernel with a MIC device or a card
kernel for a MIC device, then say M (recommended) or Y, else
say N. If unsure say N.
More information about the Intel MIC family as well as the Linux
OS and tools for MIC to use with this driver are available from
<http://software.intel.com/en-us/mic-developer>.
config K3_DMA
tristate "Hisilicon K3 DMA support"
2016-08-29 20:30:53 +03:00
depends on ARCH_HI3xxx || ARCH_HISI || COMPILE_TEST
2013-10-08 01:42:10 +04:00
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
2015-08-24 11:13:14 +03:00
Support the DMA engine for Hisilicon K3 platform
devices.
2013-10-08 01:42:10 +04:00
2015-08-24 11:13:14 +03:00
config LPC18XX_DMAMUX
bool "NXP LPC18xx/43xx DMA MUX for PL080"
depends on ARCH_LPC18XX || COMPILE_TEST
depends on OF && AMBA_PL08X
select MFD_SYSCON
help
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
2009-09-07 07:26:23 +04:00
2018-08-19 20:27:16 +03:00
config MCF_EDMA
tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
depends on M5441x || COMPILE_TEST
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Support the Freescale ColdFire eDMA engine, 64-channel
implementation that performs complex data transfers with
minimal intervention from a host processor.
This module can be found on Freescale ColdFire mcf5441x SoCs.
2015-08-24 11:13:14 +03:00
config MMP_PDMA
bool "MMP PDMA support"
2016-09-02 13:25:56 +03:00
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
2009-11-19 21:49:17 +03:00
select DMA_ENGINE
help
2015-08-24 11:13:14 +03:00
Support the MMP PDMA engine for PXA and MMP platform.
2009-11-19 21:49:17 +03:00
2015-08-24 11:13:14 +03:00
config MMP_TDMA
bool "MMP Two-Channel DMA support"
2016-09-02 13:27:09 +03:00
depends on ARCH_MMP || COMPILE_TEST
2010-03-30 17:33:42 +04:00
select DMA_ENGINE
2016-09-02 13:27:09 +03:00
select MMP_SRAM if ARCH_MMP
2016-10-07 00:59:53 +03:00
select GENERIC_ALLOCATOR
2010-03-30 17:33:42 +04:00
help
2015-08-24 11:13:14 +03:00
Support the MMP Two-Channel DMA engine.
This engine used for MMP Audio DMA and pxa910 SQU.
It needs sram driver under mach-mmp.
2010-03-30 17:33:42 +04:00
2015-08-24 11:13:14 +03:00
config MOXART_DMA
tristate "MOXART DMA support"
depends on ARCH_MOXART
2009-12-12 07:24:44 +03:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
select DMA_VIRTUAL_CHANNELS
2009-12-12 07:24:44 +03:00
help
2015-08-24 11:13:14 +03:00
Enable support for the MOXA ART SoC DMA controller.
Say Y here if you enabled MMP ADMA, otherwise say N.
2009-12-12 07:24:44 +03:00
2015-08-24 11:13:14 +03:00
config MPC512X_DMA
tristate "Freescale MPC512x built-in DMA engine support"
depends on PPC_MPC512x || PPC_MPC831x
2010-03-25 21:44:21 +03:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
---help---
Enable support for the Freescale MPC512x built-in DMA engine.
2010-03-25 21:44:21 +03:00
2015-08-24 11:13:14 +03:00
config MV_XOR
bool "Marvell XOR engine support"
2016-04-29 10:49:08 +03:00
depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
2011-10-28 06:22:39 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
select DMA_ENGINE_RAID
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
---help---
Enable support for the Marvell XOR engine.
2011-10-28 06:22:39 +04:00
2016-06-16 15:28:34 +03:00
config MV_XOR_V2
bool "Marvell XOR engine version 2 support "
depends on ARM64
select DMA_ENGINE
select DMA_ENGINE_RAID
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
select GENERIC_MSI_IRQ_DOMAIN
---help---
Enable support for the Marvell version 2 XOR engine.
This engine provides acceleration for copy, XOR and RAID6
operations, and is available on Marvell Armada 7K and 8K
platforms.
2015-08-24 11:13:14 +03:00
config MXS_DMA
bool "MXS DMA support"
2017-06-09 01:46:23 +03:00
depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST
2015-08-24 11:13:14 +03:00
select STMP_DEVICE
2011-10-28 06:22:39 +04:00
select DMA_ENGINE
help
2015-08-24 11:13:14 +03:00
Support the MXS DMA engine. This engine including APBH-DMA
2017-06-16 17:58:46 +03:00
and APBX-DMA is integrated into some Freescale chips.
2011-10-28 06:22:39 +04:00
2015-08-24 11:13:14 +03:00
config MX3_IPU
bool "MX3x Image Processing Unit support"
depends on ARCH_MXC
2012-08-23 05:09:34 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
default y
2012-08-23 05:09:34 +04:00
help
2015-08-24 11:13:14 +03:00
If you plan to use the Image Processing unit in the i.MX3x, say
Y here. If unsure, select Y.
2015-04-09 12:35:49 +03:00
2015-08-24 11:13:14 +03:00
config MX3_IPU_IRQS
int "Number of dynamically mapped interrupts for IPU"
depends on MX3_IPU
range 2 137
default 4
help
Out of 137 interrupt sources on i.MX31 IPU only very few are used.
To avoid bloating the irq_desc[] array we allocate a sufficient
number of IRQ slots and map them dynamically to specific sources.
2009-12-12 07:24:44 +03:00
2015-08-24 11:13:14 +03:00
config NBPFAXI_DMA
tristate "Renesas Type-AXI NBPF DMA support"
2010-05-24 07:28:19 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
depends on ARM || COMPILE_TEST
2010-05-24 07:28:19 +04:00
help
2015-08-24 11:13:14 +03:00
Support for "Type-AXI" NBPF DMA IPs from Renesas
2010-05-24 07:28:19 +04:00
2018-07-26 08:06:57 +03:00
config OWL_DMA
tristate "Actions Semi Owl SoCs DMA support"
depends on ARCH_ACTIONS
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Enable support for the Actions Semi Owl SoCs DMA controller.
2010-07-30 12:23:03 +04:00
config PCH_DMA
2011-11-17 11:14:23 +04:00
tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
2014-05-16 18:17:37 +04:00
depends on PCI && (X86_32 || COMPILE_TEST)
2010-07-30 12:23:03 +04:00
select DMA_ENGINE
help
2011-01-05 11:43:52 +03:00
Enable support for Intel EG20T PCH DMA engine.
2011-11-17 11:14:22 +04:00
This driver also can be used for LAPIS Semiconductor IOH(Input/
2011-11-17 11:14:23 +04:00
Output Hub), ML7213, ML7223 and ML7831.
ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
for MP(Media Phone) use and ML7831 IOH is for general purpose use.
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
2010-07-30 12:23:03 +04:00
2015-08-24 11:13:14 +03:00
config PL330_DMA
tristate "DMA API Driver for PL330"
2010-09-30 17:56:34 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
depends on ARM_AMBA
2010-09-30 17:56:34 +04:00
help
2015-08-24 11:13:14 +03:00
Select if your platform has one or more PL330 DMACs.
You need to provide platform specific settings via
platform_data for a dma-pl330 device.
2010-09-30 17:56:34 +04:00
2015-08-24 11:13:14 +03:00
config PXA_DMA
bool "PXA DMA support"
depends on (ARCH_MMP || ARCH_PXA)
2010-10-06 12:25:55 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
select DMA_VIRTUAL_CHANNELS
2010-10-06 12:25:55 +04:00
help
2015-08-24 11:13:14 +03:00
Support the DMA engine for PXA. It is also compatible with MMP PDMA
platform. The internal DMA IP of all PXA variants is supported, with
16 to 32 channels for peripheral to memory or memory to memory
transfers.
2010-10-06 12:25:55 +04:00
2015-08-24 11:13:14 +03:00
config SIRF_DMA
tristate "CSR SiRFprimaII/SiRFmarco DMA support"
depends on ARCH_SIRF
2011-02-26 19:47:42 +03:00
select DMA_ENGINE
help
2015-08-24 11:13:14 +03:00
Enable support for the CSR SiRFprimaII DMA engine.
2011-02-26 19:47:42 +03:00
2015-08-24 11:13:14 +03:00
config STE_DMA40
bool "ST-Ericsson DMA40 support"
depends on ARCH_U8500
2011-05-29 14:10:02 +04:00
select DMA_ENGINE
help
2015-08-24 11:13:14 +03:00
Support for ST-Ericsson DMA40 controller
2011-05-29 14:10:02 +04:00
2016-10-18 12:39:11 +03:00
config ST_FDMA
tristate "ST FDMA dmaengine support"
depends on ARCH_STI
2016-11-17 12:53:01 +03:00
depends on REMOTEPROC
2016-10-18 12:39:11 +03:00
select ST_SLIM_REMOTEPROC
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Enable support for ST FDMA controller.
It supports 16 independent DMA channels, accepts up to 32 DMA requests
Say Y here if you have such a chipset.
If unsure, say N.
2015-10-16 16:59:14 +03:00
config STM32_DMA
bool "STMicroelectronics STM32 DMA support"
2016-09-02 13:27:51 +03:00
depends on ARCH_STM32 || COMPILE_TEST
2015-10-16 16:59:14 +03:00
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Enable support for the on-chip DMA controller on STMicroelectronics
STM32 MCUs.
2016-12-13 16:40:44 +03:00
If you have a board based on such a MCU and wish to use DMA say Y
2015-10-16 16:59:14 +03:00
here.
2017-09-22 10:31:30 +03:00
config STM32_DMAMUX
bool "STMicroelectronics STM32 dma multiplexer support"
depends on STM32_DMA || COMPILE_TEST
help
Enable support for the on-chip DMA multiplexer on STMicroelectronics
STM32 MCUs.
If you have a board based on such a MCU and wish to use DMAMUX say Y
here.
2017-09-28 18:36:41 +03:00
config STM32_MDMA
bool "STMicroelectronics STM32 master dma support"
depends on ARCH_STM32 || COMPILE_TEST
2017-10-11 17:00:04 +03:00
depends on OF
2017-09-28 18:36:41 +03:00
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Enable support for the on-chip MDMA controller on STMicroelectronics
STM32 platforms.
If you have a board based on STM32 SoC and wish to use the master DMA
say Y here.
2017-10-24 08:47:50 +03:00
config SPRD_DMA
tristate "Spreadtrum DMA support"
depends on ARCH_SPRD || COMPILE_TEST
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Enable support for the on-chip DMA controller on Spreadtrum platform.
2015-08-24 11:13:14 +03:00
config S3C24XX_DMAC
2015-11-19 00:31:11 +03:00
bool "Samsung S3C24XX DMA support"
2016-09-02 13:30:41 +03:00
depends on ARCH_S3C24XX || COMPILE_TEST
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 01:44:07 +04:00
select DMA_ENGINE
2012-04-13 15:07:23 +04:00
select DMA_VIRTUAL_CHANNELS
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 01:44:07 +04:00
help
2015-08-24 11:13:14 +03:00
Support for the Samsung S3C24XX DMA controller driver. The
DMA controller is having multiple DMA channels which can be
configured for different peripherals like audio, UART, SPI.
The DMA controller can transfer data from memory to peripheral,
periphal to memory, periphal to periphal and memory to memory.
DMA: sa11x0: add SA-11x0 DMA driver
Add support for the SA-11x0 DMA driver, which replaces the private
API version in arch/arm/mach-sa1100/dma.c.
We model this as a set of virtual DMA channels, one for each request
signal, and assign the virtual DMA channel to a physical DMA channel
when there is work to be done. This allows DMA users to claim their
channels, and hold them while not in use, without affecting the
availability of the physical channels.
Another advantage over this approach, compared to the private version,
is that a channel can be reconfigured on the fly without having to
release and re-request it - which for the IrDA driver, allows us to
use DMA for SIR mode transmit without eating up three physical
channels. As IrDA is half-duplex, we actually only need one physical
channel, and this architecture allows us to achieve that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-10 01:44:07 +04:00
2015-08-24 11:13:14 +03:00
config TXX9_DMAC
tristate "Toshiba TXx9 SoC DMA support"
depends on MACH_TX49XX || MACH_TX39XX
2012-06-15 07:04:08 +04:00
select DMA_ENGINE
help
2015-08-24 11:13:14 +03:00
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
2012-06-15 07:04:08 +04:00
2015-08-24 11:13:14 +03:00
config TEGRA20_APB_DMA
bool "NVIDIA Tegra20 APB DMA support"
depends on ARCH_TEGRA
2012-04-13 15:10:24 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
help
Support for the NVIDIA Tegra20 APB DMA controller driver. The
DMA controller is having multiple DMA channel which can be
configured for different peripherals like audio, UART, SPI,
I2C etc which is in APB bus.
This DMA controller transfers data from memory to peripheral fifo
or vice versa. It does not support memory to memory data transfer.
2012-04-13 15:10:24 +04:00
2016-05-12 20:02:23 +03:00
config TEGRA210_ADMA
2016-10-23 01:25:10 +03:00
tristate "NVIDIA Tegra210 ADMA support"
2019-06-20 18:54:19 +03:00
depends on (ARCH_TEGRA_210_SOC || COMPILE_TEST)
2016-05-12 20:02:23 +03:00
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Support for the NVIDIA Tegra210 ADMA controller driver. The
DMA controller has multiple DMA channels and is used to service
various audio clients in the Tegra210 audio processing engine
(APE). This DMA controller transfers data from memory to
peripheral and vice versa. It does not support memory to
memory data transfer.
2015-08-24 11:13:14 +03:00
config TIMB_DMA
tristate "Timberdale FPGA DMA support"
2016-09-02 13:37:05 +03:00
depends on MFD_TIMBERDALE || COMPILE_TEST
2014-01-06 23:18:24 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
help
Enable support for the Timberdale FPGA DMA engine.
2014-01-06 23:18:24 +04:00
2018-10-11 19:41:03 +03:00
config UNIPHIER_MDMAC
tristate "UniPhier MIO DMAC"
depends on ARCH_UNIPHIER || COMPILE_TEST
depends on OF
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
Enable support for the MIO DMAC (Media I/O DMA controller) on the
UniPhier platform. This DMA controller is used as the external
DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.
2015-08-24 11:13:14 +03:00
config XGENE_DMA
tristate "APM X-Gene DMA support"
depends on ARCH_XGENE || COMPILE_TEST
2014-02-18 06:17:12 +04:00
select DMA_ENGINE
2015-08-24 11:13:14 +03:00
select DMA_ENGINE_RAID
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
2014-02-18 06:17:12 +04:00
help
2015-08-24 11:13:14 +03:00
Enable support for the APM X-Gene SoC DMA engine.
2014-01-17 12:46:05 +04:00
2016-06-24 08:21:25 +03:00
config XILINX_DMA
tristate "Xilinx AXI DMAS Engine"
2016-04-06 08:08:08 +03:00
depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
2014-04-23 18:53:26 +04:00
select DMA_ENGINE
help
Enable support for Xilinx AXI VDMA Soft IP.
2016-06-24 08:21:25 +03:00
AXI VDMA engine provides high-bandwidth direct memory access
2014-04-23 18:53:26 +04:00
between memory and AXI4-Stream video type target
peripherals including peripherals which support AXI4-
Stream Video Protocol. It has two stream interfaces/
channels, Memory Mapped to Stream (MM2S) and Stream to
Memory Mapped (S2MM) for the data transfers.
2016-06-24 08:21:25 +03:00
AXI CDMA engine provides high-bandwidth direct memory access
between a memory-mapped source address and a memory-mapped
destination address.
AXI DMA engine provides high-bandwidth one dimensional direct
memory access between memory and AXI4-Stream target peripherals.
2014-04-23 18:53:26 +04:00
2016-07-01 14:37:06 +03:00
config XILINX_ZYNQMP_DMA
tristate "Xilinx ZynqMP DMA Engine"
depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
select DMA_ENGINE
help
Enable support for Xilinx ZynqMP DMA controller.
2014-04-23 18:53:26 +04:00
2015-05-05 17:06:08 +03:00
config ZX_DMA
2016-12-15 17:03:35 +03:00
tristate "ZTE ZX DMA support"
2016-09-02 13:40:07 +03:00
depends on ARCH_ZX || COMPILE_TEST
2014-12-12 01:59:17 +03:00
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help
2016-12-15 17:03:35 +03:00
Support the DMA engine for ZTE ZX family platform devices.
2014-12-12 01:59:17 +03:00
2015-03-18 16:47:34 +03:00
2015-08-24 11:13:14 +03:00
# driver files
source "drivers/dma/bestcomm/Kconfig"
2006-05-24 04:18:44 +04:00
2018-03-15 10:40:36 +03:00
source "drivers/dma/mediatek/Kconfig"
2016-02-05 07:34:32 +03:00
source "drivers/dma/qcom/Kconfig"
2015-08-24 11:13:14 +03:00
source "drivers/dma/dw/Kconfig"
2012-04-13 15:07:23 +04:00
dmaengine: Add Synopsys eDMA IP core driver
Add Synopsys PCIe Endpoint eDMA IP core driver to kernel.
This IP is generally distributed with Synopsys PCIe Endpoint IP (depends
of the use and licensing agreement).
This core driver, initializes and configures the eDMA IP using vma-helpers
functions and dma-engine subsystem.
This driver can be compile as built-in or external module in kernel.
To enable this driver just select DW_EDMA option in kernel configuration,
however it requires and selects automatically DMA_ENGINE and
DMA_VIRTUAL_CHANNELS option too.
In order to transfer data from point A to B as fast as possible this IP
requires a dedicated memory space containing linked list of elements.
All elements of this linked list are continuous and each one describes a
data transfer (source and destination addresses, length and a control
variable).
For the sake of simplicity, lets assume a memory space for channel write
0 which allows about 42 elements.
+---------+
| Desc #0 |-+
+---------+ |
V
+----------+
| Chunk #0 |-+
| CB = 1 | | +----------+ +-----+ +-----------+ +-----+
+----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp |
| +----------+ +-----+ +-----------+ +-----+
V
+----------+
| Chunk #1 |-+
| CB = 0 | | +-----------+ +-----+ +-----------+ +-----+
+----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp |
| +-----------+ +-----+ +-----------+ +-----+
V
+----------+
| Chunk #2 |-+
| CB = 1 | | +-----------+ +-----+ +------------+ +-----+
+----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp |
| +-----------+ +-----+ +------------+ +-----+
V
+----------+
| Chunk #3 |-+
| CB = 0 | | +------------+ +-----+ +------------+ +-----+
+----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp |
+------------+ +-----+ +------------+ +-----+
Legend:
- Linked list, also know as Chunk
- Linked list element*, also know as Burst *CB*, also know as Change Bit,
it's a control bit (and typically is toggled) that allows to easily
identify and differentiate between the current linked list and the
previous or the next one.
- LLP, is a special element that indicates the end of the linked list
element stream also informs that the next CB should be toggle
On every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or
even Burst #129) is set some flags on their control variable (RIE and
LIE bits) that will trigger the send of "done" interruption.
On the interruptions callback, is decided whether to recycle the linked
list memory space by writing a new set of Bursts elements (if still
exists Chunks to transfer) or is considered completed (if there is no
Chunks available to transfer).
On scatter-gather transfer mode, the client will submit a scatter-gather
list of n (on this case 130) elements, that will be divide in multiple
Chunks, each Chunk will have (on this case 42) a limited number of
Bursts and after transferring all Bursts, an interrupt will be
triggered, which will allow to recycle the all linked list dedicated
memory again with the new information relative to the next Chunk and
respective Burst associated and repeat the whole cycle again.
On cyclic transfer mode, the client will submit a buffer pointer, length
of it and number of repetitions, in this case each burst will correspond
directly to each repetition.
Each Burst can describes a data transfer from point A(source) to point
B(destination) with a length that can be from 1 byte up to 4 GB. Since
dedicated the memory space where the linked list will reside is limited,
the whole n burst elements will be organized in several Chunks, that
will be used later to recycle the dedicated memory space to initiate a
new sequence of data transfers.
The whole transfer is considered has completed when it was transferred
all bursts.
Currently this IP has a set well-known register map, which includes
support for legacy and unroll modes. Legacy mode is version of this
register map that has multiplexer register that allows to switch
registers between all write and read channels and the unroll modes
repeats all write and read channels registers with an offset between
them. This register map is called v0.
The IP team is creating a new register map more suitable to the latest
PCIe features, that very likely will change the map register, which this
version will be called v1. As soon as this new version is released by
the IP team the support for this version in be included on this driver.
According to the logic, patches 1, 2 and 3 should be squashed into 1
unique patch, but for the sake of simplicity of review, it was divided
in this 3 patches files.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <rmk+kernel@armlinux.org.uk>
Cc: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-06-04 16:29:22 +03:00
source "drivers/dma/dw-edma/Kconfig"
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source "drivers/dma/hsu/Kconfig"
2013-04-09 15:05:43 +04:00
2015-08-24 11:13:14 +03:00
source "drivers/dma/sh/Kconfig"
2013-02-12 21:15:02 +04:00
2018-04-25 11:45:03 +03:00
source "drivers/dma/ti/Kconfig"
2015-08-24 11:13:14 +03:00
# clients
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comment "DMA Clients"
2007-10-16 12:27:42 +04:00
depends on DMA_ENGINE
2006-06-18 08:24:58 +04:00
2009-03-25 19:13:25 +03:00
config ASYNC_TX_DMA
bool "Async_tx: Offload support for the async_tx api"
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depends on DMA_ENGINE
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help
This allows the async_tx api to take advantage of offload engines for
memcpy, memset, xor, and raid6 p+q operations. If your platform has
a dma engine that can perform raid operations and you have enabled
MD_RAID456 say Y.
If unsure, say N.
2008-07-08 22:58:45 +04:00
config DMATEST
tristate "DMA Test client"
depends on DMA_ENGINE
2017-04-27 15:21:40 +03:00
select DMA_ENGINE_RAID
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help
Simple DMA test client. Say N unless you're debugging a
DMA Device driver.
2013-12-09 22:33:16 +04:00
config DMA_ENGINE_RAID
bool
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endif