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/ *
* Copyright 2 0 0 3 - 2 0 1 3 B r o a d c o m C o r p o r a t i o n .
* All R i g h t s R e s e r v e d .
*
* This s o f t w a r e i s a v a i l a b l e t o y o u u n d e r a c h o i c e o f o n e o f t w o
* licenses. Y o u m a y c h o o s e t o b e l i c e n s e d u n d e r t h e t e r m s o f t h e G N U
* General P u b l i c L i c e n s e ( G P L ) V e r s i o n 2 , a v a i l a b l e f r o m t h e f i l e
* COPYING i n t h e m a i n d i r e c t o r y o f t h i s s o u r c e t r e e , o r t h e B r o a d c o m
* license b e l o w :
*
* Redistribution a n d u s e i n s o u r c e a n d b i n a r y f o r m s , w i t h o r w i t h o u t
* modification, a r e p e r m i t t e d p r o v i d e d t h a t t h e f o l l o w i n g c o n d i t i o n s
* are m e t :
*
* 1 . Redistributions o f s o u r c e c o d e m u s t r e t a i n t h e a b o v e c o p y r i g h t
* notice, t h i s l i s t o f c o n d i t i o n s a n d t h e f o l l o w i n g d i s c l a i m e r .
* 2 . Redistributions i n b i n a r y f o r m m u s t r e p r o d u c e t h e a b o v e c o p y r i g h t
* notice, t h i s l i s t o f c o n d i t i o n s a n d t h e f o l l o w i n g d i s c l a i m e r i n
* the d o c u m e n t a t i o n a n d / o r o t h e r m a t e r i a l s p r o v i d e d w i t h t h e
* distribution.
*
* THIS S O F T W A R E I S P R O V I D E D B Y B R O A D C O M ` ` A S I S ' ' A N D A N Y E X P R E S S O R
* IMPLIED W A R R A N T I E S , I N C L U D I N G , B U T N O T L I M I T E D T O , T H E I M P L I E D
* WARRANTIES O F M E R C H A N T A B I L I T Y A N D F I T N E S S F O R A P A R T I C U L A R P U R P O S E
* ARE D I S C L A I M E D . I N N O E V E N T S H A L L B R O A D C O M O R C O N T R I B U T O R S B E L I A B L E
* FOR A N Y D I R E C T , I N D I R E C T , I N C I D E N T A L , S P E C I A L , E X E M P L A R Y , O R
* CONSEQUENTIAL D A M A G E S ( I N C L U D I N G , B U T N O T L I M I T E D T O , P R O C U R E M E N T O F
* SUBSTITUTE G O O D S O R S E R V I C E S ; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS I N T E R R U P T I O N ) H O W E V E R C A U S E D A N D O N A N Y T H E O R Y O F L I A B I L I T Y ,
* WHETHER I N C O N T R A C T , S T R I C T L I A B I L I T Y , O R T O R T ( I N C L U D I N G N E G L I G E N C E
* OR O T H E R W I S E ) A R I S I N G I N A N Y W A Y O U T O F T H E U S E O F T H I S S O F T W A R E , E V E N
* IF A D V I S E D O F T H E P O S S I B I L I T Y O F S U C H D A M A G E .
* /
# include < a s m / a s m . h >
# include < a s m / a s m - o f f s e t s . h >
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# include < a s m / c p u . h >
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# include < a s m / c a c h e o p s . h >
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# include < a s m / r e g d e f . h >
# include < a s m / m i p s r e g s . h >
# include < a s m / s t a c k f r a m e . h >
# include < a s m / a s m m a c r o . h >
# include < a s m / a d d r s p a c e . h >
# include < a s m / n e t l o g i c / c o m m o n . h >
# include < a s m / n e t l o g i c / x l p - h a l / i o m a p . h >
# include < a s m / n e t l o g i c / x l p - h a l / x l p . h >
# include < a s m / n e t l o g i c / x l p - h a l / s y s . h >
# include < a s m / n e t l o g i c / x l p - h a l / c p u c o n t r o l . h >
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# define S Y S _ C P U _ C O H E R E N T _ B A S E C K S E G 1 A D D R ( X L P _ D E F A U L T _ I O _ B A S E ) + \
XLP_ I O _ S Y S _ O F F S E T ( 0 ) + X L P _ I O _ P C I _ H D R S Z + \
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SYS_ C P U _ N O N C O H E R E N T _ M O D E * 4
/* Enable XLP features and workarounds in the LSU */
.macro xlp_config_lsu
li t 0 , L S U _ D E F E A T U R E
mfcr t 1 , t 0
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lui t 2 , 0 x40 8 0 / * E n a b l e U n a l i g n e d A c c e s s , L 2 H P E * /
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or t 1 , t 1 , t 2
mtcr t 1 , t 0
li t 0 , I C U _ D E F E A T U R E
mfcr t 1 , t 0
ori t 1 , 0 x10 0 0 / * E n a b l e I c a c h e p a r t i t i o n i n g * /
mtcr t 1 , t 0
li t 0 , S C H E D _ D E F E A T U R E
lui t 1 , 0 x01 0 0 / * D i s a b l e B R U a c c e p t i n g A L U o p s * /
mtcr t 1 , t 0
.endm
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/ *
* Allow a c c e s s t o p h y s i c a l m e m > 6 4 G b y e n a b l i n g E L P A i n P A G E G R A I N
* register. T h i s i s n e e d e d b e f o r e g o i n g t o C c o d e s i n c e t h e S P c a n
* in t h i s r e g i o n . C a l l e d f r o m a l l H W t h r e a d s .
* /
.macro xlp_early_mmu_init
mfc0 t 0 , C P 0 _ P A G E M A S K , 1
li t 1 , ( 1 < < 2 9 ) / * E L P A b i t * /
or t 0 , t 1
mtc0 t 0 , C P 0 _ P A G E M A S K , 1
.endm
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/ *
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* L1 D c a c h e h a s t o b e f l u s h e d b e f o r e e n a b l i n g t h r e a d s i n X L P .
* On X L P 8 x x / X L P 3 x x , w e d o a l o w l e v e l f l u s h u s i n g p r o c e s s o r c o n t r o l
* registers. O n X L P I I C P U s , u s u a l c a c h e i n s t r u c t i o n s w o r k .
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* /
.macro xlp_flush_l1_dcache
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mfc0 t 0 , C P 0 _ P R I D
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andi t 0 , t 0 , P R I D _ I M P _ M A S K
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slt t 1 , t 0 , 0 x12 0 0
beqz t 1 , 1 5 f
nop
/* XLP8xx low level cache flush */
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li t 0 , L S U _ D E B U G _ D A T A 0
li t 1 , L S U _ D E B U G _ A D D R
li t 2 , 0 / * i n d e x * /
li t 3 , 0 x10 0 0 / * l o o p c o u n t * /
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11 :
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sll v0 , t 2 , 5
mtcr z e r o , t 0
ori v1 , v0 , 0 x3 / * w a y 0 | w r i t e _ e n a b l e | w r i t e _ a c t i v e * /
mtcr v1 , t 1
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12 :
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mfcr v1 , t 1
andi v1 , 0 x1 / * w a i t f o r w r i t e _ a c t i v e = = 0 * /
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bnez v1 , 1 2 b
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nop
mtcr z e r o , t 0
ori v1 , v0 , 0 x7 / * w a y 1 | w r i t e _ e n a b l e | w r i t e _ a c t i v e * /
mtcr v1 , t 1
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13 :
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mfcr v1 , t 1
andi v1 , 0 x1 / * w a i t f o r w r i t e _ a c t i v e = = 0 * /
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bnez v1 , 1 3 b
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nop
addi t 2 , 1
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bne t 3 , t 2 , 1 1 b
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nop
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b 1 7 f
nop
/* XLPII CPUs, Invalidate all 64k of L1 D-cache */
15 :
li t 0 , 0 x80 0 0 0 0 0 0
li t 1 , 0 x80 0 1 0 0 0 0
16 : cache I n d e x _ W r i t e b a c k _ I n v _ D , 0 ( t 0 )
addiu t 0 , t 0 , 3 2
bne t 0 , t 1 , 1 6 b
nop
17 :
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.endm
/ *
* nlm_ r e s e t _ e n t r y w i l l b e c o p i e d t o t h e r e s e t e n t r y p o i n t f o r
* XLR a n d X L P . T h e X L P c o r e s s t a r t h e r e w h e n t h e y a r e w o k e n u p . T h i s
* is a l s o t h e N M I e n t r y p o i n t .
*
* We u s e s c r a t c h r e g 6 / 7 t o s a v e k 0 / k 1 a n d c h e c k f o r N M I f i r s t .
*
* The d a t a c o r r e s p o n d i n g t o r e s e t / N M I i s s t o r e d a t R E S E T _ D A T A _ P H Y S
* location, t h i s w i l l h a v e t h e t h r e a d m a s k ( u s e d w h e n c o r e i s w o k e n u p )
* and t h e c u r r e n t N M I h a n d l e r i n c a s e w e r e a c h e d h e r e f o r a n N M I .
*
* When a c o r e o r t h r e a d i s n e w l y w o k e n u p , i t m a r k s i t s e l f r e a d y a n d
* loops i n a ' w a i t ' . W h e n t h e C P U r e a l l y n e e d s w a k i n g u p , w e s e n d a n N M I
* IPI t o i t , w i t h t h e N M I h a n d l e r s e t t o p r o m _ b o o t _ s e c o n d a r y _ c p u s
* /
.set noreorder
.set noat
.set xlr / * f o r m f c r / m t c r , X L R i s s u f f i c i e n t * /
FEXPORT( n l m _ r e s e t _ e n t r y )
dmtc0 k 0 , $ 2 2 , 6
dmtc0 k 1 , $ 2 2 , 7
mfc0 k 0 , C P 0 _ S T A T U S
li k 1 , 0 x80 0 0 0
and k 1 , k 0 , k 1
beqz k 1 , 1 f / * g o t o r e a l r e s e t e n t r y * /
nop
li k 1 , C K S E G 1 A D D R ( R E S E T _ D A T A _ P H Y S ) / * N M I * /
ld k 0 , B O O T _ N M I _ H A N D L E R ( k 1 )
jr k 0
nop
1 : /* Entry point on core wakeup */
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mfc0 t 0 , C P 0 _ P R I D / * p r o c e s s o r I D * /
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andi t 0 , P R I D _ I M P _ M A S K
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li t 1 , 0 x15 0 0 / * X L P 9 x x * /
beq t 0 , t 1 , 2 f / * d o e s n o t n e e d t o s e t c o h e r e n t * /
nop
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li t 1 , 0 x13 0 0 / * X L P 5 x x * /
beq t 0 , t 1 , 2 f / * d o e s n o t n e e d t o s e t c o h e r e n t * /
nop
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/* set bit in SYS coherent register for the core */
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mfc0 t 0 , C P 0 _ E B A S E
mfc0 t 1 , C P 0 _ E B A S E
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srl t 1 , 5
andi t 1 , 0 x3 / * t 1 < - n o d e * /
li t 2 , 0 x40 0 0 0
mul t 3 , t 2 , t 1 / * t 3 = n o d e * 0 x40 0 0 0 * /
srl t 0 , t 0 , 2
and t 0 , t 0 , 0 x7 / * t 0 < - c o r e * /
li t 1 , 0 x1
sll t 0 , t 1 , t 0
nor t 0 , t 0 , z e r o / * t 0 < - ~ ( 1 < < c o r e ) * /
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li t 2 , S Y S _ C P U _ C O H E R E N T _ B A S E
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add t 2 , t 2 , t 3 / * t 2 < - S Y S o f f s e t f o r n o d e * /
lw t 1 , 0 ( t 2 )
and t 1 , t 1 , t 0
sw t 1 , 0 ( t 2 )
/* read back to ensure complete */
lw t 1 , 0 ( t 2 )
sync
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2 :
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/* Configure LSU on Non-0 Cores. */
xlp_ c o n f i g _ l s u
/* FALL THROUGH */
/ *
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* Wake u p s i b l i n g t h r e a d s f r o m t h e i n i t i a l t h r e a d i n a c o r e .
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* /
EXPORT( n l m _ b o o t _ s i b l i n g s )
/* core L1D flush before enable threads */
xlp_ f l u s h _ l 1 _ d c a c h e
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/* save ra and sp, will be used later (only for boot cpu) */
dmtc0 r a , $ 2 2 , 6
dmtc0 s p , $ 2 2 , 7
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
li t 0 , C K S E G 1 A D D R ( R E S E T _ D A T A _ P H Y S )
lw t 1 , B O O T _ T H R E A D _ M O D E ( t 0 ) / * t 1 < - t h r e a d m o d e * /
li t 0 , ( ( C P U _ B L O C K I D _ M A P < < 8 ) | M A P _ T H R E A D M O D E )
mfcr t 2 , t 0
or t 2 , t 2 , t 1
mtcr t 2 , t 0
/ *
* The n e w h a r d w a r e t h r e a d s t a r t s a t t h e n e x t i n s t r u c t i o n
* For a l l t h e c a s e s o t h e r t h a n c o r e 0 t h r e a d 0 , w e w i l l
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* jump t o t h e s e c o n d a r y w a i t f u n c t i o n .
* NOTE : All G P R c o n t e n t s a r e l o s t a f t e r t h e m t c r a b o v e !
* /
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mfc0 v0 , C P 0 _ E B A S E
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andi v0 , 0 x3 f f / * v0 < - n o d e / c o r e * /
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/ *
* Errata : to a v o i d p o t e n t i a l l i v e l o c k , s e t u p I F U _ B R U B _ R E S E R V E
* when r u n n i n g 4 t h r e a d s p e r c o r e
* /
andi v1 , v0 , 0 x3 / * v1 < - t h r e a d i d * /
bnez v1 , 2 f
nop
/* thread 0 of each core. */
li t 0 , C K S E G 1 A D D R ( R E S E T _ D A T A _ P H Y S )
lw t 1 , B O O T _ T H R E A D _ M O D E ( t 0 ) / * t 1 < - t h r e a d m o d e * /
subu t 1 , 0 x3 / * 4 - t h r e a d p e r c o r e m o d e ? * /
bnez t 1 , 2 f
nop
li t 0 , I F U _ B R U B _ R E S E R V E
li t 1 , 0 x55
mtcr t 1 , t 0
_ ehb
2 :
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beqz v0 , 4 f / * b o o t c p u ( c p u i d = = 0 ) ? * /
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nop
/* setup status reg */
move t 1 , z e r o
# ifdef C O N F I G _ 6 4 B I T
ori t 1 , S T 0 _ K X
# endif
mtc0 t 1 , C P 0 _ S T A T U S
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xlp_ e a r l y _ m m u _ i n i t
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/* mark CPU ready */
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li t 3 , C K S E G 1 A D D R ( R E S E T _ D A T A _ P H Y S )
ADDIU t 1 , t 3 , B O O T _ C P U _ R E A D Y
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sll v1 , v0 , 2
PTR_ A D D U t 1 , v1
li t 2 , 1
sw t 2 , 0 ( t 1 )
/* Wait until NMI hits */
3 : wait
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b 3 b
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nop
/ *
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* For t h e b o o t C P U , w e h a v e t o r e s t o r e r a a n d s p a n d r e t u r n , r e s t
* of t h e r e g i s t e r s w i l l b e r e s t o r e d b y t h e c a l l e r
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* /
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4 :
dmfc0 r a , $ 2 2 , 6
dmfc0 s p , $ 2 2 , 7
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jr r a
nop
EXPORT( n l m _ r e s e t _ e n t r y _ e n d )
LEAF( n l m _ i n i t _ b o o t _ c p u )
# ifdef C O N F I G _ C P U _ X L P
xlp_ c o n f i g _ l s u
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xlp_ e a r l y _ m m u _ i n i t
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# endif
jr r a
nop
END( n l m _ i n i t _ b o o t _ c p u )
