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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
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#include <dt-bindings/gpio/gpio.h>
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#include "imx28-pinfunc.h"
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/ {
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#address-cells = <1>;
#size-cells = <1>;
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interrupt-parent = <&icoll>;
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/*
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
*/
chosen {};
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aliases {
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ethernet0 = &mac0;
ethernet1 = &mac1;
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gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
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saif0 = &saif0;
saif1 = &saif1;
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serial0 = &auart0;
serial1 = &auart1;
serial2 = &auart2;
serial3 = &auart3;
serial4 = &auart4;
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spi0 = &ssp1;
spi1 = &ssp2;
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usbphy0 = &usbphy0;
usbphy1 = &usbphy1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,arm926ej-s";
device_type = "cpu";
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reg = <0>;
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};
};
apb@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x80000>;
ranges;
apbh@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x3c900>;
ranges;
icoll: interrupt-controller@80000000 {
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compatible = "fsl,imx28-icoll", "fsl,icoll";
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interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80000000 0x2000>;
};
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hsadc: hsadc@80002000 {
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reg = <0x80002000 0x2000>;
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interrupts = <13>;
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dmas = <&dma_apbh 12>;
dma-names = "rx";
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status = "disabled";
};
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dma_apbh: dma-apbh@80004000 {
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compatible = "fsl,imx28-dma-apbh";
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reg = <0x80004000 0x2000>;
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interrupts = <82 83 84 85
88 88 88 88
88 88 88 88
87 86 0 0>;
interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
"gpmi0", "gmpi1", "gpmi2", "gmpi3",
"gpmi4", "gmpi5", "gpmi6", "gmpi7",
"hsadc", "lcdif", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
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clocks = <&clks 25>;
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};
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perfmon: perfmon@80006000 {
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reg = <0x80006000 0x800>;
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interrupts = <27>;
status = "disabled";
};
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gpmi: nand-controller@8000c000 {
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compatible = "fsl,imx28-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
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reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <41>;
interrupt-names = "bch";
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clocks = <&clks 50>;
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clock-names = "gpmi_io";
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dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
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status = "disabled";
};
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ssp0: spi@80010000 {
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#address-cells = <1>;
#size-cells = <0>;
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reg = <0x80010000 0x2000>;
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interrupts = <96>;
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clocks = <&clks 46>;
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dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
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status = "disabled";
};
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ssp1: spi@80012000 {
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#address-cells = <1>;
#size-cells = <0>;
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reg = <0x80012000 0x2000>;
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interrupts = <97>;
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clocks = <&clks 47>;
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dmas = <&dma_apbh 1>;
dma-names = "rx-tx";
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status = "disabled";
};
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ssp2: spi@80014000 {
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#address-cells = <1>;
#size-cells = <0>;
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reg = <0x80014000 0x2000>;
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interrupts = <98>;
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clocks = <&clks 48>;
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dmas = <&dma_apbh 2>;
dma-names = "rx-tx";
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status = "disabled";
};
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ssp3: spi@80016000 {
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#address-cells = <1>;
#size-cells = <0>;
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reg = <0x80016000 0x2000>;
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interrupts = <99>;
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clocks = <&clks 49>;
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dmas = <&dma_apbh 3>;
dma-names = "rx-tx";
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status = "disabled";
};
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pinctrl: pinctrl@80018000 {
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#address-cells = <1>;
#size-cells = <0>;
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compatible = "fsl,imx28-pinctrl", "simple-bus";
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reg = <0x80018000 0x2000>;
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gpio0: gpio@0 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
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reg = <0>;
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interrupts = <127>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@1 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
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reg = <1>;
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interrupts = <126>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
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reg = <2>;
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interrupts = <125>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@3 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
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reg = <3>;
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interrupts = <124>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@4 {
compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
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reg = <4>;
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interrupts = <123>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
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duart_pins_a: duart@0 {
reg = <0>;
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fsl,pinmux-ids = <
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MX28_PAD_PWM0__DUART_RX
MX28_PAD_PWM1__DUART_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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duart_pins_b: duart@1 {
reg = <1>;
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fsl,pinmux-ids = <
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MX28_PAD_AUART0_CTS__DUART_RX
MX28_PAD_AUART0_RTS__DUART_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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duart_4pins_a: duart-4pins@0 {
reg = <0>;
fsl,pinmux-ids = <
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MX28_PAD_AUART0_CTS__DUART_RX
MX28_PAD_AUART0_RTS__DUART_TX
MX28_PAD_AUART0_RX__DUART_CTS
MX28_PAD_AUART0_TX__DUART_RTS
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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gpmi_pins_a: gpmi-nand@0 {
reg = <0>;
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fsl,pinmux-ids = <
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MX28_PAD_GPMI_D00__GPMI_D0
MX28_PAD_GPMI_D01__GPMI_D1
MX28_PAD_GPMI_D02__GPMI_D2
MX28_PAD_GPMI_D03__GPMI_D3
MX28_PAD_GPMI_D04__GPMI_D4
MX28_PAD_GPMI_D05__GPMI_D5
MX28_PAD_GPMI_D06__GPMI_D6
MX28_PAD_GPMI_D07__GPMI_D7
MX28_PAD_GPMI_CE0N__GPMI_CE0N
MX28_PAD_GPMI_RDY0__GPMI_READY0
MX28_PAD_GPMI_RDN__GPMI_RDN
MX28_PAD_GPMI_WRN__GPMI_WRN
MX28_PAD_GPMI_ALE__GPMI_ALE
MX28_PAD_GPMI_CLE__GPMI_CLE
MX28_PAD_GPMI_RESETN__GPMI_RESETN
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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gpmi_status_cfg: gpmi-status-cfg@0 {
reg = <0>;
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fsl,pinmux-ids = <
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MX28_PAD_GPMI_RDN__GPMI_RDN
MX28_PAD_GPMI_WRN__GPMI_WRN
MX28_PAD_GPMI_RESETN__GPMI_RESETN
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>;
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fsl,drive-strength = <MXS_DRIVE_12mA>;
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};
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auart0_pins_a: auart0@0 {
reg = <0>;
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fsl,pinmux-ids = <
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MX28_PAD_AUART0_RX__AUART0_RX
MX28_PAD_AUART0_TX__AUART0_TX
MX28_PAD_AUART0_CTS__AUART0_CTS
MX28_PAD_AUART0_RTS__AUART0_RTS
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
auart0_2pins_a: auart0-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
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MX28_PAD_AUART0_RX__AUART0_RX
MX28_PAD_AUART0_TX__AUART0_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart1_pins_a: auart1@0 {
reg = <0>;
fsl,pinmux-ids = <
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MX28_PAD_AUART1_RX__AUART1_RX
MX28_PAD_AUART1_TX__AUART1_TX
MX28_PAD_AUART1_CTS__AUART1_CTS
MX28_PAD_AUART1_RTS__AUART1_RTS
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart1_2pins_a: auart1-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
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MX28_PAD_AUART1_RX__AUART1_RX
MX28_PAD_AUART1_TX__AUART1_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
auart2_2pins_a: auart2-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
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MX28_PAD_SSP2_SCK__AUART2_RX
MX28_PAD_SSP2_MOSI__AUART2_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart2_2pins_b: auart2-2pins@1 {
reg = <1>;
fsl,pinmux-ids = <
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MX28_PAD_AUART2_RX__AUART2_RX
MX28_PAD_AUART2_TX__AUART2_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart2_pins_a: auart2-pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_AUART2_RX__AUART2_RX
MX28_PAD_AUART2_TX__AUART2_TX
MX28_PAD_AUART2_CTS__AUART2_CTS
MX28_PAD_AUART2_RTS__AUART2_RTS
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
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auart3_pins_a: auart3@0 {
reg = <0>;
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fsl,pinmux-ids = <
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MX28_PAD_AUART3_RX__AUART3_RX
MX28_PAD_AUART3_TX__AUART3_TX
MX28_PAD_AUART3_CTS__AUART3_CTS
MX28_PAD_AUART3_RTS__AUART3_RTS
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart3_2pins_a: auart3-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
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MX28_PAD_SSP2_MISO__AUART3_RX
MX28_PAD_SSP2_SS0__AUART3_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart3_2pins_b: auart3-2pins@1 {
reg = <1>;
fsl,pinmux-ids = <
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MX28_PAD_AUART3_RX__AUART3_RX
MX28_PAD_AUART3_TX__AUART3_TX
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>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart4_2pins_a: auart4@0 {
reg = <0>;
fsl,pinmux-ids = <
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MX28_PAD_SSP3_SCK__AUART4_TX
MX28_PAD_SSP3_MOSI__AUART4_RX
2013-04-08 14:57:33 +02:00
>;
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fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
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};
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auart4_2pins_b: auart4@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_AUART0_CTS__AUART4_RX
MX28_PAD_AUART0_RTS__AUART4_TX
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
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mac0_pins_a: mac0@0 {
reg = <0>;
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fsl,pinmux-ids = <
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MX28_PAD_ENET0_MDC__ENET0_MDC
MX28_PAD_ENET0_MDIO__ENET0_MDIO
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
MX28_PAD_ENET0_RXD0__ENET0_RXD0
MX28_PAD_ENET0_RXD1__ENET0_RXD1
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
MX28_PAD_ENET0_TXD0__ENET0_TXD0
MX28_PAD_ENET0_TXD1__ENET0_TXD1
MX28_PAD_ENET_CLK__CLKCTRL_ENET
2012-06-28 11:44:57 +08:00
>;
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fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
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};
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mac0_pins_b: mac0@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_ENET0_MDC__ENET0_MDC
MX28_PAD_ENET0_MDIO__ENET0_MDIO
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
MX28_PAD_ENET0_RXD0__ENET0_RXD0
MX28_PAD_ENET0_RXD1__ENET0_RXD1
MX28_PAD_ENET0_RXD2__ENET0_RXD2
MX28_PAD_ENET0_RXD3__ENET0_RXD3
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
MX28_PAD_ENET0_TXD0__ENET0_TXD0
MX28_PAD_ENET0_TXD1__ENET0_TXD1
MX28_PAD_ENET0_TXD2__ENET0_TXD2
MX28_PAD_ENET0_TXD3__ENET0_TXD3
MX28_PAD_ENET_CLK__CLKCTRL_ENET
MX28_PAD_ENET0_COL__ENET0_COL
MX28_PAD_ENET0_CRS__ENET0_CRS
MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
2012-03-31 21:26:57 +08:00
mac1_pins_a: mac1@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_ENET0_CRS__ENET1_RX_EN
MX28_PAD_ENET0_RXD2__ENET1_RXD0
MX28_PAD_ENET0_RXD3__ENET1_RXD1
MX28_PAD_ENET0_COL__ENET1_TX_EN
MX28_PAD_ENET0_TXD2__ENET1_TXD0
MX28_PAD_ENET0_TXD3__ENET1_TXD1
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-03-31 21:26:57 +08:00
};
2012-05-06 16:33:34 +08:00
mmc0_8bit_pins_a: mmc0-8bit@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SSP0_DATA0__SSP0_D0
MX28_PAD_SSP0_DATA1__SSP0_D1
MX28_PAD_SSP0_DATA2__SSP0_D2
MX28_PAD_SSP0_DATA3__SSP0_D3
MX28_PAD_SSP0_DATA4__SSP0_D4
MX28_PAD_SSP0_DATA5__SSP0_D5
MX28_PAD_SSP0_DATA6__SSP0_D6
MX28_PAD_SSP0_DATA7__SSP0_D7
MX28_PAD_SSP0_CMD__SSP0_CMD
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
MX28_PAD_SSP0_SCK__SSP0_SCK
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-05-06 16:33:34 +08:00
};
2012-06-27 10:18:11 +02:00
mmc0_4bit_pins_a: mmc0-4bit@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SSP0_DATA0__SSP0_D0
MX28_PAD_SSP0_DATA1__SSP0_D1
MX28_PAD_SSP0_DATA2__SSP0_D2
MX28_PAD_SSP0_DATA3__SSP0_D3
MX28_PAD_SSP0_CMD__SSP0_CMD
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
MX28_PAD_SSP0_SCK__SSP0_SCK
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-06-27 10:18:11 +02:00
};
2017-12-27 12:04:35 -02:00
mmc0_cd_cfg: mmc0-cd-cfg@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-05-06 16:33:34 +08:00
};
2017-12-27 12:04:35 -02:00
mmc0_sck_cfg: mmc0-sck-cfg@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SSP0_SCK__SSP0_SCK
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-05-06 16:33:34 +08:00
};
2012-05-10 15:02:10 +08:00
2014-08-08 11:24:21 +02:00
mmc1_4bit_pins_a: mmc1-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__SSP1_D0
MX28_PAD_GPMI_D01__SSP1_D1
MX28_PAD_GPMI_D02__SSP1_D2
MX28_PAD_GPMI_D03__SSP1_D3
MX28_PAD_GPMI_RDY1__SSP1_CMD
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
2017-12-27 12:04:35 -02:00
mmc1_cd_cfg: mmc1-cd-cfg@0 {
reg = <0>;
2014-08-08 11:24:21 +02:00
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
2017-12-27 12:04:35 -02:00
mmc1_sck_cfg: mmc1-sck-cfg@0 {
reg = <0>;
2014-08-08 11:24:21 +02:00
fsl,pinmux-ids = <
MX28_PAD_GPMI_WRN__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
2013-09-26 13:16:16 +02:00
mmc2_4bit_pins_a: mmc2-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA4__SSP2_D0
MX28_PAD_SSP1_SCK__SSP2_D1
MX28_PAD_SSP1_CMD__SSP2_D2
MX28_PAD_SSP0_DATA5__SSP2_D3
MX28_PAD_SSP0_DATA6__SSP2_CMD
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
MX28_PAD_SSP0_DATA7__SSP2_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
2017-02-09 08:42:41 +01:00
mmc2_4bit_pins_b: mmc2-4bit@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__SSP2_SCK
MX28_PAD_SSP2_MOSI__SSP2_CMD
MX28_PAD_SSP2_MISO__SSP2_D0
MX28_PAD_SSP2_SS0__SSP2_D3
MX28_PAD_SSP2_SS1__SSP2_D1
MX28_PAD_SSP2_SS2__SSP2_D2
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
2017-12-27 12:04:35 -02:00
mmc2_cd_cfg: mmc2-cd-cfg@0 {
reg = <0>;
2013-09-26 13:16:16 +02:00
fsl,pinmux-ids = <
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
2017-02-09 08:42:42 +01:00
mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
reg = <0>;
2013-09-26 13:16:16 +02:00
fsl,pinmux-ids = <
MX28_PAD_SSP0_DATA7__SSP2_SCK
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-05-06 16:33:34 +08:00
};
2012-05-10 15:02:10 +08:00
2017-02-09 08:42:43 +01:00
mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_SSP2_SCK__SSP2_SCK
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
2012-05-10 15:02:10 +08:00
i2c0_pins_a: i2c0@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_I2C0_SCL__I2C0_SCL
MX28_PAD_I2C0_SDA__I2C0_SDA
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-05-10 15:02:10 +08:00
};
2012-05-10 15:03:16 +08:00
2012-08-23 10:42:29 +02:00
i2c0_pins_b: i2c0@1 {
reg = <1>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_AUART0_RX__I2C0_SCL
MX28_PAD_AUART0_TX__I2C0_SDA
2012-08-23 10:42:29 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-08-23 10:42:29 +02:00
};
2012-08-31 16:00:40 +02:00
i2c1_pins_a: i2c1@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_PWM0__I2C1_SCL
MX28_PAD_PWM1__I2C1_SDA
2012-08-31 16:00:40 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-08-31 16:00:40 +02:00
};
2014-08-08 11:24:22 +02:00
i2c1_pins_b: i2c1@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_AUART2_CTS__I2C1_SCL
MX28_PAD_AUART2_RTS__I2C1_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
2012-05-10 15:03:16 +08:00
saif0_pins_a: saif0@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-05-10 15:03:16 +08:00
};
2013-08-08 14:51:22 +02:00
saif0_pins_b: saif0@1 {
reg = <1>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2013-08-08 14:51:22 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2013-08-08 14:51:22 +02:00
};
2012-05-10 15:03:16 +08:00
saif1_pins_a: saif1@0 {
reg = <0>;
2012-06-28 11:44:57 +08:00
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
2012-06-28 11:44:57 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-05-10 15:03:16 +08:00
};
2012-06-28 11:45:06 +08:00
2012-07-09 12:34:35 +08:00
pwm0_pins_a: pwm0@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_PWM0__PWM_0
2012-07-09 12:34:35 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-07-09 12:34:35 +08:00
};
2012-06-28 11:45:06 +08:00
pwm2_pins_a: pwm2@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_PWM2__PWM_2
2012-06-28 11:45:06 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-06-28 11:45:06 +08:00
};
2012-06-28 11:45:07 +08:00
2012-10-27 12:15:46 +02:00
pwm3_pins_a: pwm3@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_PWM3__PWM_3
2012-10-27 12:15:46 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-10-27 12:15:46 +02:00
};
2013-01-25 09:54:06 +01:00
pwm3_pins_b: pwm3@1 {
reg = <1>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SAIF0_MCLK__PWM_3
2013-01-25 09:54:06 +01:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2013-01-25 09:54:06 +01:00
};
2012-08-23 10:42:30 +02:00
pwm4_pins_a: pwm4@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_PWM4__PWM_4
2012-08-23 10:42:30 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-08-23 10:42:30 +02:00
};
2012-06-28 11:45:07 +08:00
lcdif_24bit_pins_a: lcdif-24bit@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
MX28_PAD_LCD_D02__LCD_D2
MX28_PAD_LCD_D03__LCD_D3
MX28_PAD_LCD_D04__LCD_D4
MX28_PAD_LCD_D05__LCD_D5
MX28_PAD_LCD_D06__LCD_D6
MX28_PAD_LCD_D07__LCD_D7
MX28_PAD_LCD_D08__LCD_D8
MX28_PAD_LCD_D09__LCD_D9
MX28_PAD_LCD_D10__LCD_D10
MX28_PAD_LCD_D11__LCD_D11
MX28_PAD_LCD_D12__LCD_D12
MX28_PAD_LCD_D13__LCD_D13
MX28_PAD_LCD_D14__LCD_D14
MX28_PAD_LCD_D15__LCD_D15
MX28_PAD_LCD_D16__LCD_D16
MX28_PAD_LCD_D17__LCD_D17
MX28_PAD_LCD_D18__LCD_D18
MX28_PAD_LCD_D19__LCD_D19
MX28_PAD_LCD_D20__LCD_D20
MX28_PAD_LCD_D21__LCD_D21
MX28_PAD_LCD_D22__LCD_D22
MX28_PAD_LCD_D23__LCD_D23
2012-06-28 11:45:07 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-06-28 11:45:07 +08:00
};
2012-06-28 11:45:03 +08:00
2013-12-05 14:28:04 +01:00
lcdif_18bit_pins_a: lcdif-18bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
MX28_PAD_LCD_D02__LCD_D2
MX28_PAD_LCD_D03__LCD_D3
MX28_PAD_LCD_D04__LCD_D4
MX28_PAD_LCD_D05__LCD_D5
MX28_PAD_LCD_D06__LCD_D6
MX28_PAD_LCD_D07__LCD_D7
MX28_PAD_LCD_D08__LCD_D8
MX28_PAD_LCD_D09__LCD_D9
MX28_PAD_LCD_D10__LCD_D10
MX28_PAD_LCD_D11__LCD_D11
MX28_PAD_LCD_D12__LCD_D12
MX28_PAD_LCD_D13__LCD_D13
MX28_PAD_LCD_D14__LCD_D14
MX28_PAD_LCD_D15__LCD_D15
MX28_PAD_LCD_D16__LCD_D16
MX28_PAD_LCD_D17__LCD_D17
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
2012-11-01 17:50:59 +01:00
lcdif_16bit_pins_a: lcdif-16bit@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_LCD_D00__LCD_D0
MX28_PAD_LCD_D01__LCD_D1
MX28_PAD_LCD_D02__LCD_D2
MX28_PAD_LCD_D03__LCD_D3
MX28_PAD_LCD_D04__LCD_D4
MX28_PAD_LCD_D05__LCD_D5
MX28_PAD_LCD_D06__LCD_D6
MX28_PAD_LCD_D07__LCD_D7
MX28_PAD_LCD_D08__LCD_D8
MX28_PAD_LCD_D09__LCD_D9
MX28_PAD_LCD_D10__LCD_D10
MX28_PAD_LCD_D11__LCD_D11
MX28_PAD_LCD_D12__LCD_D12
MX28_PAD_LCD_D13__LCD_D13
MX28_PAD_LCD_D14__LCD_D14
MX28_PAD_LCD_D15__LCD_D15
2012-11-01 17:50:59 +01:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-11-01 17:50:59 +01:00
};
2013-08-08 14:51:24 +02:00
lcdif_sync_pins_a: lcdif-sync@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_LCD_RS__LCD_DOTCLK
MX28_PAD_LCD_CS__LCD_ENABLE
MX28_PAD_LCD_RD_E__LCD_VSYNC
MX28_PAD_LCD_WR_RWN__LCD_HSYNC
2013-08-08 14:51:24 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2013-08-08 14:51:24 +02:00
};
2012-06-28 11:45:03 +08:00
can0_pins_a: can0@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_GPMI_RDY2__CAN0_TX
MX28_PAD_GPMI_RDY3__CAN0_RX
2012-06-28 11:45:03 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-06-28 11:45:03 +08:00
};
can1_pins_a: can1@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_GPMI_CE2N__CAN1_TX
MX28_PAD_GPMI_CE3N__CAN1_RX
2012-06-28 11:45:03 +08:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-06-28 11:45:03 +08:00
};
2012-08-25 01:51:37 +02:00
spi2_pins_a: spi2@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SSP2_SCK__SSP2_SCK
MX28_PAD_SSP2_MOSI__SSP2_CMD
MX28_PAD_SSP2_MISO__SSP2_D0
MX28_PAD_SSP2_SS0__SSP2_D3
2012-08-25 01:51:37 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-08-25 01:51:37 +02:00
};
2012-08-25 01:51:38 +02:00
2013-08-08 14:51:23 +02:00
spi3_pins_a: spi3@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_AUART2_RX__SSP3_D4
MX28_PAD_AUART2_TX__SSP3_D5
MX28_PAD_SSP3_SCK__SSP3_SCK
MX28_PAD_SSP3_MOSI__SSP3_CMD
MX28_PAD_SSP3_MISO__SSP3_D0
MX28_PAD_SSP3_SS0__SSP3_D3
2013-08-08 14:51:23 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2013-08-08 14:51:23 +02:00
};
2015-03-19 10:55:47 +01:00
spi3_pins_b: spi3@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_SSP3_SCK__SSP3_SCK
MX28_PAD_SSP3_MOSI__SSP3_CMD
MX28_PAD_SSP3_MISO__SSP3_D0
MX28_PAD_SSP3_SS0__SSP3_D3
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
2013-12-06 15:56:40 +01:00
usb0_pins_a: usb0@0 {
2012-08-25 01:51:38 +02:00
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
2012-08-25 01:51:38 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-08-25 01:51:38 +02:00
};
2013-12-06 15:56:40 +01:00
usb0_pins_b: usb0@1 {
2012-08-25 01:51:38 +02:00
reg = <1>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
2012-08-25 01:51:38 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-08-25 01:51:38 +02:00
};
2013-12-06 15:56:40 +01:00
usb1_pins_a: usb1@0 {
2012-08-25 01:51:38 +02:00
reg = <0>;
fsl,pinmux-ids = <
2013-09-19 08:59:48 +02:00
MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
2012-08-25 01:51:38 +02:00
>;
2013-09-22 14:02:59 +08:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
2012-08-25 01:51:38 +02:00
};
2013-08-21 10:27:03 -03:00
usb0_id_pins_a: usb0id@0 {
reg = <0>;
fsl,pinmux-ids = <
2013-09-23 14:20:27 +02:00
MX28_PAD_AUART1_RTS__USB0_ID
2012-08-25 01:51:38 +02:00
>;
2013-09-23 14:20:27 +02:00
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
2012-08-25 01:51:38 +02:00
};
2013-12-05 14:28:05 +01:00
usb0_id_pins_b: usb0id1@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_PWM2__USB0_ID
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
2012-03-31 21:26:57 +08:00
};
2013-08-08 14:51:21 +02:00
digctl: digctl@8001c000 {
2013-06-04 10:18:44 -03:00
compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
2012-07-30 21:29:19 -03:00
reg = <0x8001c000 0x2000>;
2012-03-31 21:26:57 +08:00
interrupts = <89>;
status = "disabled";
};
2013-08-08 14:51:21 +02:00
etm: etm@80022000 {
2012-07-30 21:29:19 -03:00
reg = <0x80022000 0x2000>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-02-25 21:56:56 +08:00
dma_apbx: dma-apbx@80024000 {
2012-05-04 20:12:19 +08:00
compatible = "fsl,imx28-dma-apbx";
2012-07-30 21:29:19 -03:00
reg = <0x80024000 0x2000>;
2013-02-25 21:56:56 +08:00
interrupts = <78 79 66 0
80 81 68 69
70 71 72 73
74 75 76 77>;
2015-04-24 13:29:47 +02:00
interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
2013-02-25 21:56:56 +08:00
"saif0", "saif1", "i2c0", "i2c1",
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
#dma-cells = <1>;
dma-channels = <16>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 26>;
2012-03-31 21:26:57 +08:00
};
2020-03-05 15:59:08 +02:00
dcp: crypto@80028000 {
2013-12-10 20:26:22 +01:00
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
2012-07-30 21:29:19 -03:00
reg = <0x80028000 0x2000>;
2012-03-31 21:26:57 +08:00
interrupts = <52 53 54>;
2013-12-10 20:26:22 +01:00
status = "okay";
2012-03-31 21:26:57 +08:00
};
2013-08-08 14:51:21 +02:00
pxp: pxp@8002a000 {
2012-07-30 21:29:19 -03:00
reg = <0x8002a000 0x2000>;
2012-03-31 21:26:57 +08:00
interrupts = <39>;
status = "disabled";
};
2020-05-28 11:12:49 +08:00
ocotp: efuse@8002c000 {
2015-08-12 22:21:56 +00:00
compatible = "fsl,imx28-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
2012-07-30 21:29:19 -03:00
reg = <0x8002c000 0x2000>;
2015-08-12 22:21:56 +00:00
clocks = <&clks 25>;
2012-03-31 21:26:57 +08:00
};
axi-ahb@8002e000 {
2012-07-30 21:29:19 -03:00
reg = <0x8002e000 0x2000>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
lcdif: lcdif@80030000 {
2012-06-28 11:45:07 +08:00
compatible = "fsl,imx28-lcdif";
2012-07-30 21:29:19 -03:00
reg = <0x80030000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <38>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 55>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbh 13>;
dma-names = "rx";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
can0: can@80032000 {
2017-11-24 18:52:12 +05:30
compatible = "fsl,imx28-flexcan";
2012-07-30 21:29:19 -03:00
reg = <0x80032000 0x2000>;
2012-03-31 21:26:57 +08:00
interrupts = <8>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 58>, <&clks 58>;
clock-names = "ipg", "per";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
can1: can@80034000 {
2017-11-24 18:52:12 +05:30
compatible = "fsl,imx28-flexcan";
2012-07-30 21:29:19 -03:00
reg = <0x80034000 0x2000>;
2012-03-31 21:26:57 +08:00
interrupts = <9>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 59>, <&clks 59>;
clock-names = "ipg", "per";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
simdbg: simdbg@8003c000 {
2012-07-30 21:29:19 -03:00
reg = <0x8003c000 0x200>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
simgpmisel: simgpmisel@8003c200 {
2012-07-30 21:29:19 -03:00
reg = <0x8003c200 0x100>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
simsspsel: simsspsel@8003c300 {
2012-07-30 21:29:19 -03:00
reg = <0x8003c300 0x100>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
simmemsel: simmemsel@8003c400 {
2012-07-30 21:29:19 -03:00
reg = <0x8003c400 0x100>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
gpiomon: gpiomon@8003c500 {
2012-07-30 21:29:19 -03:00
reg = <0x8003c500 0x100>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
simenet: simenet@8003c700 {
2012-07-30 21:29:19 -03:00
reg = <0x8003c700 0x100>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
armjtag: armjtag@8003c800 {
2012-07-30 21:29:19 -03:00
reg = <0x8003c800 0x100>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:20 +02:00
};
2012-03-31 21:26:57 +08:00
apbx@80040000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80040000 0x40000>;
ranges;
2012-08-22 21:36:29 +08:00
clks: clkctrl@80040000 {
2013-03-29 09:33:09 +08:00
compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
2012-07-30 21:29:19 -03:00
reg = <0x80040000 0x2000>;
2012-08-22 21:36:29 +08:00
#clock-cells = <1>;
2012-03-31 21:26:57 +08:00
};
saif0: saif@80042000 {
2016-12-20 16:35:16 +01:00
#sound-dai-cells = <0>;
2012-05-10 15:03:16 +08:00
compatible = "fsl,imx28-saif";
2012-07-30 21:29:19 -03:00
reg = <0x80042000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <59>;
2013-07-01 15:46:05 +08:00
#clock-cells = <0>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 53>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 4>;
dma-names = "rx-tx";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
power: power@80044000 {
2012-07-30 21:29:19 -03:00
reg = <0x80044000 0x2000>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
saif1: saif@80046000 {
2016-12-20 16:35:16 +01:00
#sound-dai-cells = <0>;
2012-05-10 15:03:16 +08:00
compatible = "fsl,imx28-saif";
2012-07-30 21:29:19 -03:00
reg = <0x80046000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <58>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 54>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 5>;
dma-names = "rx-tx";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
lradc: lradc@80050000 {
2012-08-17 10:42:52 +08:00
compatible = "fsl,imx28-lradc";
2012-07-30 21:29:19 -03:00
reg = <0x80050000 0x2000>;
2012-08-17 10:42:52 +08:00
interrupts = <10 14 15 16 17 18 19
20 21 22 23 24 25>;
2012-03-31 21:26:57 +08:00
status = "disabled";
2013-09-23 15:36:00 +01:00
clocks = <&clks 41>;
2013-12-06 21:20:31 +01:00
#io-channel-cells = <1>;
2012-03-31 21:26:57 +08:00
};
2013-08-08 14:51:21 +02:00
spdif: spdif@80054000 {
2012-07-30 21:29:19 -03:00
reg = <0x80054000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <45>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 2>;
dma-names = "tx";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
mxs_rtc: rtc@80056000 {
2012-06-28 11:45:05 +08:00
compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
2012-07-30 21:29:19 -03:00
reg = <0x80056000 0x2000>;
2012-06-28 11:45:05 +08:00
interrupts = <29>;
2012-03-31 21:26:57 +08:00
};
i2c0: i2c@80058000 {
2012-05-10 15:02:10 +08:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-i2c";
2012-07-30 21:29:19 -03:00
reg = <0x80058000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <111>;
2012-07-09 18:22:53 +02:00
clock-frequency = <100000>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 6>;
dma-names = "rx-tx";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
i2c1: i2c@8005a000 {
2012-05-10 15:02:10 +08:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-i2c";
2012-07-30 21:29:19 -03:00
reg = <0x8005a000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <110>;
2012-07-09 18:22:53 +02:00
clock-frequency = <100000>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 7>;
dma-names = "rx-tx";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2012-06-28 11:45:06 +08:00
pwm: pwm@80064000 {
compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
2012-07-30 21:29:19 -03:00
reg = <0x80064000 0x2000>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 44>;
2012-06-28 11:45:06 +08:00
#pwm-cells = <2>;
fsl,pwm-number = <8>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
timer: timrot@80068000 {
2012-08-20 08:51:45 +08:00
compatible = "fsl,imx28-timrot", "fsl,timrot";
2012-07-30 21:29:19 -03:00
reg = <0x80068000 0x2000>;
2012-08-20 08:51:45 +08:00
interrupts = <48 49 50 51>;
2013-03-25 22:57:14 +08:00
clocks = <&clks 26>;
2012-03-31 21:26:57 +08:00
};
auart0: serial@8006a000 {
2012-06-15 12:35:56 -03:00
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
2012-03-31 21:26:57 +08:00
reg = <0x8006a000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <112>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
2012-08-22 21:36:29 +08:00
clocks = <&clks 45>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
auart1: serial@8006c000 {
2012-06-15 12:35:56 -03:00
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
2012-03-31 21:26:57 +08:00
reg = <0x8006c000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <113>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 10>, <&dma_apbx 11>;
dma-names = "rx", "tx";
2012-08-22 21:36:29 +08:00
clocks = <&clks 45>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
auart2: serial@8006e000 {
2012-06-15 12:35:56 -03:00
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
2012-03-31 21:26:57 +08:00
reg = <0x8006e000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <114>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 12>, <&dma_apbx 13>;
dma-names = "rx", "tx";
2012-08-22 21:36:29 +08:00
clocks = <&clks 45>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
auart3: serial@80070000 {
2012-06-15 12:35:56 -03:00
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
2012-03-31 21:26:57 +08:00
reg = <0x80070000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <115>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 14>, <&dma_apbx 15>;
dma-names = "rx", "tx";
2012-08-22 21:36:29 +08:00
clocks = <&clks 45>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
auart4: serial@80072000 {
2012-06-15 12:35:56 -03:00
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
2012-03-31 21:26:57 +08:00
reg = <0x80072000 0x2000>;
2013-07-16 17:10:55 +08:00
interrupts = <116>;
2013-02-25 21:56:56 +08:00
dmas = <&dma_apbx 0>, <&dma_apbx 1>;
dma-names = "rx", "tx";
2012-08-22 21:36:29 +08:00
clocks = <&clks 45>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
duart: serial@80074000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80074000 0x1000>;
interrupts = <47>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 45>, <&clks 26>;
clock-names = "uart", "apb_pclk";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
usbphy0: usbphy@8007c000 {
2012-07-12 10:25:27 +08:00
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
2012-03-31 21:26:57 +08:00
reg = <0x8007c000 0x2000>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 62>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
usbphy1: usbphy@8007e000 {
2012-07-12 10:25:27 +08:00
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
2012-03-31 21:26:57 +08:00
reg = <0x8007e000 0x2000>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 63>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
};
};
ahb@80080000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80080000 0x80000>;
ranges;
2012-07-12 10:25:27 +08:00
usb0: usb@80080000 {
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
2012-03-31 21:26:57 +08:00
reg = <0x80080000 0x10000>;
2012-07-12 10:25:27 +08:00
interrupts = <93>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 60>;
2012-07-12 10:25:27 +08:00
fsl,usbphy = <&usbphy0>;
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2012-07-12 10:25:27 +08:00
usb1: usb@80090000 {
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
2012-03-31 21:26:57 +08:00
reg = <0x80090000 0x10000>;
2012-07-12 10:25:27 +08:00
interrupts = <92>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 61>;
2012-07-12 10:25:27 +08:00
fsl,usbphy = <&usbphy1>;
2015-02-27 09:06:00 -05:00
dr_mode = "host";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
dflpt: dflpt@800c0000 {
2012-03-31 21:26:57 +08:00
reg = <0x800c0000 0x10000>;
status = "disabled";
};
mac0: ethernet@800f0000 {
compatible = "fsl,imx28-fec";
reg = <0x800f0000 0x4000>;
interrupts = <101>;
2013-01-29 15:46:12 +01:00
clocks = <&clks 57>, <&clks 57>, <&clks 64>;
clock-names = "ipg", "ahb", "enet_out";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
mac1: ethernet@800f4000 {
compatible = "fsl,imx28-fec";
reg = <0x800f4000 0x4000>;
interrupts = <102>;
2012-08-22 21:36:29 +08:00
clocks = <&clks 57>, <&clks 57>;
clock-names = "ipg", "ahb";
2012-03-31 21:26:57 +08:00
status = "disabled";
};
2013-08-08 14:51:21 +02:00
etn_switch: switch@800f8000 {
2012-03-31 21:26:57 +08:00
reg = <0x800f8000 0x8000>;
status = "disabled";
};
};
2013-12-18 19:50:55 +01:00
2016-02-16 10:30:54 +05:30
iio-hwmon {
2013-12-18 19:50:55 +01:00
compatible = "iio-hwmon";
io-channels = <&lradc 8>;
};
2012-03-31 21:26:57 +08:00
};
