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linux/arch/arm/mach-keystone/keystone.c

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ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
/*
* Keystone2 based boards and SOC related code.
*
* Copyright 2013 Texas Instruments, Inc.
* Cyril Chemparathy <cyril@ti.com>
* Santosh Shilimkar <santosh.shillimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/init.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
ARM: keystone: Drop use of meminfo since its not available anymore Laura's series removed the meminfo structure and its no longer available. Update keystone code to remove the usage of it. Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-06-05 15:22:52 -04:00
#include <linux/memblock.h>
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
#include <asm/setup.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
ARM: keystone: Enable SMP support on Keystone machines Add basic SMP support for Keystone machines. This does not include support for CPU hotplug for now. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 12:20:17 -04:00
#include <asm/smp_plat.h>
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
#include <asm/memory.h>
#include "memory.h"
ARM: keystone: Enable SMP support on Keystone machines Add basic SMP support for Keystone machines. This does not include support for CPU hotplug for now. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 12:20:17 -04:00
#include "keystone.h"
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
ARM: keystone: Update the dma offset for non-dt platform devices Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-02-24 17:32:59 +02:00
static unsigned long keystone_dma_pfn_offset __read_mostly;
static int keystone_platform_notifier(struct notifier_block *nb,
unsigned long event, void *data)
{
struct device *dev = data;
if (event != BUS_NOTIFY_ADD_DEVICE)
return NOTIFY_DONE;
if (!dev)
return NOTIFY_BAD;
if (!dev->of_node) {
dev->dma_pfn_offset = keystone_dma_pfn_offset;
dev_err(dev, "set dma_pfn_offset%08lx\n",
dev->dma_pfn_offset);
}
return NOTIFY_OK;
}
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
ARM: keystone2: move platform notifier initialisation into platform init We ideally want the init_meminfo function to do nothing but return the delta to be applied to PHYS_OFFSET - it should do nothing else. As we can detect in platform init code whether we are running in the high physical address space, move the platform notifier initialisation entirely into the platform init code. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 11:30:04 +01:00
static struct notifier_block platform_nb = {
.notifier_call = keystone_platform_notifier,
};
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
static void __init keystone_init(void)
{
ARM: keystone2: move platform notifier initialisation into platform init We ideally want the init_meminfo function to do nothing but return the delta to be applied to PHYS_OFFSET - it should do nothing else. As we can detect in platform init code whether we are running in the high physical address space, move the platform notifier initialisation entirely into the platform init code. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 11:30:04 +01:00
if (PHYS_OFFSET >= KEYSTONE_HIGH_PHYS_START) {
keystone_dma_pfn_offset = PFN_DOWN(KEYSTONE_HIGH_PHYS_START -
KEYSTONE_LOW_PHYS_START);
ARM: keystone: Update the dma offset for non-dt platform devices Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-02-24 17:32:59 +02:00
bus_register_notifier(&platform_bus_type, &platform_nb);
ARM: keystone2: move platform notifier initialisation into platform init We ideally want the init_meminfo function to do nothing but return the delta to be applied to PHYS_OFFSET - it should do nothing else. As we can detect in platform init code whether we are running in the high physical address space, move the platform notifier initialisation entirely into the platform init code. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 11:30:04 +01:00
}
keystone_pm_runtime_init();
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
}
ARM: keystone2: rename init_meminfo to pv_fixup The init_meminfo() method is not about initialising meminfo - it's about fixing up the physical to virtual translation so that we use a different physical address space, possibly above the 4GB physical address space. Therefore, the name "init_meminfo()" is confusing. Rename it to pv_fixup() instead. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 10:01:10 +01:00
static long long __init keystone_pv_fixup(void)
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
{
ARM: keystone2: move update of the phys-to-virt constants into generic code Make the init_meminfo function return the offset to be applied to the phys-to-virt translation constants. This allows us to move the update into generic code, along with the requirements for this update. This avoids platforms having to know the details of the phys-to-virt translation support. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 09:53:38 +01:00
long long offset;
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
phys_addr_t mem_start, mem_end;
ARM: keystone: Drop use of meminfo since its not available anymore Laura's series removed the meminfo structure and its no longer available. Update keystone code to remove the usage of it. Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-06-05 15:22:52 -04:00
mem_start = memblock_start_of_DRAM();
mem_end = memblock_end_of_DRAM();
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
/* nothing to do if we are running out of the <32-bit space */
if (mem_start >= KEYSTONE_LOW_PHYS_START &&
mem_end <= KEYSTONE_LOW_PHYS_END)
ARM: keystone2: move update of the phys-to-virt constants into generic code Make the init_meminfo function return the offset to be applied to the phys-to-virt translation constants. This allows us to move the update into generic code, along with the requirements for this update. This avoids platforms having to know the details of the phys-to-virt translation support. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 09:53:38 +01:00
return 0;
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
if (mem_start < KEYSTONE_HIGH_PHYS_START ||
mem_end > KEYSTONE_HIGH_PHYS_END) {
pr_crit("Invalid address space for memory (%08llx-%08llx)\n",
ARM: keystone2: move update of the phys-to-virt constants into generic code Make the init_meminfo function return the offset to be applied to the phys-to-virt translation constants. This allows us to move the update into generic code, along with the requirements for this update. This avoids platforms having to know the details of the phys-to-virt translation support. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 09:53:38 +01:00
(u64)mem_start, (u64)mem_end);
return 0;
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
}
ARM: keystone2: move update of the phys-to-virt constants into generic code Make the init_meminfo function return the offset to be applied to the phys-to-virt translation constants. This allows us to move the update into generic code, along with the requirements for this update. This avoids platforms having to know the details of the phys-to-virt translation support. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 09:53:38 +01:00
offset = KEYSTONE_HIGH_PHYS_START - KEYSTONE_LOW_PHYS_START;
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
/* Populate the arch idmap hook */
ARM: provide improved virt_to_idmap() functionality For kexec, we need more functionality from the IDMAP system. We need to be able to convert physical addresses to their identity mappped versions as well as virtual addresses. Convert the existing arch_virt_to_idmap() to deal with physical addresses instead. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2016-03-15 14:55:03 +00:00
arch_phys_to_idmap_offset = -offset;
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
ARM: keystone2: move update of the phys-to-virt constants into generic code Make the init_meminfo function return the offset to be applied to the phys-to-virt translation constants. This allows us to move the update into generic code, along with the requirements for this update. This avoids platforms having to know the details of the phys-to-virt translation support. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 09:53:38 +01:00
return offset;
ARM: keystone: Switch over to coherent memory address space With late code patching updates for LPAE machines has merged now and memblock conversion from bootmem is on its way, Keystone can switch to the coherent memory address space which starts beyond 4GB boundary. The idmap alias needs are managed via virt_to_idmap() for boot purpose. Tested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-13 19:24:39 -04:00
}
ARM: make arrays containing machine compatible strings const The definition static const char *axxia_dt_match[] __initconst = { ... defines a changable array of constant strings. That is you must not do: *axxia_dt_match[0] = 'k'; but axxia_dt_match[0] = "different string"; is fine. So the annotation __initconst is wrong and yields a compiler error when other really const variables are added with __initconst. As the struct machine_desc member dt_compat is declared as const char *const *dt_compat; making the arrays const is the better alternative over changing all annotations to __initdata. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-02-18 21:01:45 +01:00
static const char *const keystone_match[] __initconst = {
ARM: keystone: Update compatible to have SoC specific matches With future SoCs of keystone2 family, the generic compatible match may not be sufficient to handle SoC specific handling. So introduce matches based on SoC compatiblity. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2015-10-03 17:02:56 -07:00
"ti,k2hk",
"ti,k2e",
"ti,k2l",
ARM: keystone: Create new binding for K2G SoC K2G SoC family is the newest version of the Keystone family of processors. The technical reference manual for K2G can be found here: http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf Add new bindings for K2G and the K2G evm. Also document these new bindings. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
2016-02-05 10:37:17 -08:00
"ti,k2g",
ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm As suggested by Olof Johansson at http://www.spinics.net/lists/arm-kernel/msg314009.html. It be better just keeping a "ti,keystone" top-level compatible and just using that to probe. If so we don't have to touch the file for new boards in the future. So use common "ti,keystone" compatible in keystone.c for all boards. Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Olof Johansson <olof@lixom.net> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-03-20 17:00:27 -04:00
"ti,keystone",
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
NULL,
};
DT_MACHINE_START(KEYSTONE, "Keystone")
ARM: keystone: enable DMA zone for LPAE Keystone II peripheral devices support 32-bit DMA and hence can access only first 2GB of the memory address space. So set the platform dma_zone_size to handle that case. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-11-23 16:58:03 -05:00
#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
.dma_zone_size = SZ_2G,
#endif
ARM: keystone: Enable SMP support on Keystone machines Add basic SMP support for Keystone machines. This does not include support for CPU hotplug for now. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 12:20:17 -04:00
.smp = smp_ops(keystone_smp_ops),
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
.init_machine = keystone_init,
.dt_compat = keystone_match,
ARM: keystone2: rename init_meminfo to pv_fixup The init_meminfo() method is not about initialising meminfo - it's about fixing up the physical to virtual translation so that we use a different physical address space, possibly above the 4GB physical address space. Therefore, the name "init_meminfo()" is confusing. Rename it to pv_fixup() instead. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-04 10:01:10 +01:00
.pv_fixup = keystone_pv_fixup,
ARM: keystone: Add minimal TI Keystone platform support Texas Instruments Keystone family of multi-core devices are based on ARM Cortex A15. Patch adds basic definitions for a new Keystone sub-architecture in ARM. The TCI66xxK2H Communications Infrastructure Keystone SoCs are member of the C66x family based on TI's new KeyStone 2 multi-core SoC Architecture designed specifically for high performance wireless and networking infrastructure applications. The SOCs contains many subsystems like Cortex A15 ARM CorePacs, C66XX DSP CorePacs, MSMC memory controller, Tera Net bus, IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers and queue based communication systems. Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-10 11:27:13 -04:00
MACHINE_END
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